schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
#endif
schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
-#if 0
+
/* Initialzie the timer queue */
- memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE);
+ memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE);
/* Initialize the timer control point */
memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
/* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
- /* Timer Registration request to SSI */
+ /* Timer Registration request to system services */
if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst,
(int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
{
"register timer.");
return (LCM_REASON_MEM_NOAVAIL);
}
-#endif
+
/* Set Config done in TskInit */
schCb[inst].schInit.cfgDone = TRUE;
DU_LOG("\nINFO --> SCH : Scheduler gen config done");
void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg)
{
uint16_t periodicityInMicroSec = 0;
- uint32_t slotBitPos, symbBitPos, bitMask;
int8_t slotIdx, symbIdx;
periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod);
cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000;
-cell->slotFrmtBitMap = 0;
+ cell->slotFrmtBitMap = 0;
cell->symbFrmtBitMap = 0;
- slotBitPos = (cell->numSlotsInPeriodicity*2)-1; /* considering 2 bits to represent a slot */
- symbBitPos = (MAX_SYMB_PER_SLOT*2)-1; /* considering 2 bits to represent a symbol */
for(slotIdx = cell->numSlotsInPeriodicity-1; slotIdx >= 0; slotIdx--)
{
symbIdx = 0;
case DL_SLOT:
{
/*BitMap to be set to 00 */
- bitMask = 1<<slotBitPos;
- cell->slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<<slotBitPos) & bitMask);
- slotBitPos--;
- bitMask = 1<<slotBitPos;
- cell->slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<<slotBitPos) & bitMask);
- slotBitPos--;
+ cell->slotFrmtBitMap = (cell->slotFrmtBitMap<<2);
break;
}
case UL_SLOT:
{
/*BitMap to be set to 01 */
- bitMask = 1<<slotBitPos;
- cell->slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<<slotBitPos) & bitMask);
- slotBitPos--;
- bitMask = 1<<slotBitPos;
- cell->slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((1<<slotBitPos) & bitMask);
- slotBitPos--;
+ cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (UL_SLOT));
break;
}
default:
continue;
}
/* slot config is flexible. First set slotBitMap to 10 */
- bitMask = 1<<slotBitPos;
- cell->slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((1<<slotBitPos) & bitMask);
- slotBitPos--;
- bitMask = 1<<slotBitPos;
- cell->slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<<slotBitPos) & bitMask);
- slotBitPos--;
+ cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (FLEXI_SLOT));
+
/* Now set symbol bitmap */
for(symbIdx = MAX_SYMB_PER_SLOT-1; symbIdx >= 0; symbIdx--)
{
case DL_SLOT:
{
/*symbol BitMap to be set to 00 */
- bitMask = 1<<symbBitPos;
- cell->symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<<symbBitPos) & bitMask);
- symbBitPos--;
- bitMask = 1<<symbBitPos;
- cell->symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<<symbBitPos) & bitMask);
- symbBitPos--;
+ cell->symbFrmtBitMap = (cell->symbFrmtBitMap<<2);
break;
}
case UL_SLOT:
{
/*symbol BitMap to be set to 01 */
- bitMask = 1<<symbBitPos;
- cell->symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<<symbBitPos) & bitMask);
- symbBitPos--;
- bitMask = 1<<symbBitPos;
- cell->symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((1<<symbBitPos) & bitMask);
- symbBitPos--;
+ cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (UL_SLOT));
break;
}
case FLEXI_SLOT:
{
/*symbol BitMap to be set to 10 */
- bitMask = 1<<symbBitPos;
- cell->symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((1<<symbBitPos) & bitMask);
- symbBitPos--;
- bitMask = 1<<symbBitPos;
- cell->symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<<symbBitPos) & bitMask);
- symbBitPos--;
+ cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (FLEXI_SLOT));
break;
}
default:
}
}
}
-
}
#endif
* uint8_t offsetPointA : offset
* @return void
**/
-void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
+void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
{
uint8_t coreset0Idx = 0;
uint8_t searchSpace0Idx = 0;
uint8_t slotIndex = 0;
uint8_t FreqDomainResource[6] = {0};
uint16_t tbSize = 0;
- uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
+ uint8_t numPdschSymbols = 11; /* considering pdsch region from symbols 3 to 13 */
+ uint8_t ssbIdx = 0;
PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
* [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
* assuming u = 0, i = 0, numSlotsPerSubframe = 10
* Also, from this configuration, coreset0 is only on even subframe */
- slotIndex = ((oValue * 1) + (0 * mValue)) % numSlots;
+ slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots;
sib1SchCfg->n0 = slotIndex;
/* calculate the PRBs */
pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
pdsch->codeword[cwCount].rvIndex = 0;
- tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen);
+ tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen + TX_PAYLOAD_HDR_LEN);
pdsch->codeword[cwCount].tbSize = tbSize;
}
pdsch->dataScramblingId = pci;
pdsch->numLayers = 1;
pdsch->transmissionScheme = 0;
pdsch->refPoint = 0;
- pdsch->dmrs.dlDmrsSymbPos = 2;
+ pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
pdsch->dmrs.dlDmrsScramblingId = pci;
pdsch->dmrs.scid = 0;
pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
- pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0,
+ pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0,
and PDSCH is always above SSB */
pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
pdsch->pdschTimeAlloc.rowIndex = 1;
- pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
+ /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */
+ pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
pdsch->beamPdschInfo.numPrgs = 1;
pdsch->beamPdschInfo.prgSize = 1;
cellCb->macInst = pst->srcInst;
/* derive the SIB1 config parameters */
- fillSchSib1Cfg(schCellCfg->bandwidth, cellCb->numSlots,
+ fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots,
&(schCellCfg->sib1SchCfg), schCellCfg->phyCellId,
schCellCfg->ssbSchCfg.ssbOffsetPointA);
memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
uint8_t lcId = 0;
uint16_t ueIdx = 0;
uint16_t slot;
+#ifdef NR_TDD
+ uint16_t slotIdx = 0;
+#endif
SchUeCb *ueCb = NULLP;
SchCellCb *cell = NULLP;
SchDlSlotInfo *schDlSlotInfo = NULLP;
return RFAILED;
}
- slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % cell->numSlots;
+ slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots;
+#ifdef NR_TDD
+ while(schGetSlotSymbFrmt(cell->slotFrmtBitMap, slot) != DL_SLOT)
+ {
+ slot = (slot + 1)%cell->numSlots;
+ slotIdx++;
+ if(slotIdx==cell->numSlots)
+ {
+ DU_LOG("\nERROR --> SCH : No DL Slot available");
+ return RFAILED;
+ }
+ }
+#endif
schDlSlotInfo = cell->schDlSlotInfo[slot];
SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo));