#include "du_app_mac_inf.h"
#include "mac_sch_interface.h"
#include "sch.h"
+#include "sch_utils.h"
#include "du_log.h"
-
extern SchCb schCb[SCH_MAX_INST];
+void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
/* local defines */
SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
{
packSchCellCfgCfm /* LWLC */
};
+
/**
* @brief Task Initiation function.
*
RETVALUE(ROK);
} /* macSchSlotInd */
+/*******************************************************************
+ *
+ * @brief Processes Rach indication from MAC
+ *
+ * @details
+ *
+ * Function : macSchRachInd
+ *
+ * Functionality:
+ * Processes Rach indication from MAC
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+int macSchRachInd(Pst *pst, RachIndInfo *rachInd)
+{
+ Inst inst = pst->dstInst-SCH_INST_START;
+ DU_LOG("\nSCH : Received Rach indication");
+ schProcessRachInd(rachInd, inst);
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief Processes CRC indication from MAC
+ *
+ * @details
+ *
+ * Function : macSchCrcInd
+ *
+ * Functionality:
+ * Processes CRC indication from MAC
+ *
+ * @params[in] Post structure
+ * Crc Indication
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+int macSchCrcInd(Pst *pst, CrcIndInfo *crcInd)
+{
+ switch(crcInd->crcInd[0])
+ {
+ case CRC_FAILED:
+ DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]");
+ break;
+ case CRC_PASSED:
+ DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]");
+ break;
+ default:
+ DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]);
+ return RFAILED;
+ }
+ return ROK;
+}
+
+
/**
* @brief inti cellCb based on cellCfg
*
cell->cellId = schCellCfg->cellId;
cell->instIdx = inst;
- switch(schCellCfg->scsCommon)
+ switch(schCellCfg->ssbSchCfg.scsCommon)
{
case SCH_SCS_15KHZ:
{
}
break;
default:
- DU_LOG("\nSCS %d not supported", schCellCfg->scsCommon);
+ DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon);
}
for(uint8_t idx=0; idx<SCH_NUM_SLOTS; idx++)
{
SchDlAlloc *schDlAlloc;
+ SchUlAlloc *schUlAlloc;
+
+ /* DL Alloc */
SCH_ALLOC(schDlAlloc, sizeof(SchDlAlloc));
if(!schDlAlloc)
{
return RFAILED;
}
- schDlAlloc->totalPrb = ((schCellCfg->bandwidth *
- 1000)/(schCellCfg->scsCommon))/SCH_NUM_SC_PRB;
- for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
+ /* UL Alloc */
+ SCH_ALLOC(schUlAlloc, sizeof(SchUlAlloc));
+ if(!schUlAlloc)
+ {
+ DU_LOG("\nMemory allocation failed in InitSchCellCb");
+ return RFAILED;
+ }
+
+ schDlAlloc->totalPrb = schUlAlloc->totalPrb = MAX_NUM_RB;
+
+ for(uint8_t itr=0; itr<SCH_SYMBOL_PER_SLOT; itr++)
{
schDlAlloc->assignedPrb[itr] = 0;
+ schUlAlloc->assignedPrb[itr] = 0;
}
+ schUlAlloc->schPuschInfo = NULLP;
+
for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
{
memset(&schDlAlloc->ssbInfo[itr], 0, sizeof(SsbInfo));
}
cell->dlAlloc[idx] = schDlAlloc;
+ cell->ulAlloc[idx] = schUlAlloc;
+
}
- schCb[inst].cells[inst] = cell; //Sphoorthi TODO: check if this works
+ schCb[inst].cells[inst] = cell;
DU_LOG("\nCell init completed for cellId:%d", cell->cellId);
return ROK;
}
+void fillSchSib1Cfg(
+Inst schInst,
+SchSib1Cfg *sib1SchCfg,
+uint16_t pci,
+uint8_t offsetPointA
+)
+{
+ uint8_t coreset0Idx = 0;
+ uint8_t searchSpace0Idx = 0;
+ //uint8_t ssbMuxPattern = 0;
+ uint8_t numRbs = 0;
+ uint8_t numSymbols = 0;
+ uint8_t offset = 0;
+ uint8_t oValue = 0;
+ //uint8_t numSearchSpacePerSlot = 0;
+ uint8_t mValue = 0;
+ uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
+ uint8_t slotIndex = 0;
+ uint8_t FreqDomainResource[6] = {0};
+
+ PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
+ PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
+
+ coreset0Idx = sib1SchCfg->coresetZeroIndex;
+ searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
+
+ /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
+ //ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
+ numRbs = coresetIdxTable[coreset0Idx][1];
+ numSymbols = coresetIdxTable[coreset0Idx][2];
+ offset = coresetIdxTable[coreset0Idx][3];
+
+ /* derive the search space params from table 13-11 spec 38.213 */
+ oValue = searchSpaceIdxTable[searchSpace0Idx][0];
+ //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
+ mValue = searchSpaceIdxTable[searchSpace0Idx][2];
+ firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
+
+ /* calculate the n0, need to add the formulae, as of now the value is 0
+ * Need to add the even and odd values of i during configuration
+ * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
+ * assuming u = 0, i = 0, numSlotsPerSubframe = 10
+ * Also, from this configuration, coreset0 is only on even subframe */
+ slotIndex = ((oValue * 1) + (0 * mValue)) % 10;
+ sib1SchCfg->n0 = slotIndex;
+
+ /* calculate the PRBs */
+ calculatePRB( ((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
+
+ /* fill the PDCCH PDU */
+ pdcch->pdcchBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
+ pdcch->pdcchBwpCfg.BWPStart = 0;
+ pdcch->pdcchBwpCfg.subcarrierSpacing = 0; /* 15Khz */
+ pdcch->pdcchBwpCfg.cyclicPrefix = 0; /* normal */
+ pdcch->coreset0Cfg.coreSet0Size = numRbs;
+ pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
+ pdcch->coreset0Cfg.durationSymbols = numSymbols;
+ memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
+ pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
+ pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->coreset0Cfg.coreSetType = 0;
+ pdcch->coreset0Cfg.shiftIndex = pci;
+ pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
+ pdcch->numDlDci = 1;
+ pdcch->dci.rnti = SI_RNTI;
+ pdcch->dci.scramblingId = pci;
+ pdcch->dci.scramblingRnti = 0;
+ pdcch->dci.cceIndex = 0;
+ pdcch->dci.aggregLevel = 4;
+ pdcch->dci.beamPdcchInfo.numPrgs = 1;
+ pdcch->dci.beamPdcchInfo.prgSize = 1;
+ pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
+ pdcch->dci.txPdcchPower.powerValue = 0;
+ pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
+ /* Storing pdschCfg pointer here. Required to access pdsch config while
+ fillig up pdcch pdu */
+ pdcch->dci.pdschCfg = pdsch;
+
+ /* fill the PDSCH PDU */
+ uint8_t cwCount = 0;
+ pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
+ pdsch->rnti = 0xFFFF; /* SI-RNTI */
+ pdsch->pduIndex = 0;
+ pdsch->pdschBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
+ pdsch->pdschBwpCfg.BWPStart = 0;
+ pdsch->numCodewords = 1;
+ for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
+ {
+ pdsch->codeword[cwCount].targetCodeRate = 308;
+ pdsch->codeword[cwCount].qamModOrder = 2;
+ pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
+ pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
+ pdsch->codeword[cwCount].rvIndex = 0;
+ pdsch->codeword[cwCount].tbSize = 768/8; /* 38.214: Table 5.1.3.2-1,
+ devided by 8 to get the value in bytes */
+ }
+ pdsch->dataScramblingId = pci;
+ pdsch->numLayers = 1;
+ pdsch->transmissionScheme = 0;
+ pdsch->refPoint = 0;
+ pdsch->dmrs.dlDmrsSymbPos = 2;
+ pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
+ pdsch->dmrs.dlDmrsScramblingId = pci;
+ pdsch->dmrs.scid = 0;
+ pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
+ pdsch->dmrs.dmrsPorts = 0;
+ pdsch->freqAlloc.resourceAlloc = 1; /* RAT type-1 RIV format */
+ pdsch->freqAlloc.rbStart = offset + SCH_SSB_PRB_DURATION; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
+ /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 *
+ * Ninfo = Nre . R . Qm . v *
+ * Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh *
+ * Nre = min(156,Nre') . nPrb */
+ pdsch->freqAlloc.rbSize = 10; /* This value is calculated from above formulae */
+ pdsch->freqAlloc.vrbPrbMapping = 0; /* non-interleaved */
+ pdsch->timeAlloc.rowIndex = 1;
+ pdsch->timeAlloc.startSymbolIndex = 2; /* spec-38.214, Table 5.1.2.1-1 */
+ pdsch->timeAlloc.numSymbols = 12;
+ pdsch->beamPdschInfo.numPrgs = 1;
+ pdsch->beamPdschInfo.prgSize = 1;
+ pdsch->beamPdschInfo.digBfInterfaces = 0;
+ pdsch->beamPdschInfo.prg[0].pmIdx = 0;
+ pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
+ pdsch->txPdschPower.powerControlOffset = 0;
+ pdsch->txPdschPower.powerControlOffsetSS = 0;
+
+}
+
/**
* @brief cell config from MAC to SCH.
*
Inst inst = pst->dstInst-1;
InitSchCellCb(inst, schCellCfg);
- cellCb = schCb[inst].cells[inst];
+ cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
cellCb->macInst = pst->srcInst;
+
+ /* derive the SIB1 config parameters */
+ fillSchSib1Cfg(
+ inst,
+ &(schCellCfg->sib1SchCfg),
+ schCellCfg->phyCellId,
+ schCellCfg->ssbSchCfg.ssbOffsetPointA);
memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
memset(&rspPst, 0, sizeof(Pst));
}
+/*******************************************************************
+ *
+ * @brief Processes DL RLC BO info from MAC
+ *
+ * @details
+ *
+ * Function : macSchDlRlcBoInfo
+ *
+ * Functionality:
+ * Processes DL RLC BO info from MAC
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t macSchDlRlcBoInfo(Pst *pst, DlRlcBOInfo *dlBoInfo)
+{
+ uint16_t lcIdx;
+ Inst inst = pst->dstInst-SCH_INST_START;
+ DU_LOG("\nSCH : Received RLC BO Status indication");
+
+ SchCellCb *cell = schCb[inst].cells[inst];
+ SchDlAlloc *dlAlloc = \
+ cell->dlAlloc[(cell->slotInfo.slot + SCHED_DELTA) % SCH_NUM_SLOTS];
+
+ for(lcIdx = 0; lcIdx < dlBoInfo->numLc; lcIdx++)
+ {
+ if(dlBoInfo->boInfo[lcIdx].lcId == CCCH_LCID)
+ {
+ SCH_ALLOC(dlAlloc->msg4Info, sizeof(Msg4Info));
+ if(!dlAlloc->msg4Info)
+ {
+ DU_LOG("\nSCH : Memory allocation failed for msg4Info");
+ dlAlloc = NULL;
+ return RFAILED;
+ }
+ dlAlloc->msg4Info->crnti = dlBoInfo->crnti;
+ dlAlloc->msg4Info->ndi = 1;
+ dlAlloc->msg4Info->harqProcNum = 0;
+ dlAlloc->msg4Info->dlAssignIdx = 0;
+ dlAlloc->msg4Info->pucchTpc = 0;
+ dlAlloc->msg4Info->pucchResInd = 0;
+ dlAlloc->msg4Info->harqFeedbackInd = 0;
+ dlAlloc->msg4Info->dciFormatId = 1;
+ }
+ }
+
+ return ROK;
+}
+
/**********************************************************************
End of file
**********************************************************************/
Code Review / o-du / l2.git / blobdiff