/** @file sch.c
@brief This file implements the schedulers main access to MAC layer code.
*/
-#include "stdbool.h"
-#include "envopt.h" /* environment options */
-#include "envdep.h" /* environment dependent */
-#include "envind.h" /* environment independent */
-#include "gen.h" /* general layer */
-#include "ssi.h" /* system service interface */
-#include "cm_tkns.h" /* Common Token Defines */
-#include "cm_llist.h" /* Common Link List Defines */
-#include "cm_hash.h" /* Common Hash List Defines */
-#include "cm_mblk.h" /* common memory link list library */
-#include "cm_lte.h" /* Common LTE Defines */
+#include "common_def.h"
+#include "du_app_mac_inf.h"
#include "lrg.h"
-#include "rgr.h"
#include "tfu.h"
+#include "du_log.h"
+#include "rgr.h"
#include "rg_sch_inf.h"
#include "rg_sch.h"
-#include "gen.x" /* general layer typedefs */
-#include "ssi.x" /* system services typedefs */
-#include "cm5.x" /* system services */
-#include "cm_tkns.x" /* Common Token Definitions */
-#include "cm_llist.x" /* Common Link List Definitions */
-#include "cm_lib.x" /* Common Library Definitions */
-#include "cm_hash.x" /* Common Hash List Definitions */
-#include "cm_mblk.x" /* common memory link list library */
-#include "cm_lte.x" /* Common LTE Defines */
+
#include "tfu.x" /* TFU types */
#include "lrg.x" /* layer management typedefs for MAC */
#include "rgr.x" /* layer management typedefs for MAC */
#include "rg_sch_inf.x" /* typedefs for Scheduler */
-#include "du_app_mac_inf.h"
#include "mac_sch_interface.h"
#include "sch.h"
#include "sch_utils.h"
-#include "du_log.h"
extern SchCb schCb[SCH_MAX_INST];
-extern int8_t coresetIdxTable[MAX_CORESET_INDEX][4];
-extern int8_t searchSpaceIdxTable[MAX_SEARCH_SPACE_INDEX][4];
+void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
/* local defines */
SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
{
- packSchCellCfgCfm, /* LC */
- MacProcSchCellCfgCfm, /* TC */
- packSchCellCfgCfm /* LWLC */
+ packSchCellCfgCfm, /* LC */
+ MacProcSchCellCfgCfm, /* TC */
+ packSchCellCfgCfm /* LWLC */
};
* @return int
* -# ROK
**/
-int schActvInit
-(
-Ent entity, /* entity */
-Inst instId, /* instance */
-Region region, /* region */
-Reason reason /* reason */
-)
+uint8_t schActvInit(Ent entity, Inst instId, Region region, Reason reason)
{
Inst inst = (instId - SCH_INST_START);
schCb[inst].schInit.trc = FALSE;
schCb[inst].schInit.procId = SFndProcId();
- RETVALUE(ROK);
+ return ROK;
} /* schActvInit */
/**
*
* Function : SchInstCfg
*
- * This function in called by HandleSchGenCfgReq(). It handles the
+ * This function in called by SchProcGenCfgReq(). It handles the
* general configurations of the scheduler instance. Returns
* reason for success/failure of this function.
*
* -# LCM_REASON_INVALID_MSGTYPE
* -# LCM_REASON_MEM_NOAVAIL
**/
-PUBLIC U16 SchInstCfg
-(
-RgCfg *cfg, /* Configuaration information */
-Inst dInst
-)
+PUBLIC U16 SchInstCfg(RgCfg *cfg, Inst dInst)
{
uint16_t ret = LCM_REASON_NOT_APPL;
Inst inst = (dInst - SCH_INST_START);
/* Check if Instance Configuration is done already */
if (schCb[inst].schInit.cfgDone == TRUE)
{
- RETVALUE(LCM_REASON_INVALID_MSGTYPE);
+ return LCM_REASON_INVALID_MSGTYPE;
}
/* Update the Pst structure for LM interface */
cmMemcpy((U8 *)&schCb[inst].schInit.lmPst,
- (U8 *)&cfg->s.schInstCfg.genCfg.lmPst,
- sizeof(Pst));
-
+ (U8 *)&cfg->s.schInstCfg.genCfg.lmPst,
+ sizeof(Pst));
+
schCb[inst].schInit.inst = inst;
schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId;
schCb[inst].schInit.lmPst.srcEnt = schCb[inst].schInit.ent;
schCb[inst].schInit.lmPst.srcInst = schCb[inst].schInit.inst +
- SCH_INST_START;
+ SCH_INST_START;
schCb[inst].schInit.lmPst.event = EVTNONE;
schCb[inst].schInit.region = cfg->s.schInstCfg.genCfg.mem.region;
/* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
/* Timer Registration request to SSI */
if (SRegTmrMt(schCb[inst].schInit.ent, dInst,
- (S16)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
+ (S16)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
{
RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "SchInstCfg(): Failed to "
- "register timer.");
+ "register timer.");
RETVALUE(LCM_REASON_MEM_NOAVAIL);
}
#endif
/* Set Config done in TskInit */
schCb[inst].schInit.cfgDone = TRUE;
printf("\nScheduler gen config done");
-
- RETVALUE(ret);
+
+ return ret;
}
/**
*
* @details
*
- * Function : HandleSchGenCfgReq
+ * Function : SchProcGenCfgReq
*
* This function handles the configuration
* request received at scheduler instance from the Layer Manager.
* @return S16
* -# ROK
**/
-int HandleSchGenCfgReq
-(
-Pst *pst, /* post structure */
-RgMngmt *cfg /* config structure */
-)
+int SchProcGenCfgReq(Pst *pst, RgMngmt *cfg)
{
uint16_t ret = LCM_PRIM_OK;
uint16_t reason = LCM_REASON_NOT_APPL;
if(pst->dstInst < SCH_INST_START)
{
DU_LOG("\nInvalid inst ID");
- DU_LOG("\nHandleSchGenCfgReq(): "
- "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
- RETVALUE(ROK);
+ DU_LOG("\nSchProcGenCfgReq(): "
+ "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
+ return ROK;
}
printf("\nReceived scheduler gen config");
/* Fill the post structure for sending the confirmation */
- memset(&cfmPst, 0 , sizeof(Pst));
+ memset(&cfmPst, 0 , sizeof(Pst));
SchFillCfmPst(pst, &cfmPst, cfg);
cmMemset((U8 *)&cfm, 0, sizeof(RgMngmt));
switch(cfg->hdr.elmId.elmnt)
{
case STSCHINST:
- reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
- break;
+ reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
+ break;
default:
- ret = LCM_PRIM_NOK;
- reason = LCM_REASON_INVALID_ELMNT;
- DU_LOG("\nInvalid Elmnt=%d", cfg->hdr.elmId.elmnt);
- break;
+ ret = LCM_PRIM_NOK;
+ reason = LCM_REASON_INVALID_ELMNT;
+ DU_LOG("\nInvalid Elmnt=%d", cfg->hdr.elmId.elmnt);
+ break;
}
if (reason != LCM_REASON_NOT_APPL)
SchSendCfgCfm(&cfmPst, &cfm);
/* SPutSBuf(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */
-
- RETVALUE(ROK);
-}/*-- HandleSchGenCfgReq --*/
+
+ return ROK;
+}/*-- SchProcGenCfgReq --*/
/**
* @brief slot indication from MAC to SCH.
* -# ROK
* -# RFAILED
**/
-int macSchSlotInd
-(
-Pst *pst,
-SlotIndInfo *slotInd
-)
+uint8_t macSchSlotInd(Pst *pst, SlotIndInfo *slotInd)
{
Inst inst = pst->dstInst-SCH_INST_START;
/* Now call the TOM (Tfu ownership module) primitive to process further */
schProcessSlotInd(slotInd, inst);
- RETVALUE(ROK);
+ return ROK;
} /* macSchSlotInd */
+/*******************************************************************
+ *
+ * @brief Processes Rach indication from MAC
+ *
+ * @details
+ *
+ * Function : macSchRachInd
+ *
+ * Functionality:
+ * Processes Rach indication from MAC
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t macSchRachInd(Pst *pst, RachIndInfo *rachInd)
+{
+ Inst inst = pst->dstInst-SCH_INST_START;
+ DU_LOG("\nSCH : Received Rach indication");
+ schProcessRachInd(rachInd, inst);
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief Processes CRC indication from MAC
+ *
+ * @details
+ *
+ * Function : macSchCrcInd
+ *
+ * Functionality:
+ * Processes CRC indication from MAC
+ *
+ * @params[in] Post structure
+ * Crc Indication
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t macSchCrcInd(Pst *pst, CrcIndInfo *crcInd)
+{
+ switch(crcInd->crcInd[0])
+ {
+ case CRC_FAILED:
+ DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]");
+ break;
+ case CRC_PASSED:
+ DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]");
+ break;
+ default:
+ DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]);
+ return RFAILED;
+ }
+ return ROK;
+}
+
+
/**
* @brief inti cellCb based on cellCfg
*
{
SchCellCb *cell;
SCH_ALLOC(cell, sizeof(SchCellCb));
- if(!cell)
- {
+ if(!cell)
+ {
DU_LOG("\nMemory allocation failed in InitSchCellCb");
- return RFAILED;
- }
-
- cell->cellId = schCellCfg->cellId;
- cell->instIdx = inst;
- switch(schCellCfg->ssbSchCfg.scsCommon)
- {
- case SCH_SCS_15KHZ:
- {
- cell->numSlots = SCH_NUM_SLOTS;
- }
- break;
- default:
- DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon);
- }
-
+ return RFAILED;
+ }
+
+ cell->cellId = schCellCfg->cellId;
+ cell->instIdx = inst;
+ switch(schCellCfg->ssbSchCfg.scsCommon)
+ {
+ case SCH_SCS_15KHZ:
+ {
+ cell->numSlots = SCH_NUM_SLOTS;
+ }
+ break;
+ default:
+ DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon);
+ }
+
for(uint8_t idx=0; idx<SCH_NUM_SLOTS; idx++)
- {
- SchDlAlloc *schDlAlloc;
- SCH_ALLOC(schDlAlloc, sizeof(SchDlAlloc));
- if(!schDlAlloc)
- {
- DU_LOG("\nMemory allocation failed in InitSchCellCb");
- return RFAILED;
- }
-
- schDlAlloc->totalPrb = MAX_NUM_RB;
-
- for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
- {
- schDlAlloc->assignedPrb[itr] = 0;
- }
- for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
- {
- memset(&schDlAlloc->ssbInfo[itr], 0, sizeof(SsbInfo));
- }
-
- cell->dlAlloc[idx] = schDlAlloc;
- }
- schCb[inst].cells[inst] = cell; //Sphoorthi TODO: check if this works
+ {
+ SchDlSlotInfo *schDlSlotInfo;
+ SchUlSlotInfo *schUlSlotInfo;
+
+ /* DL Alloc */
+ SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo));
+ if(!schDlSlotInfo)
+ {
+ DU_LOG("\nMemory allocation failed in InitSchCellCb");
+ return RFAILED;
+ }
+
+ /* UL Alloc */
+ SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo));
+ if(!schUlSlotInfo)
+ {
+ DU_LOG("\nMemory allocation failed in InitSchCellCb");
+ return RFAILED;
+ }
+
+ memset(schDlSlotInfo, 0, sizeof(SchDlSlotInfo));
+ memset(schUlSlotInfo, 0, sizeof(SchUlSlotInfo));
+
+ schDlSlotInfo->totalPrb = schUlSlotInfo->totalPrb = MAX_NUM_RB;
+
+ for(uint8_t itr=0; itr<SCH_SYMBOL_PER_SLOT; itr++)
+ {
+ schDlSlotInfo->assignedPrb[itr] = 0;
+ schUlSlotInfo->assignedPrb[itr] = 0;
+ }
+ schUlSlotInfo->schPuschInfo = NULLP;
+
+ for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
+ {
+ memset(&schDlSlotInfo->ssbInfo[itr], 0, sizeof(SsbInfo));
+ }
+
+ cell->schDlSlotInfo[idx] = schDlSlotInfo;
+ cell->schUlSlotInfo[idx] = schUlSlotInfo;
+
+ }
+ schCb[inst].cells[inst] = cell;
DU_LOG("\nCell init completed for cellId:%d", cell->cellId);
return ROK;
}
-void fillSchSib1Cfg(
-Inst schInst,
-SchSib1Cfg *sib1SchCfg,
-uint8_t pci,
-uint8_t offsetPointA
-)
+/**
+ * @brief Fill SIB1 configuration
+ *
+ * @details
+ *
+ * Function : fillSchSib1Cfg
+ *
+ * Fill SIB1 configuration
+ *
+ * @param[in] Inst schInst : scheduler instance
+ * SchSib1Cfg *sib1SchCfg : cfg to be filled
+ * uint16_t pci : physical cell Id
+ * uint8_t offsetPointA : offset
+ * @return void
+ **/
+void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \
+ uint8_t offsetPointA)
{
uint8_t coreset0Idx = 0;
uint8_t searchSpace0Idx = 0;
- uint8_t ssbMuxPattern = 0;
+ //uint8_t ssbMuxPattern = 0;
uint8_t numRbs = 0;
uint8_t numSymbols = 0;
uint8_t offset = 0;
uint8_t oValue = 0;
- uint8_t numSearchSpacePerSlot = 0;
+ //uint8_t numSearchSpacePerSlot = 0;
uint8_t mValue = 0;
uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
uint8_t slotIndex = 0;
uint8_t FreqDomainResource[6] = {0};
+ uint16_t tbSize = 0;
+ uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
- Sib1PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
- Sib1PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
+ PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
+ PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
+ BwpCfg *bwp = &(sib1SchCfg->bwp);
coreset0Idx = sib1SchCfg->coresetZeroIndex;
searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
/* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
- ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
+ //ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
numRbs = coresetIdxTable[coreset0Idx][1];
numSymbols = coresetIdxTable[coreset0Idx][2];
offset = coresetIdxTable[coreset0Idx][3];
/* derive the search space params from table 13-11 spec 38.213 */
oValue = searchSpaceIdxTable[searchSpace0Idx][0];
- numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
+ //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
mValue = searchSpaceIdxTable[searchSpace0Idx][2];
firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
* Also, from this configuration, coreset0 is only on even subframe */
slotIndex = ((oValue * 1) + (0 * mValue)) % 10;
sib1SchCfg->n0 = slotIndex;
-
+
/* calculate the PRBs */
- freqDomResourceAlloc( ((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
+ schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
+
+ /* fill BWP */
+ bwp->freqAlloc.numPrb = MAX_NUM_RB; /* whole of BW */
+ bwp->freqAlloc.startPrb = 0;
+ bwp->subcarrierSpacing = 0; /* 15Khz */
+ bwp->cyclicPrefix = 0; /* normal */
/* fill the PDCCH PDU */
- pdcch->sib1PdcchBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
- pdcch->sib1PdcchBwpCfg.BWPStart = 0;
- pdcch->sib1PdcchBwpCfg.subcarrierSpacing = 0; /* 15Khz */
- pdcch->sib1PdcchBwpCfg.cyclicPrefix = 0; /* normal */
- pdcch->sib1Coreset0Cfg.coreSet0Size = numRbs;
- pdcch->sib1Coreset0Cfg.startSymbolIndex = firstSymbol;
- pdcch->sib1Coreset0Cfg.durationSymbols = numSymbols;
- memcpy(pdcch->sib1Coreset0Cfg.freqDomainResource,FreqDomainResource,6);
- pdcch->sib1Coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
- pdcch->sib1Coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
- pdcch->sib1Coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
- pdcch->sib1Coreset0Cfg.coreSetType = 0;
- pdcch->sib1Coreset0Cfg.shiftIndex = pci;
- pdcch->sib1Coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
+ pdcch->coreset0Cfg.coreSet0Size = numRbs;
+ pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
+ pdcch->coreset0Cfg.durationSymbols = numSymbols;
+ memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
+ pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
+ pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->coreset0Cfg.coreSetType = 0;
+ pdcch->coreset0Cfg.shiftIndex = pci;
+ pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
pdcch->numDlDci = 1;
- pdcch->sib1DlDci.rnti = 0xFFFF; /* SI-RNTI */
- pdcch->sib1DlDci.scramblingId = pci;
- pdcch->sib1DlDci.scramblingRnti = 0;
- pdcch->sib1DlDci.cceIndex = 0;
- pdcch->sib1DlDci.aggregLevel = 4;
- pdcch->sib1DlDci.beamPdcchInfo.numPrgs = 1;
- pdcch->sib1DlDci.beamPdcchInfo.prgSize = 1;
- pdcch->sib1DlDci.beamPdcchInfo.digBfInterfaces = 0;
- pdcch->sib1DlDci.beamPdcchInfo.prg[0].pmIdx = 0;
- pdcch->sib1DlDci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
- pdcch->sib1DlDci.txPdcchPower.powerValue = 0;
- pdcch->sib1DlDci.txPdcchPower.powerControlOffsetSS = 0;
- /* Storing pdschCfg pointer here. Required to access pdsch config while
- fillig up pdcch pdu */
- pdcch->sib1DlDci.pdschCfg = pdsch;
+ pdcch->dci.rnti = SI_RNTI;
+ pdcch->dci.scramblingId = pci;
+ pdcch->dci.scramblingRnti = 0;
+ pdcch->dci.cceIndex = 0;
+ pdcch->dci.aggregLevel = 4;
+ pdcch->dci.beamPdcchInfo.numPrgs = 1;
+ pdcch->dci.beamPdcchInfo.prgSize = 1;
+ pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
+ pdcch->dci.txPdcchPower.powerValue = 0;
+ pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
+ /* Storing pdschCfg pointer here. Required to access pdsch config while
+ fillig up pdcch pdu */
+ pdcch->dci.pdschCfg = pdsch;
/* fill the PDSCH PDU */
- uint8_t cwCount = 0;
+ uint8_t cwCount = 0;
pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
pdsch->rnti = 0xFFFF; /* SI-RNTI */
pdsch->pduIndex = 0;
- pdsch->sib1PdschBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
- pdsch->sib1PdschBwpCfg.BWPStart = 0;
pdsch->numCodewords = 1;
- for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
- {
+ for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
+ {
pdsch->codeword[cwCount].targetCodeRate = 308;
pdsch->codeword[cwCount].qamModOrder = 2;
pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
pdsch->codeword[cwCount].rvIndex = 0;
- pdsch->codeword[cwCount].tbSize = 768;
+ tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen);
+ pdsch->codeword[cwCount].tbSize = tbSize;
+ }
+ pdsch->dataScramblingId = pci;
+ pdsch->numLayers = 1;
+ pdsch->transmissionScheme = 0;
+ pdsch->refPoint = 0;
+ pdsch->dmrs.dlDmrsSymbPos = 2;
+ pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
+ pdsch->dmrs.dlDmrsScramblingId = pci;
+ pdsch->dmrs.scid = 0;
+ pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
+ pdsch->dmrs.dmrsPorts = 0;
+ pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
+ pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
+ pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
+
+ pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
+ pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0,
+ and PDSCH is always above SSB */
+ pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
+ pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
+ pdsch->pdschTimeAlloc.rowIndex = 1;
+ pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
+ pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
+ pdsch->beamPdschInfo.numPrgs = 1;
+ pdsch->beamPdschInfo.prgSize = 1;
+ pdsch->beamPdschInfo.digBfInterfaces = 0;
+ pdsch->beamPdschInfo.prg[0].pmIdx = 0;
+ pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
+ pdsch->txPdschPower.powerControlOffset = 0;
+ pdsch->txPdschPower.powerControlOffsetSS = 0;
+
+}
+
+/**
+ * @brief Fill SSB start symbol
+ *
+ * @details
+ *
+ * Function : fillSsbStartSymb
+ *
+ * This API stores SSB start index per beam
+ *
+ * @param[in] SchCellCb *cellCb
+ * @return int
+ * -# ROK
+ * -# RFAILED
+ **/
+void fillSsbStartSymb(SchCellCb *cellCb)
+{
+ uint8_t cnt, scs;
+
+ scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
+ uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM];
+
+ memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
+ /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
+ switch(scs)
+ {
+ case SCH_SCS_15KHZ:
+ {
+ uint8_t symbIdx=0;
+ cnt = 2;/* n = 0, 1 for SCS = 15KHz */
+ for(uint8_t idx=0; idx<cnt; idx++)
+ {
+ /* start symbol determined using {2, 8} + 14n */
+ ssbStartSymbArr[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
+ ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
+ }
+ }
+ break;
+ default:
+ DU_LOG("\nSCS %d is currently not supported", scs);
}
- pdsch->dataScramblingId = pci;
- pdsch->numLayers = 1;
- pdsch->transmissionScheme = 0;
- pdsch->refPoint = 0;
- pdsch->dmrs.dlDmrsSymbPos = 2;
- pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
- pdsch->dmrs.dlDmrsScramblingId = pci;
- pdsch->dmrs.scid = 0;
- pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
- pdsch->dmrs.dmrsPorts = 0;
- pdsch->sib1FreqAlloc.resourceAlloc = 1; /* RAT type-1 RIV format */
- pdsch->sib1FreqAlloc.rbStart = offset + SCH_SSB_PRB_DURATION; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
- /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 *
- * Ninfo = Nre . R . Qm . v *
- * Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh *
- * Nre = min(156,Nre') . nPrb */
- pdsch->sib1FreqAlloc.rbSize = 10; /* This value is calculated from above formulae */
- pdsch->sib1FreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
- pdsch->sib1TimeAlloc.rowIndex = 1;
- pdsch->sib1TimeAlloc.startSymbolIndex = 2; /* spec-38.214, Table 5.1.2.1-1 */
- pdsch->sib1TimeAlloc.numSymbols = 12;
- pdsch->beamPdschInfo.numPrgs = 1;
- pdsch->beamPdschInfo.prgSize = 1;
- pdsch->beamPdschInfo.digBfInterfaces = 0;
- pdsch->beamPdschInfo.prg[0].pmIdx = 0;
- pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
- pdsch->txPdschPower.powerControlOffset = 0;
- pdsch->txPdschPower.powerControlOffsetSS = 0;
+ memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
+ memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
}
* -# ROK
* -# RFAILED
**/
-int SchHdlCellCfgReq
-(
-Pst *pst,
-SchCellCfg *schCellCfg
-)
+uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg)
{
- int ret = ROK;
+ uint8_t ret = ROK;
SchCellCb *cellCb;
- SchCellCfgCfm schCellCfgCfm;
- Pst rspPst;
- Inst inst = pst->dstInst-1;
+ SchCellCfgCfm schCellCfgCfm;
+ Pst rspPst;
+ Inst inst = pst->dstInst-1;
- InitSchCellCb(inst, schCellCfg);
- cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
+ InitSchCellCb(inst, schCellCfg);
+ cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
cellCb->macInst = pst->srcInst;
/* derive the SIB1 config parameters */
- fillSchSib1Cfg(
- inst,
- &(schCellCfg->sib1SchCfg),
- schCellCfg->phyCellId,
- schCellCfg->ssbSchCfg.ssbOffsetPointA);
+ fillSchSib1Cfg(
+ inst,
+ &(schCellCfg->sib1SchCfg),
+ schCellCfg->phyCellId,
+ schCellCfg->ssbSchCfg.ssbOffsetPointA);
memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
+ /* Fill and send Cell config confirm */
memset(&rspPst, 0, sizeof(Pst));
- SCH_FILL_RSP_PST(rspPst, inst);
- rspPst.event = EVENT_SCH_CELL_CFG_CFM;
- schCellCfgCfm.rsp = RSP_OK;
-
+ FILL_PST_SCH_TO_MAC(rspPst, pst->dstInst);
+ rspPst.event = EVENT_SCH_CELL_CFG_CFM;
+
+ schCellCfgCfm.cellId = schCellCfg->cellId;
+ schCellCfgCfm.rsp = RSP_OK;
+
ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm);
return ret;
}
+/*******************************************************************
+ *
+ * @brief Processes DL RLC BO info from MAC
+ *
+ * @details
+ *
+ * Function : macSchDlRlcBoInfo
+ *
+ * Functionality:
+ * Processes DL RLC BO info from MAC
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t macSchDlRlcBoInfo(Pst *pst, DlRlcBOInfo *dlBoInfo)
+{
+ uint16_t lcIdx;
+ Inst inst = pst->dstInst-SCH_INST_START;
+ DU_LOG("\nSCH : Received RLC BO Status indication");
+
+ SchCellCb *cell = schCb[inst].cells[inst];
+ SchDlSlotInfo *schDlSlotInfo = \
+ cell->schDlSlotInfo[(cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + MSG4_DELAY) % SCH_NUM_SLOTS];
+
+ for(lcIdx = 0; lcIdx < dlBoInfo->numLc; lcIdx++)
+ {
+ if(dlBoInfo->boInfo[lcIdx].lcId == CCCH_LCID)
+ {
+ SCH_ALLOC(schDlSlotInfo->msg4Info, sizeof(Msg4Info));
+ if(!schDlSlotInfo->msg4Info)
+ {
+ DU_LOG("\nSCH : Memory allocation failed for msg4Info");
+ schDlSlotInfo = NULL;
+ return RFAILED;
+ }
+ schDlSlotInfo->msg4Info->crnti = dlBoInfo->crnti;
+ schDlSlotInfo->msg4Info->ndi = 1;
+ schDlSlotInfo->msg4Info->harqProcNum = 0;
+ schDlSlotInfo->msg4Info->dlAssignIdx = 0;
+ schDlSlotInfo->msg4Info->pucchTpc = 0;
+ schDlSlotInfo->msg4Info->pucchResInd = 0;
+ schDlSlotInfo->msg4Info->harqFeedbackInd = 0;
+ schDlSlotInfo->msg4Info->dciFormatId = 1;
+ }
+ }
+
+ return ROK;
+}
+
/**********************************************************************
- End of file
-**********************************************************************/
+ End of file
+ **********************************************************************/
Code Review / o-du / l2.git / blobdiff