schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
#endif
schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
-#if 0
+
/* Initialzie the timer queue */
- memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE);
+ memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE);
/* Initialize the timer control point */
memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
/* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
- /* Timer Registration request to SSI */
+ /* Timer Registration request to system services */
if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst,
(int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
{
"register timer.");
return (LCM_REASON_MEM_NOAVAIL);
}
-#endif
+
/* Set Config done in TskInit */
schCb[inst].schInit.cfgDone = TRUE;
DU_LOG("\nINFO --> SCH : Scheduler gen config done");
pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
- pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0,
+ pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0,
and PDSCH is always above SSB */
pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
return RFAILED;
}
- slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % cell->numSlots;
+ slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots;
schDlSlotInfo = cell->schDlSlotInfo[slot];
SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo));