uint16_t ret = LCM_REASON_NOT_APPL;
Inst inst = (dInst - SCH_INST_START);
- printf("\nEntered SchInstCfg()");
+ DU_LOG("\nDEBUG --> SCH : Entered SchInstCfg()");
/* Check if Instance Configuration is done already */
if (schCb[inst].schInit.cfgDone == TRUE)
{
schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
#endif
schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
-#if 0
+
/* Initialzie the timer queue */
- memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE);
+ memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE);
/* Initialize the timer control point */
memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
/* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
- /* Timer Registration request to SSI */
+ /* Timer Registration request to system services */
if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst,
(int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
{
- RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "SchInstCfg(): Failed to "
+ DU_LOG("\nERROR --> SCH : SchInstCfg(): Failed to "
"register timer.");
return (LCM_REASON_MEM_NOAVAIL);
}
-#endif
+
/* Set Config done in TskInit */
schCb[inst].schInit.cfgDone = TRUE;
- printf("\nScheduler gen config done");
+ DU_LOG("\nINFO --> SCH : Scheduler gen config done");
return ret;
}
"pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
return ROK;
}
- printf("\nSCH : Received scheduler gen config");
+ DU_LOG("\nINFO --> SCH : Received scheduler gen config");
/* Fill the post structure for sending the confirmation */
memset(&cfmPst, 0 , sizeof(Pst));
SchFillCfmPst(pst, &cfmPst, cfg);
return ROK;
}
+#ifdef NR_TDD
+/**
+ *@brief Returns TDD periodicity in micro seconds
+ *
+ * @details
+ *
+ * Function : schGetPeriodicityInMsec
+ *
+ * This API retunrs TDD periodicity in micro seconds
+ *
+ * @param[in] DlUlTxPeriodicity
+ * @return periodicityInMsec
+ * **/
+
+uint16_t schGetPeriodicityInMsec(DlUlTxPeriodicity tddPeriod)
+{
+ uint16_t periodicityInMsec = 0;
+ switch(tddPeriod)
+ {
+ case TX_PRDCTY_MS_0P5:
+ {
+ periodicityInMsec = 500;
+ break;
+ }
+ case TX_PRDCTY_MS_0P625:
+ {
+ periodicityInMsec = 625;
+ break;
+ }
+ case TX_PRDCTY_MS_1:
+ {
+ periodicityInMsec = 1000;
+ break;
+ }
+ case TX_PRDCTY_MS_1P25:
+ {
+ periodicityInMsec = 1250;
+ break;
+ }
+ case TX_PRDCTY_MS_2:
+ {
+ periodicityInMsec = 2000;
+ break;
+ }
+ case TX_PRDCTY_MS_2P5:
+ {
+ periodicityInMsec = 2500;
+ break;
+ }
+ case TX_PRDCTY_MS_5:
+ {
+ periodicityInMsec = 5000;
+ break;
+ }
+ case TX_PRDCTY_MS_10:
+ {
+ periodicityInMsec = 10000;
+ break;
+ }
+ default:
+ {
+ DU_LOG("\nERROR --> SCH : Invalid DlUlTxPeriodicity:%d", tddPeriod);
+ }
+ }
+
+ return periodicityInMsec;
+}
+
+
+/**
+ * @brief init TDD slot config
+ *
+ * @details
+ *
+ * Function : schInitTddSlotCfg
+ *
+ * This API is invoked after receiving schCellCfg
+ *
+ * @param[in] schCellCb *cell
+ * @param[in] SchCellCfg *schCellCfg
+ * @return void
+ **/
+void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg)
+{
+ uint16_t periodicityInMicroSec = 0;
+ int8_t slotIdx, symbIdx;
+
+ periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod);
+ cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000;
+ cell->slotFrmtBitMap = 0;
+ cell->symbFrmtBitMap = 0;
+ for(slotIdx = cell->numSlotsInPeriodicity-1; slotIdx >= 0; slotIdx--)
+ {
+ symbIdx = 0;
+ /* If the first and last symbol are the same, the entire slot is the same type */
+ if((schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] == schCellCfg->tddCfg.slotCfg[slotIdx][MAX_SYMB_PER_SLOT-1]) &&
+ schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] != FLEXI_SLOT)
+ {
+ switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
+ {
+ case DL_SLOT:
+ {
+ /*BitMap to be set to 00 */
+ cell->slotFrmtBitMap = (cell->slotFrmtBitMap<<2);
+ break;
+ }
+ case UL_SLOT:
+ {
+ /*BitMap to be set to 01 */
+ cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (UL_SLOT));
+ break;
+ }
+ default:
+ DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
+ }
+ continue;
+ }
+ /* slot config is flexible. First set slotBitMap to 10 */
+ cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (FLEXI_SLOT));
+
+ /* Now set symbol bitmap */
+ for(symbIdx = MAX_SYMB_PER_SLOT-1; symbIdx >= 0; symbIdx--)
+ {
+ switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
+ {
+ case DL_SLOT:
+ {
+ /*symbol BitMap to be set to 00 */
+ cell->symbFrmtBitMap = (cell->symbFrmtBitMap<<2);
+ break;
+ }
+ case UL_SLOT:
+ {
+ /*symbol BitMap to be set to 01 */
+ cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (UL_SLOT));
+ break;
+ }
+ case FLEXI_SLOT:
+ {
+ /*symbol BitMap to be set to 10 */
+ cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (FLEXI_SLOT));
+ break;
+ }
+ default:
+ DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
+ }
+ }
+ }
+}
+#endif
/**
- * @brief inti cellCb based on cellCfg
+ * @brief Fill SSB start symbol
+ *
+ * @details
+ *
+ * Function : fillSsbStartSymb
+ *
+ * This API stores SSB start index per beam
+ *
+ * @param[in] SchCellCb *cellCb
+ * @return int
+ * -# ROK
+ * -# RFAILED
+ **/
+void fillSsbStartSymb(SchCellCb *cellCb)
+{
+ uint8_t cnt, scs, symbIdx, ssbStartSymbArr[SCH_MAX_SSB_BEAM];
+
+ scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
+
+ memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
+ symbIdx = 0;
+ /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
+ switch(scs)
+ {
+ case SCS_15KHZ:
+ {
+ if(cellCb->cellCfg.dlFreq <= 300000)
+ cnt = 2;/* n = 0, 1 */
+ else
+ cnt = 4; /* n = 0, 1, 2, 3 */
+ for(uint8_t idx=0; idx<cnt; idx++)
+ {
+ /* start symbol determined using {2, 8} + 14n */
+ ssbStartSymbArr[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
+ ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
+ }
+ }
+ break;
+ case SCS_30KHZ:
+ {
+ if(cellCb->cellCfg.dlFreq <= 300000)
+ cnt = 1;/* n = 0 */
+ else
+ cnt = 2; /* n = 0, 1 */
+ for(uint8_t idx=0; idx<cnt; idx++)
+ {
+ /* start symbol determined using {4, 8, 16, 20} + 28n */
+ ssbStartSymbArr[symbIdx++] = 4 + SCH_SYMBOL_PER_SLOT*idx;
+ ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
+ ssbStartSymbArr[symbIdx++] = 16 + SCH_SYMBOL_PER_SLOT*idx;
+ ssbStartSymbArr[symbIdx++] = 20 + SCH_SYMBOL_PER_SLOT*idx;
+ }
+ }
+ break;
+ default:
+ DU_LOG("\nERROR --> SCH : SCS %d is currently not supported", scs);
+ }
+ memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
+ memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
+
+}
+
+
+/**
+ * @brief init cellCb based on cellCfg
*
* @details
*
**/
uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg)
{
- SchCellCb *cell;
+ SchCellCb *cell= NULLP;
SCH_ALLOC(cell, sizeof(SchCellCb));
if(!cell)
{
default:
DU_LOG("\nERROR --> SCH : Numerology %d not supported", schCellCfg->numerology);
}
+#ifdef NR_TDD
+ schInitTddSlotCfg(cell, schCellCfg);
+#endif
SCH_ALLOC(cell->schDlSlotInfo, cell->numSlots * sizeof(SchDlSlotInfo*));
if(!cell->schDlSlotInfo)
cell->schUlSlotInfo[idx] = schUlSlotInfo;
}
+ cell->firstSsbTransmitted = false;
+ cell->firstSib1Transmitted = false;
+ fillSsbStartSymb(cell);
schCb[inst].cells[inst] = cell;
DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId);
* uint8_t offsetPointA : offset
* @return void
**/
-void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
+void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
{
uint8_t coreset0Idx = 0;
uint8_t searchSpace0Idx = 0;
uint8_t mValue = 0;
uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
uint8_t slotIndex = 0;
- uint8_t FreqDomainResource[6] = {0};
+ /* TODO : This should be filled through freqDomRscAllocType0() */
+ uint8_t FreqDomainResource[6] = {15, 0, 0, 0, 0, 0};
uint16_t tbSize = 0;
- uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
+ uint8_t numPdschSymbols = 11; /* considering pdsch region from symbols 3 to 13 */
+ uint8_t ssbIdx = 0;
PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
* [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
* assuming u = 0, i = 0, numSlotsPerSubframe = 10
* Also, from this configuration, coreset0 is only on even subframe */
- slotIndex = ((oValue * 1) + (0 * mValue)) % numSlots;
+ slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots;
sib1SchCfg->n0 = slotIndex;
/* calculate the PRBs */
- freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
+ //freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
/* fill BWP */
switch(bandwidth)
pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
pdsch->codeword[cwCount].rvIndex = 0;
- tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen);
+ tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen + TX_PAYLOAD_HDR_LEN);
pdsch->codeword[cwCount].tbSize = tbSize;
}
pdsch->dataScramblingId = pci;
pdsch->numLayers = 1;
pdsch->transmissionScheme = 0;
pdsch->refPoint = 0;
- pdsch->dmrs.dlDmrsSymbPos = 2;
+ pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
pdsch->dmrs.dlDmrsScramblingId = pci;
pdsch->dmrs.scid = 0;
pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
- pdsch->dmrs.dmrsPorts = 0;
+ pdsch->dmrs.dmrsPorts = 0x0001;
pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
- pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0,
+ pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0,
and PDSCH is always above SSB */
pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
pdsch->pdschTimeAlloc.rowIndex = 1;
- pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
+ /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */
+ pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
pdsch->beamPdschInfo.numPrgs = 1;
pdsch->beamPdschInfo.prgSize = 1;
}
-/**
- * @brief Fill SSB start symbol
- *
- * @details
- *
- * Function : fillSsbStartSymb
- *
- * This API stores SSB start index per beam
- *
- * @param[in] SchCellCb *cellCb
- * @return int
- * -# ROK
- * -# RFAILED
- **/
-void fillSsbStartSymb(SchCellCb *cellCb)
-{
- uint8_t cnt, scs;
-
- scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
- uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM];
-
- memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
- /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
- switch(scs)
- {
- case SCH_SCS_15KHZ:
- {
- uint8_t symbIdx=0;
- cnt = 2;/* n = 0, 1 for SCS = 15KHz */
- for(uint8_t idx=0; idx<cnt; idx++)
- {
- /* start symbol determined using {2, 8} + 14n */
- ssbStartSymbArr[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
- ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
- }
- }
- break;
- default:
- DU_LOG("\nERROR --> SCH : SCS %d is currently not supported", scs);
- }
- memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
- memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
-
-}
-
/**
* @brief cell config from MAC to SCH.
*
cellCb->macInst = pst->srcInst;
/* derive the SIB1 config parameters */
- fillSchSib1Cfg(schCellCfg->bandwidth, cellCb->numSlots,
+ fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots,
&(schCellCfg->sib1SchCfg), schCellCfg->phyCellId,
schCellCfg->ssbSchCfg.ssbOffsetPointA);
memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
uint8_t lcId = 0;
uint16_t ueIdx = 0;
uint16_t slot;
+#ifdef NR_TDD
+ uint16_t slotIdx = 0;
+#endif
SchUeCb *ueCb = NULLP;
SchCellCb *cell = NULLP;
SchDlSlotInfo *schDlSlotInfo = NULLP;
DU_LOG("\nDEBUG --> SCH : Received RLC BO Status indication");
cell = schCb[inst].cells[inst];
+ if(cell == NULLP)
+ {
+ DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): Cell does not exists");
+ return RFAILED;
+ }
+
GET_UE_IDX(dlBoInfo->crnti, ueIdx);
ueCb = &cell->ueCb[ueIdx-1];
lcId = dlBoInfo->lcId;
if(lcId == SRB1_LCID || lcId == SRB2_LCID || lcId == SRB3_LCID || \
- (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID))
+ (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID))
{
SET_ONE_BIT(ueIdx, cell->boIndBitMap);
ueCb->dlInfo.dlLcCtxt[lcId].bo = dlBoInfo->dataVolume;
return RFAILED;
}
- slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % cell->numSlots;
+ slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots;
+#ifdef NR_TDD
+ while(schGetSlotSymbFrmt(cell->slotFrmtBitMap, slot) != DL_SLOT)
+ {
+ slot = (slot + 1)%cell->numSlots;
+ slotIdx++;
+ if(slotIdx==cell->numSlots)
+ {
+ DU_LOG("\nERROR --> SCH : No DL Slot available");
+ return RFAILED;
+ }
+ }
+#endif
+
schDlSlotInfo = cell->schDlSlotInfo[slot];
+ if(schDlSlotInfo == NULLP)
+ {
+ DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): schDlSlotInfo does not exists");
+ return RFAILED;
+ }
SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo));
- if(!schDlSlotInfo->dlMsgInfo)
+ if(schDlSlotInfo->dlMsgInfo == NULLP)
{
DU_LOG("\nERROR --> SCH : Memory allocation failed for dlMsgInfo");
schDlSlotInfo = NULL;
return RFAILED;
}
+
schDlSlotInfo->dlMsgInfo->crnti = dlBoInfo->crnti;
schDlSlotInfo->dlMsgInfo->ndi = 1;
schDlSlotInfo->dlMsgInfo->harqProcNum = 0;
schDlSlotInfo->dlMsgInfo->harqFeedbackInd = 0;
schDlSlotInfo->dlMsgInfo->dciFormatId = 1;
if(lcId == SRB0_LCID)
+ {
schDlSlotInfo->dlMsgInfo->isMsg4Pdu = true;
-
+ schDlSlotInfo->dlMsgInfo->dlMsgPduLen = dlBoInfo->dataVolume;
+ }
return ROK;
}
Code Review / o-du / l2.git / blobdiff