RARandSib1Transmission

[o-du/l2.git] / src / 5gnrmac / rg_tom.c

diff --git a/src/5gnrmac/rg_tom.c b/src/5gnrmac/rg_tom.c
index a181fd5..f18947b 100755 (executable)
--- a/src/5gnrmac/rg_tom.c
+++ b/src/5gnrmac/rg_tom.c
@@ -613,10 +613,14 @@ SlotIndInfo slotInd
    }
 #endif
 
-/* Trigger for DL TTI REQ */
-   CmLteTimingInfo   dlTtiReqtimingInfo;
-   RGADDTOCRNTTIME(cellCb->crntTime, dlTtiReqtimingInfo, TFU_DELTA);
-   handleDlTtiReq(&dlTtiReqtimingInfo);
+   CmLteTimingInfo   timingInfo;
+   RGADDTOCRNTTIME(cellCb->crntTime, timingInfo, TFU_DELTA);
+
+   /* Trigger for DL TTI REQ */
+   handleDlTtiReq(&timingInfo);
+
+   /* Trigger for UL TTI REQ */
+   handleUlTtiReq(&timingInfo);
 
    dlSf = &cellCb->subFrms[(slotInd.slot % RG_NUM_SUB_FRAMES)];
 
@@ -1511,8 +1515,8 @@ Inst             inst;
 #ifdef LTEMAC_SPS
    Bool              isSpsRnti=FALSE;
    Pst               schPst1;  
-   RgInfSpsRelInfo   relInfo;
-   Bool              spsToBeActvtd = FALSE;
+  // RgInfSpsRelInfo   relInfo;
+       Bool              spsToBeActvtd = FALSE;
    U16               sduSize = 0;
 #endif
    U32               lcgBytes[RGINF_MAX_LCG_PER_UE];
@@ -1664,10 +1668,12 @@ Inst             inst;
 
                      ueCb->ul.implRelCntr = 0;
                      ueCb->ul.explRelCntr = 0;
-                     relInfo.cellSapId = cellCb->schInstMap.cellSapId;
+#if 0                     
+                                                       relInfo.cellSapId = cellCb->schInstMap.cellSapId;
                      relInfo.cRnti = ueCb->ueId;
-                     relInfo.isExplRel = FALSE;
+                                                       relInfo.isExplRel= FALSE;
                      //TODO: commented for compilation without SCH RgMacSchSpsRel(&schPst1, &relInfo);
+#endif  
                   }
                }
                else