/* MAX values */
#define MAX_MAC_CE 6
#define MAX_CRI_SIZE 6
-#define MAX_MAC_DL_PDU 10
+#define MAX_MAC_DL_PDU 16
#define MAX_NUM_HARQ_PROC 16
-#define MAX_SLOT_SUPPORTED 10 /* numerology 0 15Khz */
#define MAX_ZERO_CORR_CFG_IDX 16 /* max zero correlation config index */
+#define MAC_TQ_SIZE 10 /* Timing Queue Size */
+#define MAX_NUM_TIMER 1 /* MAX number of MAC timers */
#define DEFAULT_CELLS 1
#define SI_RNTI 0xFFFF
#define P_RNTI 0xFFFE
-#define PERIODIC_BSR_TMR_1MS 1
-#define PERIODIC_BSR_TMR_5MS 5
-#define PERIODIC_BSR_TMR_10MS 10
-#define PERIODIC_BSR_TMR_16MS 16
-#define PERIODIC_BSR_TMR_20MS 20
-#define PERIODIC_BSR_TMR_32MS 32
-#define PERIODIC_BSR_TMR_40MS 40
-#define PERIODIC_BSR_TMR_60MS 60
-#define PERIODIC_BSR_TMR_80MS 80
-#define PERIODIC_BSR_TMR_128MS 128
-#define PERIODIC_BSR_TMR_160MS 160
-#define PERIODIC_BSR_TMR_320MS 320
-#define PERIODIC_BSR_TMR_640MS 640
-#define PERIODIC_BSR_TMR_1280MS 1280
-#define PERIODIC_BSR_TMR_2560MS 2560
-
-#define RETX_BSR_TMR_10MS 10
-#define RETX_BSR_TMR_20MS 20
-#define RETX_BSR_TMR_40MS 40
-#define RETX_BSR_TMR_80MS 80
-#define RETX_BSR_TMR_160MS 160
-#define RETX_BSR_TMR_320MS 320
-#define RETX_BSR_TMR_640MS 640
-#define RETX_BSR_TMR_1280MS 1280
-#define RETX_BSR_TMR_2560MS 2560
-#define RETX_BSR_TMR_5120MS 5120
-#define RETX_BSR_TMR_10240MS 10240
-
-#define SR_DELAY_TMR_20MS 20
-#define SR_DELAY_TMR_40MS 40
-#define SR_DELAY_TMR_64MS 64
-#define SR_DELAY_TMR_128MS 128
-#define SR_DELAY_TMR_512MS 512
-#define SR_DELAY_TMR_1024MS 1024
-#define SR_DELAY_TMR_2560MS 2560
-
#define MAC_LCID_CCCH 0
-#define MAC_DEDLC_MIN_LCID 1
-#define MAC_DEDLC_MAX_LCID 32
+#define MAC_LCID_MIN 1
+#define MAC_LCID_MAX 32
#define MAC_LCID_RESERVED_MIN 33
#define MAC_LCID_RESERVED_MAX 51
#define MAC_LCID_CCCH_48BIT 52
#define MAC_LCID_CRI 62
#define MAC_LCID_PADDING 63
+/* Definitions for size of RAR PDU contents (in bits).
+ * Refer spec 38.321, sections 6.1.4, 6.2.2 and 6.2.3*/
+#define E_BIT_SIZE 1
+#define T_BIT_SIZE 1
+#define R_BIT_SIZE 1
+#define RAPID_SIZE 6
+#define LC_ID_SIZE 6
+#define TIMING_ADVANCE_SIZE 12
+#define T_CRNTI_SIZE 16
+/* UL Grant is of size = 27 bits. Refer to Spec 38.213, Table 8.2-1 for
+ * contents of UL grant in RAR */
+#define FREQ_HOP_FLAG_SIZE 1
+#define FREQ_RSRC_ALLOC_SIZE 14
+#define TIME_RSRC_ALLOC_SIZE 4
+#define MCS_SIZE 4
+#define TPC_COMMAND_SIZE 3
+#define CSI_REQUEST_SIZE 1
+
typedef struct macCellCb MacCellCb;
+typedef enum
+{
+ CELL_STATE_UP,
+ CELL_TO_BE_STOPPED,
+ CELL_STOP_IN_PROGRESS,
+}CellState;
+
typedef enum
{
UE_STATE_INACTIVE,
- UE_STATE_ACTIVE
+ UE_STATE_ACTIVE,
+ UE_HANDIN_IN_PROGRESS
}UeState;
typedef enum
{
- LC_STATE_INACTIVE,
- LC_STATE_ACTIVE
-}LcState;
+ MAC_LC_STATE_INACTIVE,
+ MAC_LC_STATE_ACTIVE
+}MacLcState;
typedef struct macDlSlot
{
typedef struct macDlData
{
+ uint8_t ueId;
uint16_t numPdu;
MacDlInfo pduInfo[MAX_MAC_DL_PDU];
}MacDlData;
/* Uplink deidcated logical channel info */
typedef struct ulLcCb
{
- uint8_t lcId; /* Logical Channel Id */
- uint8_t lcGrpId; /* Logical Channel group */
- LcState lcActive; /* Is LC active ? */
+ uint8_t lcId; /* Logical Channel Id */
+ uint8_t lcGrpId; /* Logical Channel group */
+ MacLcState lcActive; /* Is LC active ? */
+ /*Commenting as S-NSSAI and PDU session will be used in future scope*/
+ /*For eg: When we have to send these for AMBR cases*/
+ #if 0
+ uint16_t pduSessionId; /*Pdu Session Id*/
+ Snssai *snssai; /*S-NSSAI assoc with LCID*/
+ #endif
}UlLcCb;
/* Downlink dedicated logical channel info */
typedef struct dlLcCb
{
- uint8_t lcId; /* Logical channel Id */
- LcState lcState; /* Is LC active ? */
+ uint8_t lcId; /* Logical channel Id */
+ MacLcState lcState; /* Is LC active ? */
+ /*Commenting as S-NSSAI and PDU session will be used in future scope*/
+ /*For eg: When we have to send these info via FAPI to phy layer*/
+ #if 0
+ uint16_t pduSessionId;/*Pdu Session Id*/
+ Snssai *snssai; /*S-NSSAI assoc with LCID*/
+ #endif
}DlLcCb;
/* BSR Information */
{
uint8_t maxReTx; /* MAX HARQ retransmission */
uint8_t numUlLc; /* Number of uplink logical channels */
- UlLcCb lcCb[MAX_NUM_LOGICAL_CHANNELS]; /* Uplink dedicated logocal channels */
+ UlLcCb lcCb[MAX_NUM_LC]; /* Uplink dedicated logocal channels */
}UeUlCb;
/* UE specific DL Info */
{
DlHarqEnt dlHarqEnt; /* DL HARQ entity */
uint8_t numDlLc; /* Number of downlink logical channels */
- DlLcCb lcCb[MAX_NUM_LOGICAL_CHANNELS]; /* Downlink dedicated logical channels */
+ DlLcCb lcCb[MAX_NUM_LC]; /* Downlink dedicated logical channels */
}UeDlCb;
/* UE Cb */
typedef struct macUeCb
{
- uint16_t ueIdx; /* UE Idx assigned by DU APP */
+ uint16_t ueId; /* UE Id from DU APP */
uint16_t crnti; /* UE CRNTI */
MacCellCb *cellCb; /* Pointer to cellCb to whihc this UE belongs */
UeState state; /* Is UE active ? */
MacBsrTmrCfg bsrTmrCfg; /* BSR Timer Info */
UeUlCb ulInfo; /* UE specific UL info */
UeDlCb dlInfo; /* UE specific DL info */
+ DataTransmissionAction transmissionAction;
}MacUeCb;
struct macCellCb
{
uint16_t cellId;
+ CellState state;
+ uint8_t crntiMap;
MacRaCbInfo macRaCb[MAX_NUM_UE];
- MacDlSlot dlSlot[MAX_SLOT_SUPPORTED];
- MacUlSlot ulSlot[MAX_SLOT_SUPPORTED];
+ MacDlSlot dlSlot[MAX_SLOTS];
+ MacUlSlot ulSlot[MAX_SLOTS];
uint16_t numActvUe;
+ MacUeCfg *ueCfgTmpData[MAX_NUM_UE];
MacUeCb ueCb[MAX_NUM_UE];
MacCellCfg macCellCfg;
- SlotIndInfo currTime;
+ SlotTimingInfo currTime;
};
typedef struct macCb
{
- Inst macInst;
- ProcId procId;
- MacCellCb *macCell[MAX_NUM_CELL];
+ Inst macInst;
+ ProcId procId;
+ uint8_t tmrRes; /*!< Timer resolution */
+ CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
+ CmTqType tmrTq[MAC_TQ_SIZE]; /*!< Timer Task Queue */
+ CmTimer tmrBlk[MAX_NUM_TIMER]; /*!< Timer Block */
+ MacCellCb *macCell[MAX_NUM_CELL];
}MacCb;
/* global variable */
MacCb macCb;
+
+/* Function declarations */
+short int macActvTmr(Ent ent,Inst inst);
void fillRarPdu(RarInfo *rarInfo);
-void createMacRaCb(uint16_t cellId, uint16_t crnti);
-void fillMsg4DlData(uint16_t cellId, MacDlData *dlData, uint8_t *msg4Pdu);
+void createMacRaCb(RachIndInfo *rachIndInfo);
+void fillMsg4DlData(MacDlData *dlData, uint16_t msg4PduLen, uint8_t *msg4Pdu);
void fillMacCe(MacCeInfo *macCeData, uint8_t *msg3Pdu);
void macMuxPdu(MacDlData *dlData, MacCeInfo *macCeData, uint8_t *msg4TxPdu, uint16_t tbSize);
-uint8_t unpackRxData(uint16_t cellId, RxDataIndPdu *rxDataIndPdu);
-uint8_t macSendUlCcchInd(uint8_t *rrcContainer, uint16_t cellId, uint16_t crnti);
-void fillMg4Pdu(Msg4Alloc *msg4Alloc);
-void buildAndSendMuxPdu(SlotIndInfo currTimingInfo);
-
+uint8_t unpackRxData(uint16_t cellId, SlotTimingInfo slotInfo, RxDataIndPdu *rxDataIndPdu);
+void fillMg4Pdu(DlMsgAlloc *msg4Alloc);
+void buildAndSendMuxPdu(SlotTimingInfo currTimingInfo);
+uint8_t macProcUlCcchInd(uint16_t cellId, uint16_t crnti, uint16_t rrcContSize, uint8_t *rrcContainer);
+uint8_t macProcShortBsr(uint16_t cellId, uint16_t crnti, uint8_t lcgId, uint32_t bufferSize);
+uint8_t macProcUlData(uint16_t cellId, uint16_t rnti, SlotTimingInfo slotInfo, \
+ uint8_t lcId, uint16_t pduLen, uint8_t *pdu);
+uint8_t sendSchedRptToRlc(DlSchedInfo dlInfo, SlotTimingInfo slotInfo, uint8_t ueIdx, uint8_t schInfoIdx);
+uint8_t macProcLongBsr(uint16_t cellId, uint16_t crnti,uint8_t numLcg,\
+ DataVolInfo dataVolInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS]);
+void freeMacSliceCfgReq(MacSliceCfgReq *cfgReq,Pst *pst);
#endif
/**********************************************************************
End of file
Code Review / o-du / l2.git / blobdiff