#endif
#include "lwr_mac_fsm.h"
#include "lwr_mac_phy.h"
+#include "lwr_mac_utils.h"
#include "mac_utils.h"
+#include "nfapi_interface.h"
#define MIB_SFN_BITMASK 0xFC
#define PDCCH_PDU_TYPE 0
/* Global variables */
LwrMacCb lwrMacCb;
-uint8_t UnrestrictedSetNcsTable[MAX_ZERO_CORR_CFG_IDX];
+extern uint8_t UnrestrictedSetNcsTable[MAX_ZERO_CORR_CFG_IDX];
void fapiMacConfigRsp(uint16_t cellId);
uint16_t sendTxDataReq(SlotTimingInfo currTimingInfo, MacDlSlot *dlSlot, p_fapi_api_queue_elem_t prevElem, fapi_vendor_tx_data_req_t *vendorTxDataReq);
uint16_t fillUlTtiReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t prevElem, fapi_vendor_ul_tti_req_t* vendorUlTti);
* @return void
*
* ****************************************************************/
-void fillMsgHeader(fapi_msg_t *hdr, uint16_t msgType, uint16_t msgLen)
+void fillMsgHeader(fapi_msg_t *hdr, uint16_t msgType, uint32_t msgLen)
{
memset(hdr, 0, sizeof(fapi_msg_t));
hdr->msg_id = msgType;
uint8_t sysInfoIndSize = 1;
uint8_t reservedSize = 15;
- dlDciPtr->rnti = sib1PdcchInfo->dci.rnti;
- dlDciPtr->scramblingId = sib1PdcchInfo->dci.scramblingId;
- dlDciPtr->scramblingRnti = sib1PdcchInfo->dci.scramblingRnti;
- dlDciPtr->cceIndex = sib1PdcchInfo->dci.cceIndex;
- dlDciPtr->aggregationLevel = sib1PdcchInfo->dci.aggregLevel;
- dlDciPtr->pc_and_bform.numPrgs = sib1PdcchInfo->dci.beamPdcchInfo.numPrgs;
- dlDciPtr->pc_and_bform.prgSize = sib1PdcchInfo->dci.beamPdcchInfo.prgSize;
- dlDciPtr->pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
- dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
- dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
- dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
- dlDciPtr->powerControlOffsetSS = sib1PdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+ dlDciPtr[0].rnti = sib1PdcchInfo->dci[0].rnti;
+ dlDciPtr[0].scramblingId = sib1PdcchInfo->dci[0].scramblingId;
+ dlDciPtr[0].scramblingRnti = sib1PdcchInfo->dci[0].scramblingRnti;
+ dlDciPtr[0].cceIndex = sib1PdcchInfo->dci[0].cceIndex;
+ dlDciPtr[0].aggregationLevel = sib1PdcchInfo->dci[0].aggregLevel;
+ dlDciPtr[0].pc_and_bform.numPrgs = sib1PdcchInfo->dci[0].beamPdcchInfo.numPrgs;
+ dlDciPtr[0].pc_and_bform.prgSize = sib1PdcchInfo->dci[0].beamPdcchInfo.prgSize;
+ dlDciPtr[0].pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci[0].beamPdcchInfo.digBfInterfaces;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci[0].beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci[0].beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr[0].beta_pdcch_1_0 = sib1PdcchInfo->dci[0].txPdcchPower.beta_pdcch_1_0;
+ dlDciPtr[0].powerControlOffsetSS = sib1PdcchInfo->dci[0].txPdcchPower.powerControlOffsetSS;
/* Calculating freq domain resource allocation field value and size
* coreset0Size = Size of coreset 0
* Spec 38.214 Sec 5.1.2.2.2
*/
coreset0Size= sib1PdcchInfo->coresetCfg.coreSetSize;
- rbStart = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb;
- rbLen = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb;
+ rbStart = sib1PdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.startPrb;
+ rbLen = sib1PdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.numPrb;
if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
{
}
/* Fetching DCI field values */
- timeDomResAssign = sib1PdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex -1;
- VRB2PRBMap = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping;
- modNCodScheme = sib1PdcchInfo->dci.pdschCfg.codeword[0].mcsIndex;
- redundancyVer = sib1PdcchInfo->dci.pdschCfg.codeword[0].rvIndex;
+ timeDomResAssign = sib1PdcchInfo->dci[0].pdschCfg.pdschTimeAlloc.rowIndex -1;
+ VRB2PRBMap = sib1PdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = sib1PdcchInfo->dci[0].pdschCfg.codeword[0].mcsIndex;
+ redundancyVer = sib1PdcchInfo->dci[0].pdschCfg.codeword[0].rvIndex;
sysInfoInd = 0; /* 0 for SIB1; 1 for SI messages */
reserved = 0;
sysInfoInd = reverseBits(sysInfoInd, sysInfoIndSize);
/* Calulating total number of bytes in buffer */
- dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ dlDciPtr[0].payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ VRB2PRBMapSize + modNCodSchemeSize + redundancyVerSize\
+ sysInfoIndSize + reservedSize;
- numBytes = dlDciPtr->payloadSizeBits / 8;
- if(dlDciPtr->payloadSizeBits % 8)
+ numBytes = dlDciPtr[0].payloadSizeBits / 8;
+ if(dlDciPtr[0].payloadSizeBits % 8)
numBytes += 1;
if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
/* Initialize buffer */
for(bytePos = 0; bytePos < numBytes; bytePos++)
- dlDciPtr->payload[bytePos] = 0;
+ dlDciPtr[0].payload[bytePos] = 0;
bytePos = numBytes - 1;
bitPos = 0;
/* Packing DCI format fields */
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
freqDomResAssign, freqDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
timeDomResAssign, timeDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
VRB2PRBMap, VRB2PRBMapSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
modNCodScheme, modNCodSchemeSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
redundancyVer, redundancyVerSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
sysInfoInd, sysInfoIndSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
reserved, reservedSize);
}
uint8_t tbScalingSize = 2;
uint8_t reservedSize = 6;
- dlDciPtr->rnti = P_RNTI;
- dlDciPtr->scramblingId = macCellCfg->cellCfg.phyCellId;
- dlDciPtr->scramblingRnti = 0;
- dlDciPtr->cceIndex = dlPageAlloc->pageDlDci.cceIndex;
- dlDciPtr->aggregationLevel = dlPageAlloc->pageDlDci.aggregLevel;
- dlDciPtr->pc_and_bform.numPrgs = 1;
- dlDciPtr->pc_and_bform.prgSize = 1;
- dlDciPtr->pc_and_bform.digBfInterfaces = 0;
- dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = 0;
- dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = 0;
- dlDciPtr->beta_pdcch_1_0 = 0;
- dlDciPtr->powerControlOffsetSS = 0;
+ dlDciPtr[0].rnti = P_RNTI;
+ dlDciPtr[0].scramblingId = macCellCfg->cellCfg.phyCellId;
+ dlDciPtr[0].scramblingRnti = 0;
+ dlDciPtr[0].cceIndex = dlPageAlloc->pageDlDci.cceIndex;
+ dlDciPtr[0].aggregationLevel = dlPageAlloc->pageDlDci.aggregLevel;
+ dlDciPtr[0].pc_and_bform.numPrgs = 1;
+ dlDciPtr[0].pc_and_bform.prgSize = 1;
+ dlDciPtr[0].pc_and_bform.digBfInterfaces = 0;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].pmIdx = 0;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = 0;
+ dlDciPtr[0].beta_pdcch_1_0 = 0;
+ dlDciPtr[0].powerControlOffsetSS = 0;
/* Calculating freq domain resource allocation field value and size
* coreset0Size = Size of coreset 0
tbScaling = reverseBits(tbScaling, tbScalingSize);
/* Calulating total number of bytes in buffer */
- dlDciPtr->payloadSizeBits = shortMsgIndSize + shortMsgSize + freqDomResAssignSize\
+ dlDciPtr[0].payloadSizeBits = shortMsgIndSize + shortMsgSize + freqDomResAssignSize\
+ timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
+ tbScaling + reservedSize;
- numBytes = dlDciPtr->payloadSizeBits / 8;
- if(dlDciPtr->payloadSizeBits % 8)
+ numBytes = dlDciPtr[0].payloadSizeBits / 8;
+ if(dlDciPtr[0].payloadSizeBits % 8)
{
numBytes += 1;
}
/* Initialize buffer */
for(bytePos = 0; bytePos < numBytes; bytePos++)
{
- dlDciPtr->payload[bytePos] = 0;
+ dlDciPtr[0].payload[bytePos] = 0;
}
bytePos = numBytes - 1;
bitPos = 0;
/* Packing DCI format fields */
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
shortMsgInd, shortMsgIndSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
shortMsg, shortMsgSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
freqDomResAssign, freqDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
timeDomResAssign, timeDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
VRB2PRBMap, VRB2PRBMapSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
modNCodScheme, modNCodSchemeSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
tbScaling, tbScalingSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
reserved, reservedSize);
}
} /* fillPageDlDciPdu */
uint8_t tbScalingSize = 2;
uint8_t reservedSize = 16;
- dlDciPtr->rnti = rarPdcchInfo->dci.rnti;
- dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId;
- dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti;
- dlDciPtr->cceIndex = rarPdcchInfo->dci.cceIndex;
- dlDciPtr->aggregationLevel = rarPdcchInfo->dci.aggregLevel;
- dlDciPtr->pc_and_bform.numPrgs = rarPdcchInfo->dci.beamPdcchInfo.numPrgs;
- dlDciPtr->pc_and_bform.prgSize = rarPdcchInfo->dci.beamPdcchInfo.prgSize;
- dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
- dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
- dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
- dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
- dlDciPtr->powerControlOffsetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+ dlDciPtr[0].rnti = rarPdcchInfo->dci[0].rnti;
+ dlDciPtr[0].scramblingId = rarPdcchInfo->dci[0].scramblingId;
+ dlDciPtr[0].scramblingRnti = rarPdcchInfo->dci[0].scramblingRnti;
+ dlDciPtr[0].cceIndex = rarPdcchInfo->dci[0].cceIndex;
+ dlDciPtr[0].aggregationLevel = rarPdcchInfo->dci[0].aggregLevel;
+ dlDciPtr[0].pc_and_bform.numPrgs = rarPdcchInfo->dci[0].beamPdcchInfo.numPrgs;
+ dlDciPtr[0].pc_and_bform.prgSize = rarPdcchInfo->dci[0].beamPdcchInfo.prgSize;
+ dlDciPtr[0].pc_and_bform.digBfInterfaces = rarPdcchInfo->dci[0].beamPdcchInfo.digBfInterfaces;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci[0].beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci[0].beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr[0].beta_pdcch_1_0 = rarPdcchInfo->dci[0].txPdcchPower.beta_pdcch_1_0;
+ dlDciPtr[0].powerControlOffsetSS = rarPdcchInfo->dci[0].txPdcchPower.powerControlOffsetSS;
/* Calculating freq domain resource allocation field value and size
* coreset0Size = Size of coreset 0
/* TODO: Fill values of coreset0Size, rbStart and rbLen */
coreset0Size= rarPdcchInfo->coresetCfg.coreSetSize;
- rbStart = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb;
- rbLen = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb;
+ rbStart = rarPdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.startPrb;
+ rbLen = rarPdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.numPrb;
if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
{
}
/* Fetching DCI field values */
- timeDomResAssign = rarPdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex;
- VRB2PRBMap = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping;
- modNCodScheme = rarPdcchInfo->dci.pdschCfg.codeword[0].mcsIndex;
+ timeDomResAssign = rarPdcchInfo->dci[0].pdschCfg.pdschTimeAlloc.rowIndex;
+ VRB2PRBMap = rarPdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = rarPdcchInfo->dci[0].pdschCfg.codeword[0].mcsIndex;
tbScaling = 0; /* configured to 0 scaling */
reserved = 0;
tbScaling = reverseBits(tbScaling, tbScalingSize);
/* Calulating total number of bytes in buffer */
- dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ dlDciPtr[0].payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ VRB2PRBMapSize + modNCodSchemeSize + tbScalingSize + reservedSize;
- numBytes = dlDciPtr->payloadSizeBits / 8;
- if(dlDciPtr->payloadSizeBits % 8)
+ numBytes = dlDciPtr[0].payloadSizeBits / 8;
+ if(dlDciPtr[0].payloadSizeBits % 8)
numBytes += 1;
if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
/* Initialize buffer */
for(bytePos = 0; bytePos < numBytes; bytePos++)
- dlDciPtr->payload[bytePos] = 0;
+ dlDciPtr[0].payload[bytePos] = 0;
bytePos = numBytes - 1;
bitPos = 0;
/* Packing DCI format fields */
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
freqDomResAssign, freqDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
timeDomResAssign, timeDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
VRB2PRBMap, VRB2PRBMapSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
modNCodScheme, modNCodSchemeSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
tbScaling, tbScalingSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
reserved, reservedSize);
}
} /* fillRarDlDciPdu */
void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\
DlMsgSchInfo *dlMsgSchInfo)
{
+ uint8_t dciIndex = 0;
if(dlDciPtr != NULLP)
{
uint8_t numBytes;
uint8_t pucchResoIndSize = 3;
uint8_t harqFeedbackIndSize = 3;
- dlDciPtr->rnti = pdcchInfo->dci.rnti;
- dlDciPtr->scramblingId = pdcchInfo->dci.scramblingId;
- dlDciPtr->scramblingRnti = pdcchInfo->dci.scramblingRnti;
- dlDciPtr->cceIndex = pdcchInfo->dci.cceIndex;
- dlDciPtr->aggregationLevel = pdcchInfo->dci.aggregLevel;
- dlDciPtr->pc_and_bform.numPrgs = pdcchInfo->dci.beamPdcchInfo.numPrgs;
- dlDciPtr->pc_and_bform.prgSize = pdcchInfo->dci.beamPdcchInfo.prgSize;
- dlDciPtr->pc_and_bform.digBfInterfaces = pdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
- dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
- dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
- dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
- dlDciPtr->powerControlOffsetSS = pdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
-
- /* Calculating freq domain resource allocation field value and size
- * coreset0Size = Size of coreset 0
- * RBStart = Starting Virtual Rsource block
- * RBLen = length of contiguously allocted RBs
- * Spec 38.214 Sec 5.1.2.2.2
- */
- coresetSize = pdcchInfo->coresetCfg.coreSetSize;
- rbStart = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb;
- rbLen = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb;
-
- if((rbLen >=1) && (rbLen <= coresetSize - rbStart))
+ for(dciIndex = 0; dciIndex < pdcchInfo->numDlDci; dciIndex++)
{
- if((rbLen - 1) <= floor(coresetSize / 2))
- freqDomResAssign = (coresetSize * (rbLen-1)) + rbStart;
- else
- freqDomResAssign = (coresetSize * (coresetSize - rbLen + 1)) \
- + (coresetSize - 1 - rbStart);
-
- freqDomResAssignSize = ceil(log2(coresetSize * (coresetSize + 1) / 2));
- }
-
- /* Fetching DCI field values */
- dciFormatId = dlMsgSchInfo->dciFormatId; /* Always set to 1 for DL */
- timeDomResAssign = pdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex -1;
- VRB2PRBMap = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping;
- modNCodScheme = pdcchInfo->dci.pdschCfg.codeword[0].mcsIndex;
- ndi = dlMsgSchInfo->transportBlock[0].ndi;
- redundancyVer = pdcchInfo->dci.pdschCfg.codeword[0].rvIndex;
- harqProcessNum = dlMsgSchInfo->harqProcNum;
- dlAssignmentIdx = dlMsgSchInfo->dlAssignIdx;
- pucchTpc = dlMsgSchInfo->pucchTpc;
- pucchResoInd = dlMsgSchInfo->pucchResInd;
- harqFeedbackInd = dlMsgSchInfo->harqFeedbackInd;
+ dlDciPtr[dciIndex].rnti = pdcchInfo->dci[dciIndex].rnti;
+ dlDciPtr[dciIndex].scramblingId = pdcchInfo->dci[dciIndex].scramblingId;
+ dlDciPtr[dciIndex].scramblingRnti = pdcchInfo->dci[dciIndex].scramblingRnti;
+ dlDciPtr[dciIndex].cceIndex = pdcchInfo->dci[dciIndex].cceIndex;
+ dlDciPtr[dciIndex].aggregationLevel = pdcchInfo->dci[dciIndex].aggregLevel;
+ dlDciPtr[dciIndex].pc_and_bform.numPrgs = pdcchInfo->dci[dciIndex].beamPdcchInfo.numPrgs;
+ dlDciPtr[dciIndex].pc_and_bform.prgSize = pdcchInfo->dci[dciIndex].beamPdcchInfo.prgSize;
+ dlDciPtr[dciIndex].pc_and_bform.digBfInterfaces = pdcchInfo->dci[dciIndex].beamPdcchInfo.digBfInterfaces;
+ dlDciPtr[dciIndex].pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci[dciIndex].beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr[dciIndex].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci[dciIndex].beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr[dciIndex].beta_pdcch_1_0 = pdcchInfo->dci[dciIndex].txPdcchPower.beta_pdcch_1_0;
+ dlDciPtr[dciIndex].powerControlOffsetSS = pdcchInfo->dci[dciIndex].txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ coresetSize = pdcchInfo->coresetCfg.coreSetSize;
+ rbStart = pdcchInfo->dci[dciIndex].pdschCfg.pdschFreqAlloc.startPrb;
+ rbLen = pdcchInfo->dci[dciIndex].pdschCfg.pdschFreqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coresetSize - rbStart))
+ {
+ if((rbLen - 1) <= floor(coresetSize / 2))
+ freqDomResAssign = (coresetSize * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coresetSize * (coresetSize - rbLen + 1)) \
+ + (coresetSize - 1 - rbStart);
- /* Reversing bits in each DCI field */
- dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
- freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
- timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
- VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
- modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
- ndi = reverseBits(ndi, ndiSize);
- redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
- harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
- dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize);
- pucchTpc = reverseBits(pucchTpc, pucchTpcSize);
- pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize);
- harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize);
+ freqDomResAssignSize = ceil(log2(coresetSize * (coresetSize + 1) / 2));
+ }
+ /* Fetching DCI field values */
+ dciFormatId = dlMsgSchInfo->dciFormatId; /* Always set to 1 for DL */
+ timeDomResAssign = pdcchInfo->dci[dciIndex].pdschCfg.pdschTimeAlloc.rowIndex -1;
+ VRB2PRBMap = pdcchInfo->dci[dciIndex].pdschCfg.pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = pdcchInfo->dci[dciIndex].pdschCfg.codeword[0].mcsIndex;
+ ndi = dlMsgSchInfo->transportBlock[0].ndi;
+ redundancyVer = pdcchInfo->dci[dciIndex].pdschCfg.codeword[0].rvIndex;
+ harqProcessNum = dlMsgSchInfo->harqProcNum;
+ dlAssignmentIdx = dlMsgSchInfo->dlAssignIdx;
+ pucchTpc = dlMsgSchInfo->pucchTpc;
+ pucchResoInd = dlMsgSchInfo->pucchResInd;
+ harqFeedbackInd = dlMsgSchInfo->harqFeedbackInd;
- /* Calulating total number of bytes in buffer */
- dlDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
- + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
- + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\
- + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize);
+ /* Reversing bits in each DCI field */
+ dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ ndi = reverseBits(ndi, ndiSize);
+ redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
+ harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
+ dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize);
+ pucchTpc = reverseBits(pucchTpc, pucchTpcSize);
+ pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize);
+ harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize);
- numBytes = dlDciPtr->payloadSizeBits / 8;
- if(dlDciPtr->payloadSizeBits % 8)
- numBytes += 1;
- if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
- {
- DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
- return;
- }
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr[dciIndex].payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
+ + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
+ + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\
+ + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize);
- /* Initialize buffer */
- for(bytePos = 0; bytePos < numBytes; bytePos++)
- dlDciPtr->payload[bytePos] = 0;
+ numBytes = dlDciPtr[dciIndex].payloadSizeBits / 8;
+ if(dlDciPtr[dciIndex].payloadSizeBits % 8)
+ numBytes += 1;
- bytePos = numBytes - 1;
- bitPos = 0;
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
- /* Packing DCI format fields */
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- dciFormatId, dciFormatIdSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- freqDomResAssign, freqDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- timeDomResAssign, timeDomResAssignSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- VRB2PRBMap, VRB2PRBMapSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- modNCodScheme, modNCodSchemeSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- ndi, ndiSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- redundancyVer, redundancyVerSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- redundancyVer, redundancyVerSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- harqProcessNum, harqProcessNumSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- dlAssignmentIdx, dlAssignmentIdxSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- pucchTpc, pucchTpcSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- pucchResoInd, pucchResoIndSize);
- fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
- harqFeedbackInd, harqFeedbackIndSize);
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr[dciIndex].payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ dciFormatId, dciFormatIdSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ ndi, ndiSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ harqProcessNum, harqProcessNumSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ dlAssignmentIdx, dlAssignmentIdxSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ pucchTpc, pucchTpcSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ pucchResoInd, pucchResoIndSize);
+ fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\
+ harqFeedbackInd, harqFeedbackIndSize);
+ }
}
}
dlTtiReqPdu->pdu.pdcch_pdu.startSymbolIndex = pageAlloc->pageDlDci.ssStartSymbolIndex;
dlTtiReqPdu->pdu.pdcch_pdu.durationSymbols = pageAlloc->pageDlDci.durationSymbols;
- memcpy(dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource, pageAlloc->pageDlDci.freqDomainResource, 6*sizeof(uint8_t));
+ convertFreqDomRsrcMapToIAPIFormat(pageAlloc->pageDlDci.freqDomainResource, \
+ dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource);
dlTtiReqPdu->pdu.pdcch_pdu.cceRegMappingType = pageAlloc->pageDlDci.cceRegMappingType;
dlTtiReqPdu->pdu.pdcch_pdu.regBundleSize = pageAlloc->pageDlDci.cceReg.interleaved.regBundleSize;
dlTtiReqPdu->pdu.pdcch_pdu.interleaverSize = pageAlloc->pageDlDci.cceReg.interleaved.interleaverSize;
uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_pdu_t *dlTtiVendorPdu, MacDlSlot *dlSlot, int8_t dlMsgSchInfoIdx, \
RntiType rntiType, uint8_t coreSetType, uint8_t ueIdx)
{
+ uint8_t dciIndex = 0;
+
if(dlTtiReqPdu != NULLP)
{
PdcchCfg *pdcchInfo = NULLP;
DU_LOG("\nERROR --> LWR_MAC: Failed filling PDCCH Pdu");
return RFAILED;
}
-
+
dlTtiReqPdu->pduType = PDCCH_PDU_TYPE;
dlTtiReqPdu->pdu.pdcch_pdu.bwpSize = bwp->freqAlloc.numPrb;
dlTtiReqPdu->pdu.pdcch_pdu.bwpStart = bwp->freqAlloc.startPrb;
dlTtiReqPdu->pdu.pdcch_pdu.startSymbolIndex = pdcchInfo->coresetCfg.startSymbolIndex;
dlTtiReqPdu->pdu.pdcch_pdu.durationSymbols = pdcchInfo->coresetCfg.durationSymbols;
- memcpy(dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource, pdcchInfo->coresetCfg.freqDomainResource, 6);
+ convertFreqDomRsrcMapToIAPIFormat(pdcchInfo->coresetCfg.freqDomainResource,\
+ dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource);
dlTtiReqPdu->pdu.pdcch_pdu.cceRegMappingType = pdcchInfo->coresetCfg.cceRegMappingType;
dlTtiReqPdu->pdu.pdcch_pdu.regBundleSize = pdcchInfo->coresetCfg.regBundleSize;
dlTtiReqPdu->pdu.pdcch_pdu.interleaverSize = pdcchInfo->coresetCfg.interleaverSize;
dlTtiVendorPdu->pdu_type = FAPI_PDCCH_PDU_TYPE;
dlTtiVendorPdu->pdu_size = sizeof(fapi_vendor_dl_pdcch_pdu_t);
dlTtiVendorPdu->pdu.pdcch_pdu.num_dl_dci = dlTtiReqPdu->pdu.pdcch_pdu.numDlDci;
- dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_pdcch_to_ssb = 0;
- dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_dmrs_to_ssb = 0;
+ for(dciIndex = 0; dciIndex < dlTtiReqPdu->pdu.pdcch_pdu.numDlDci; dciIndex++)
+ {
+ dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[dciIndex].epre_ratio_of_pdcch_to_ssb = 0;
+ dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[dciIndex].epre_ratio_of_dmrs_to_ssb = 0;
+ }
}
return ROK;
{
GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
/* consider phy delay */
- ADD_DELTA_TO_TIME(currTimingInfo,dlTtiReqTimingInfo,PHY_DELTA_DL, macCb.macCell[cellIdx]->numOfSlots);
+ ADD_DELTA_TO_TIME(currTimingInfo,dlTtiReqTimingInfo,gConfigInfo.gPhyDeltaDl, macCb.macCell[cellIdx]->numOfSlots);
dlTtiReqTimingInfo.cellId = currTimingInfo.cellId;
macCellCfg = macCb.macCell[cellIdx]->macCellCfg;
/* PDSCH PDU */
fillPdschPdu(&dlTtiReq->pdus[numPduEncoded], &vendorMsg->p7_req_vendor.dl_tti_req.pdus[numPduEncoded],
- &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci.pdschCfg,
+ &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci[0].pdschCfg,
currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp,
pduIndex);
dlTtiReq->ue_grp_info[dlTtiReq->nGroup].pduIdx[pduIndex] = pduIndex;
if(dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode)
{
fillSib1TxDataReq(txDataReq->pdu_desc, pduIndex, &macCb.macCell[cellIdx]->macCellCfg, \
- &dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci.pdschCfg);
+ &dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci[0].pdschCfg);
pduIndex++;
MAC_FREE(dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg,sizeof(PdcchCfg));
txDataReq->num_pdus++;
#ifdef INTEL_FAPI
uint8_t getnPdus(fapi_ul_tti_req_t *ulTtiReq, MacUlSlot *currUlSlot)
{
- uint8_t pduCount = 0;
+ uint8_t pduCount = 0, ueIdx = 0;
if(ulTtiReq && currUlSlot)
{
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PRACH)
- {
- pduCount++;
- ulTtiReq->rachPresent++;
- }
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH)
- {
- pduCount++;
- ulTtiReq->nUlsch++;
- }
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH_UCI)
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_PRACH)
{
- pduCount++;
- ulTtiReq->nUlsch++;
+ pduCount++;
}
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_UCI)
+
+ for(ueIdx = 0; ueIdx < MAX_NUM_UE; ueIdx++)
{
- pduCount++;
- ulTtiReq->nUlcch++;
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_PUSCH)
+ {
+ if(currUlSlot->ulSchInfo.schPuschInfo[ueIdx].crnti != 0)
+ {
+ pduCount++;
+ }
+ }
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_PUSCH_UCI)
+ {
+ if(currUlSlot->ulSchInfo.schPuschUci[ueIdx].crnti != 0)
+ {
+ pduCount++;
+ }
+ }
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_UCI)
+ {
+ if(currUlSlot->ulSchInfo.schPucchInfo[ueIdx].crnti != 0)
+ {
+ pduCount++;
+ }
+ }
}
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_SRS)
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_SRS)
{
- pduCount++;
+ pduCount++;
}
}
return pduCount;
ulTtiReqPdu->pduType = PRACH_PDU_TYPE;
ulTtiReqPdu->pdu.prach_pdu.physCellId = macCellCfg->cellCfg.phyCellId;
ulTtiReqPdu->pdu.prach_pdu.numPrachOcas = \
- currUlSlot->ulInfo.prachSchInfo.numPrachOcas;
+ currUlSlot->ulSchInfo.prachSchInfo.numPrachOcas;
ulTtiReqPdu->pdu.prach_pdu.prachFormat = \
- currUlSlot->ulInfo.prachSchInfo.prachFormat;
- ulTtiReqPdu->pdu.prach_pdu.numRa = currUlSlot->ulInfo.prachSchInfo.numRa;
+ currUlSlot->ulSchInfo.prachSchInfo.prachFormat;
+ ulTtiReqPdu->pdu.prach_pdu.numRa = currUlSlot->ulSchInfo.prachSchInfo.numRa;
ulTtiReqPdu->pdu.prach_pdu.prachStartSymbol = \
- currUlSlot->ulInfo.prachSchInfo.prachStartSymb;
+ currUlSlot->ulSchInfo.prachSchInfo.prachStartSymb;
setNumCs(&ulTtiReqPdu->pdu.prach_pdu.numCs, macCellCfg);
ulTtiReqPdu->pdu.prach_pdu.beamforming.numPrgs = 0;
ulTtiReqPdu->pdu.prach_pdu.beamforming.prgSize = 0;
* RFAILED - failure
*
* ****************************************************************/
-void fillPuschPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, fapi_vendor_ul_tti_req_pdu_t *ulTtiVendorPdu, MacCellCfg *macCellCfg, MacUlSlot *currUlSlot)
+void fillPuschPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, fapi_vendor_ul_tti_req_pdu_t *ulTtiVendorPdu, MacCellCfg *macCellCfg,\
+ SchPuschInfo *puschInfo)
{
if(ulTtiReqPdu != NULLP)
{
ulTtiReqPdu->pduType = PUSCH_PDU_TYPE;
memset(&ulTtiReqPdu->pdu.pusch_pdu, 0, sizeof(fapi_ul_pusch_pdu_t));
ulTtiReqPdu->pdu.pusch_pdu.pduBitMap = 1;
- ulTtiReqPdu->pdu.pusch_pdu.rnti = currUlSlot->ulInfo.crnti;
+ ulTtiReqPdu->pdu.pusch_pdu.rnti = puschInfo->crnti;
/* TODO : Fill handle in raCb when scheduling pusch and access here */
ulTtiReqPdu->pdu.pusch_pdu.handle = 100;
ulTtiReqPdu->pdu.pusch_pdu.bwpSize = macCellCfg->cellCfg.initialUlBwp.bwp.numPrb;
ulTtiReqPdu->pdu.pusch_pdu.cyclicPrefix = \
macCellCfg->cellCfg.initialUlBwp.bwp.cyclicPrefix;
ulTtiReqPdu->pdu.pusch_pdu.targetCodeRate = 308;
- ulTtiReqPdu->pdu.pusch_pdu.qamModOrder = currUlSlot->ulInfo.schPuschInfo.tbInfo.qamOrder;
- ulTtiReqPdu->pdu.pusch_pdu.mcsIndex = currUlSlot->ulInfo.schPuschInfo.tbInfo.mcs;
- ulTtiReqPdu->pdu.pusch_pdu.mcsTable = currUlSlot->ulInfo.schPuschInfo.tbInfo.mcsTable;
+ ulTtiReqPdu->pdu.pusch_pdu.qamModOrder = puschInfo->tbInfo.qamOrder;
+ ulTtiReqPdu->pdu.pusch_pdu.mcsIndex = puschInfo->tbInfo.mcs;
+ ulTtiReqPdu->pdu.pusch_pdu.mcsTable = puschInfo->tbInfo.mcsTable;
ulTtiReqPdu->pdu.pusch_pdu.transformPrecoding = 1;
- ulTtiReqPdu->pdu.pusch_pdu.dataScramblingId = currUlSlot->ulInfo.cellId;
+ ulTtiReqPdu->pdu.pusch_pdu.dataScramblingId = macCellCfg->cellId;
ulTtiReqPdu->pdu.pusch_pdu.nrOfLayers = 1;
ulTtiReqPdu->pdu.pusch_pdu.ulDmrsSymbPos = 4;
ulTtiReqPdu->pdu.pusch_pdu.dmrsConfigType = 0;
- ulTtiReqPdu->pdu.pusch_pdu.ulDmrsScramblingId = currUlSlot->ulInfo.cellId;
+ ulTtiReqPdu->pdu.pusch_pdu.ulDmrsScramblingId = macCellCfg->cellId;
ulTtiReqPdu->pdu.pusch_pdu.scid = 0;
ulTtiReqPdu->pdu.pusch_pdu.numDmrsCdmGrpsNoData = 1;
ulTtiReqPdu->pdu.pusch_pdu.dmrsPorts = 0;
ulTtiReqPdu->pdu.pusch_pdu.resourceAlloc = \
- currUlSlot->ulInfo.schPuschInfo.fdAlloc.resAllocType;
+ puschInfo->fdAlloc.resAllocType;
ulTtiReqPdu->pdu.pusch_pdu.rbStart = \
- currUlSlot->ulInfo.schPuschInfo.fdAlloc.resAlloc.type1.startPrb;
+ puschInfo->fdAlloc.resAlloc.type1.startPrb;
ulTtiReqPdu->pdu.pusch_pdu.rbSize = \
- currUlSlot->ulInfo.schPuschInfo.fdAlloc.resAlloc.type1.numPrb;
+ puschInfo->fdAlloc.resAlloc.type1.numPrb;
ulTtiReqPdu->pdu.pusch_pdu.vrbToPrbMapping = 0;
ulTtiReqPdu->pdu.pusch_pdu.frequencyHopping = 0;
ulTtiReqPdu->pdu.pusch_pdu.txDirectCurrentLocation = 0;
ulTtiReqPdu->pdu.pusch_pdu.uplinkFrequencyShift7p5khz = 0;
ulTtiReqPdu->pdu.pusch_pdu.startSymbIndex = \
- currUlSlot->ulInfo.schPuschInfo.tdAlloc.startSymb;
+ puschInfo->tdAlloc.startSymb;
ulTtiReqPdu->pdu.pusch_pdu.nrOfSymbols = \
- currUlSlot->ulInfo.schPuschInfo.tdAlloc.numSymb;
+ puschInfo->tdAlloc.numSymb;
#ifdef INTEL_FAPI
ulTtiReqPdu->pdu.pusch_pdu.mappingType = \
- currUlSlot->ulInfo.schPuschInfo.dmrsMappingType;
+ puschInfo->dmrsMappingType;
ulTtiReqPdu->pdu.pusch_pdu.nrOfDmrsSymbols = \
- currUlSlot->ulInfo.schPuschInfo.nrOfDmrsSymbols;
+ puschInfo->nrOfDmrsSymbols;
ulTtiReqPdu->pdu.pusch_pdu.dmrsAddPos = \
- currUlSlot->ulInfo.schPuschInfo.dmrsAddPos;
+ puschInfo->dmrsAddPos;
#endif
ulTtiReqPdu->pdu.pusch_pdu.puschData.rvIndex = \
- currUlSlot->ulInfo.schPuschInfo.tbInfo.rv;
+ puschInfo->tbInfo.rv;
ulTtiReqPdu->pdu.pusch_pdu.puschData.harqProcessId = \
- currUlSlot->ulInfo.schPuschInfo.harqProcId;
+ puschInfo->harqProcId;
ulTtiReqPdu->pdu.pusch_pdu.puschData.newDataIndicator = \
- currUlSlot->ulInfo.schPuschInfo.tbInfo.ndi;
+ puschInfo->tbInfo.ndi;
ulTtiReqPdu->pdu.pusch_pdu.puschData.tbSize = \
- currUlSlot->ulInfo.schPuschInfo.tbInfo.tbSize;
+ puschInfo->tbInfo.tbSize;
/* numCb is 0 for new transmission */
ulTtiReqPdu->pdu.pusch_pdu.puschData.numCb = 0;
*
* ****************************************************************/
void fillPucchPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, fapi_vendor_ul_tti_req_pdu_t *ulTtiVendorPdu, MacCellCfg *macCellCfg,\
- MacUlSlot *currUlSlot)
+ SchPucchInfo *pucchInfo)
{
if(ulTtiReqPdu != NULLP)
{
ulTtiReqPdu->pduType = PUCCH_PDU_TYPE;
memset(&ulTtiReqPdu->pdu.pucch_pdu, 0, sizeof(fapi_ul_pucch_pdu_t));
- ulTtiReqPdu->pdu.pucch_pdu.rnti = currUlSlot->ulInfo.crnti;
+ ulTtiReqPdu->pdu.pucch_pdu.rnti = pucchInfo->crnti;
/* TODO : Fill handle in raCb when scheduling pucch and access here */
ulTtiReqPdu->pdu.pucch_pdu.handle = 100;
ulTtiReqPdu->pdu.pucch_pdu.bwpSize = macCellCfg->cellCfg.initialUlBwp.bwp.numPrb;
ulTtiReqPdu->pdu.pucch_pdu.bwpStart = macCellCfg->cellCfg.initialUlBwp.bwp.firstPrb;
ulTtiReqPdu->pdu.pucch_pdu.subCarrierSpacing = macCellCfg->cellCfg.initialUlBwp.bwp.scs;
ulTtiReqPdu->pdu.pucch_pdu.cyclicPrefix = macCellCfg->cellCfg.initialUlBwp.bwp.cyclicPrefix;
- ulTtiReqPdu->pdu.pucch_pdu.formatType = currUlSlot->ulInfo.schPucchInfo.pucchFormat; /* Supporting PUCCH Format 0 */
+ ulTtiReqPdu->pdu.pucch_pdu.formatType = pucchInfo->pucchFormat; /* Supporting PUCCH Format 0 */
ulTtiReqPdu->pdu.pucch_pdu.multiSlotTxIndicator = 0; /* No Multi Slot transmission */
- ulTtiReqPdu->pdu.pucch_pdu.prbStart = currUlSlot->ulInfo.schPucchInfo.fdAlloc.startPrb;
- ulTtiReqPdu->pdu.pucch_pdu.prbSize = currUlSlot->ulInfo.schPucchInfo.fdAlloc.numPrb;
- ulTtiReqPdu->pdu.pucch_pdu.startSymbolIndex = currUlSlot->ulInfo.schPucchInfo.tdAlloc.startSymb;
- ulTtiReqPdu->pdu.pucch_pdu.nrOfSymbols = currUlSlot->ulInfo.schPucchInfo.tdAlloc.numSymb;
- ulTtiReqPdu->pdu.pucch_pdu.freqHopFlag = currUlSlot->ulInfo.schPucchInfo.intraFreqHop;
- ulTtiReqPdu->pdu.pucch_pdu.secondHopPrb = currUlSlot->ulInfo.schPucchInfo.secondPrbHop;
+ ulTtiReqPdu->pdu.pucch_pdu.prbStart = pucchInfo->fdAlloc.startPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.prbSize = pucchInfo->fdAlloc.numPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.startSymbolIndex = pucchInfo->tdAlloc.startSymb;
+ ulTtiReqPdu->pdu.pucch_pdu.nrOfSymbols = pucchInfo->tdAlloc.numSymb;
+ ulTtiReqPdu->pdu.pucch_pdu.freqHopFlag = pucchInfo->intraFreqHop;
+ ulTtiReqPdu->pdu.pucch_pdu.secondHopPrb = pucchInfo->secondPrbHop;
ulTtiReqPdu->pdu.pucch_pdu.groupHopFlag = 0;
ulTtiReqPdu->pdu.pucch_pdu.sequenceHopFlag = 0;
ulTtiReqPdu->pdu.pucch_pdu.hoppingId = 0;
- ulTtiReqPdu->pdu.pucch_pdu.initialCyclicShift = currUlSlot->ulInfo.schPucchInfo.initialCyclicShift;
+ ulTtiReqPdu->pdu.pucch_pdu.initialCyclicShift = pucchInfo->initialCyclicShift;
ulTtiReqPdu->pdu.pucch_pdu.dataScramblingId = 0; /* Valid for Format 2, 3, 4 */
- ulTtiReqPdu->pdu.pucch_pdu.timeDomainOccIdx = currUlSlot->ulInfo.schPucchInfo.timeDomOCC;
- ulTtiReqPdu->pdu.pucch_pdu.preDftOccIdx = currUlSlot->ulInfo.schPucchInfo.occIdx; /* Valid for Format 4 only */
- ulTtiReqPdu->pdu.pucch_pdu.preDftOccLen = currUlSlot->ulInfo.schPucchInfo.occLen; /* Valid for Format 4 only */
- ulTtiReqPdu->pdu.pucch_pdu.pi2Bpsk = currUlSlot->ulInfo.schPucchInfo.pi2BPSK;
- ulTtiReqPdu->pdu.pucch_pdu.addDmrsFlag = currUlSlot->ulInfo.schPucchInfo.addDmrs;/* Valid for Format 3, 4 only */
+ ulTtiReqPdu->pdu.pucch_pdu.timeDomainOccIdx = pucchInfo->timeDomOCC;
+ ulTtiReqPdu->pdu.pucch_pdu.preDftOccIdx = pucchInfo->occIdx; /* Valid for Format 4 only */
+ ulTtiReqPdu->pdu.pucch_pdu.preDftOccLen = pucchInfo->occLen; /* Valid for Format 4 only */
+ ulTtiReqPdu->pdu.pucch_pdu.pi2Bpsk = pucchInfo->pi2BPSK;
+ ulTtiReqPdu->pdu.pucch_pdu.addDmrsFlag = pucchInfo->addDmrs;/* Valid for Format 3, 4 only */
ulTtiReqPdu->pdu.pucch_pdu.dmrsScramblingId = 0; /* Valid for Format 2 */
ulTtiReqPdu->pdu.pucch_pdu.dmrsCyclicShift = 0; /* Valid for Format 4 */
- ulTtiReqPdu->pdu.pucch_pdu.srFlag = currUlSlot->ulInfo.schPucchInfo.srFlag;
- ulTtiReqPdu->pdu.pucch_pdu.bitLenHarq = currUlSlot->ulInfo.schPucchInfo.harqInfo.harqBitLength;
+ ulTtiReqPdu->pdu.pucch_pdu.srFlag = pucchInfo->srFlag;
+ ulTtiReqPdu->pdu.pucch_pdu.bitLenHarq = pucchInfo->harqInfo.harqBitLength;
ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart1 = 0; /* Valid for Format 2, 3, 4 */
ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart2 = 0; /* Valid for Format 2, 3, 4 */
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.numPrgs = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.numPrgs;
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.prgSize = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.prgSize;
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.digBfInterface = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.digBfInterfaces;
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.prg[0].beamIdx[0];
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.numPrgs = pucchInfo->beamPucchInfo.numPrgs;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.prgSize = pucchInfo->beamPucchInfo.prgSize;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.digBfInterface = pucchInfo->beamPucchInfo.digBfInterfaces;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = pucchInfo->beamPucchInfo.prg[0].beamIdx[0];
ulTtiReqPdu->pduSize = sizeof(fapi_ul_pucch_pdu_t);
#ifdef INTEL_FAPI
uint16_t cellIdx =0;
uint8_t pduIdx = -1;
+ uint8_t ueIdx = 0;
SlotTimingInfo ulTtiReqTimingInfo;
MacUlSlot *currUlSlot = NULLP;
MacCellCfg macCellCfg;
macCellCfg = macCb.macCell[cellIdx]->macCellCfg;
/* add PHY delta */
- ADD_DELTA_TO_TIME(currTimingInfo,ulTtiReqTimingInfo,PHY_DELTA_UL, macCb.macCell[cellIdx]->numOfSlots);
+ ADD_DELTA_TO_TIME(currTimingInfo,ulTtiReqTimingInfo,gConfigInfo.gPhyDeltaUl, macCb.macCell[cellIdx]->numOfSlots);
currUlSlot = &macCb.macCell[cellIdx]->ulSlot[ulTtiReqTimingInfo.slot % macCb.macCell[cellIdx]->numOfSlots];
LWR_MAC_ALLOC(ulTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_ul_tti_req_t)));
if(ulTtiElem)
{
- FILL_FAPI_LIST_ELEM(ulTtiElem, NULLP, FAPI_UL_TTI_REQUEST, 1, \
- sizeof(fapi_ul_tti_req_t));
- ulTtiReq = (fapi_ul_tti_req_t *)(ulTtiElem +1);
- memset(ulTtiReq, 0, sizeof(fapi_ul_tti_req_t));
- fillMsgHeader(&ulTtiReq->header, FAPI_UL_TTI_REQUEST, sizeof(fapi_ul_tti_req_t));
- ulTtiReq->sfn = ulTtiReqTimingInfo.sfn;
- ulTtiReq->slot = ulTtiReqTimingInfo.slot;
- ulTtiReq->nPdus = getnPdus(ulTtiReq, currUlSlot);
- vendorUlTti->num_ul_pdu = ulTtiReq->nPdus;
- vendorUlTti->sym = 0;
- ulTtiReq->nGroup = 0;
- if(ulTtiReq->nPdus > 0)
- {
- /* Fill Prach Pdu */
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PRACH)
- {
- pduIdx++;
- fillPrachPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
- ulTtiReq->rachPresent++;
- }
-
- /* Fill PUSCH PDU */
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH)
- {
- pduIdx++;
- fillPuschPdu(&ulTtiReq->pdus[pduIdx], &vendorUlTti->ul_pdus[pduIdx], &macCellCfg, currUlSlot);
- ulTtiReq->nUlsch++;
- }
- /* Fill PUCCH PDU */
- if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_UCI)
- {
- pduIdx++;
- fillPucchPdu(&ulTtiReq->pdus[pduIdx], &vendorUlTti->ul_pdus[pduIdx], &macCellCfg, currUlSlot);
- ulTtiReq->nUlcch++;
- }
- }
+ FILL_FAPI_LIST_ELEM(ulTtiElem, NULLP, FAPI_UL_TTI_REQUEST, 1, \
+ sizeof(fapi_ul_tti_req_t));
+ ulTtiReq = (fapi_ul_tti_req_t *)(ulTtiElem +1);
+ memset(ulTtiReq, 0, sizeof(fapi_ul_tti_req_t));
+ fillMsgHeader(&ulTtiReq->header, FAPI_UL_TTI_REQUEST, sizeof(fapi_ul_tti_req_t));
+ ulTtiReq->sfn = ulTtiReqTimingInfo.sfn;
+ ulTtiReq->slot = ulTtiReqTimingInfo.slot;
+ ulTtiReq->nPdus = getnPdus(ulTtiReq, currUlSlot);
+ vendorUlTti->num_ul_pdu = ulTtiReq->nPdus;
+ vendorUlTti->sym = 0;
+ ulTtiReq->nGroup = 0;
+ if(ulTtiReq->nPdus > 0)
+ {
+#ifdef ODU_SLOT_IND_DEBUG_LOG
+ DU_LOG("\nDEBUG --> LWR_MAC: UL_TTI_REQ, datatype:%d, sfn/slot:%d/%d", currUlSlot->ulSchInfo.dataType, ulTtiReq->sfn, ulTtiReq->slot);
+#endif
+ /* Fill Prach Pdu */
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_PRACH)
+ {
+ pduIdx++;
+ fillPrachPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
+ ulTtiReq->rachPresent++;
+ }
+ for(ueIdx = 0; ueIdx < MAX_NUM_UE; ueIdx++)
+ {
+ /* Fill PUSCH PDU */
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_PUSCH)
+ {
+ if(currUlSlot->ulSchInfo.schPuschInfo[ueIdx].crnti != 0)
+ {
+#ifdef ODU_SLOT_IND_DEBUG_LOG
+ DU_LOG("\nDEBUG --> LWR_MAC: UL_TTI_REQ, PUSCH PDU ueId:%d", ueIdx);
+#endif
+ pduIdx++;
+ fillPuschPdu(&ulTtiReq->pdus[pduIdx], &vendorUlTti->ul_pdus[pduIdx], &macCellCfg, &currUlSlot->ulSchInfo.schPuschInfo[ueIdx]);
+ ulTtiReq->nUlsch++;
+ }
+ }
+ /* Fill PUCCH PDU */
+ if(currUlSlot->ulSchInfo.dataType & SCH_DATATYPE_UCI)
+ {
+ if(currUlSlot->ulSchInfo.schPucchInfo[ueIdx].crnti != 0)
+ {
+ pduIdx++;
+ fillPucchPdu(&ulTtiReq->pdus[pduIdx], &vendorUlTti->ul_pdus[pduIdx], &macCellCfg, &currUlSlot->ulSchInfo.schPucchInfo[ueIdx]);
+ ulTtiReq->nUlcch++;
+ }
+ }
+ }
+ ulTtiReq->ueGrpInfo[ulTtiReq->nGroup].nUe = MAX_NUM_UE_PER_TTI;
+ ulTtiReq->nGroup++;
+ }
#ifdef ODU_SLOT_IND_DEBUG_LOG
- DU_LOG("\nDEBUG --> LWR_MAC: Sending UL TTI Request");
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending UL TTI Request");
#endif
- prevElem->p_next = ulTtiElem;
+ prevElem->p_next = ulTtiElem;
- memset(currUlSlot, 0, sizeof(MacUlSlot));
- return ROK;
+ memset(currUlSlot, 0, sizeof(MacUlSlot));
+ return ROK;
}
else
{
- DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for UL TTI Request");
- memset(currUlSlot, 0, sizeof(MacUlSlot));
- return RFAILED;
+ DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for UL TTI Request");
+ memset(currUlSlot, 0, sizeof(MacUlSlot));
+ return RFAILED;
}
}
else
{
- lwr_mac_procInvalidEvt(&currTimingInfo);
+ lwr_mac_procInvalidEvt(&currTimingInfo);
}
#endif
return ROK;
ulDciReqPdu->pdcchPduConfig.cyclicPrefix = dlInfo->ulGrant->bwpCfg.cyclicPrefix;
ulDciReqPdu->pdcchPduConfig.startSymbolIndex = dlInfo->ulGrant->coresetCfg.startSymbolIndex;
ulDciReqPdu->pdcchPduConfig.durationSymbols = dlInfo->ulGrant->coresetCfg.durationSymbols;
- memcpy(ulDciReqPdu->pdcchPduConfig.freqDomainResource, dlInfo->ulGrant->coresetCfg.freqDomainResource, 6);
+ convertFreqDomRsrcMapToIAPIFormat(dlInfo->ulGrant->coresetCfg.freqDomainResource, \
+ ulDciReqPdu->pdcchPduConfig.freqDomainResource);
ulDciReqPdu->pdcchPduConfig.cceRegMappingType = dlInfo->ulGrant->coresetCfg.cceRegMappingType;
ulDciReqPdu->pdcchPduConfig.regBundleSize = dlInfo->ulGrant->coresetCfg.regBundleSize;
ulDciReqPdu->pdcchPduConfig.interleaverSize = dlInfo->ulGrant->coresetCfg.interleaverSize;
Code Review / o-du / l2.git / blobdiff