uint16_t sendTxDataReq(SlotTimingInfo currTimingInfo, MacDlSlot *dlSlot, p_fapi_api_queue_elem_t prevElem, fapi_vendor_tx_data_req_t *vendorTxDataReq);
uint16_t fillUlTtiReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t prevElem, fapi_vendor_ul_tti_req_t* vendorUlTti);
uint16_t fillUlDciReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t prevElem, fapi_vendor_ul_dci_req_t *vendorUlDciReq);
-uint8_t lwr_mac_procStopReqEvt(SlotTimingInfo slotInfo, p_fapi_api_queue_elem_t prevElem);
+uint8_t lwr_mac_procStopReqEvt(SlotTimingInfo slotInfo, p_fapi_api_queue_elem_t prevElem, fapi_stop_req_vendor_msg_t *vendorMsg);
void lwrMacLayerInit(Region region, Pool pool)
{
*
********************************************************************/
-uint8_t lwr_mac_procStopReqEvt(SlotTimingInfo slotInfo, p_fapi_api_queue_elem_t prevElem)
+uint8_t lwr_mac_procStopReqEvt(SlotTimingInfo slotInfo, p_fapi_api_queue_elem_t prevElem, fapi_stop_req_vendor_msg_t *vendorMsg)
{
#ifdef INTEL_FAPI
#ifdef CALL_FLOW_DEBUG_LOG
#endif
fapi_stop_req_t *stopReq;
- fapi_vendor_msg_t *vendorMsg;
p_fapi_api_queue_elem_t stopReqElem;
- p_fapi_api_queue_elem_t vendorMsgElem;
- /* Allocte And fill Vendor msg */
- LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
- if(!vendorMsgElem)
- {
- DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in stop req");
- return RFAILED;
- }
- FILL_FAPI_LIST_ELEM(vendorMsgElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
- vendorMsg = (fapi_vendor_msg_t *)(vendorMsgElem + 1);
- fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
- vendorMsg->stop_req_vendor.sfn = slotInfo.sfn;
- vendorMsg->stop_req_vendor.slot = slotInfo.slot;
+ vendorMsg->sfn = slotInfo.sfn;
+ vendorMsg->slot = slotInfo.slot;
/* Fill FAPI stop req */
LWR_MAC_ALLOC(stopReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_stop_req_t)));
if(!stopReqElem)
{
DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for stop req");
- LWR_MAC_FREE(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
return RFAILED;
}
- FILL_FAPI_LIST_ELEM(stopReqElem, vendorMsgElem, FAPI_STOP_REQUEST, 1, \
- sizeof(fapi_stop_req_t));
+ FILL_FAPI_LIST_ELEM(stopReqElem, NULLP, FAPI_STOP_REQUEST, 1, sizeof(fapi_stop_req_t));
stopReq = (fapi_stop_req_t *)(stopReqElem + 1);
memset(stopReq, 0, sizeof(fapi_stop_req_t));
fillMsgHeader(&stopReq->header, FAPI_STOP_REQUEST, sizeof(fapi_stop_req_t));
dlTtiReqPdu->pdu.ssb_pdu.physCellId = macCellCfg->phyCellId;
dlTtiReqPdu->pdu.ssb_pdu.betaPss = macCellCfg->ssbCfg.betaPss;
dlTtiReqPdu->pdu.ssb_pdu.ssbBlockIndex = currDlSlot->dlInfo.brdcstAlloc.ssbInfo[ssbIdxCount].ssbIdx;
- dlTtiReqPdu->pdu.ssb_pdu.ssbSubCarrierOffset = macCellCfg->ssbCfg.ssbScOffset;
+ dlTtiReqPdu->pdu.ssb_pdu.ssbSubCarrierOffset = macCellCfg->ssbCfg.ssbScOffset;;
/* ssbOfPdufstA to be filled in ssbCfg */
- dlTtiReqPdu->pdu.ssb_pdu.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;
+ dlTtiReqPdu->pdu.ssb_pdu.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;;
dlTtiReqPdu->pdu.ssb_pdu.bchPayloadFlag = macCellCfg->ssbCfg.bchPayloadFlag;
/* Bit manipulation for SFN */
setMibPdu(macCellCfg->ssbCfg.mibPdu, &mibPayload, sfn);
dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming. \
pmi_bfi[0].beamIdx[0].beamidx = macCellCfg->ssbCfg.beamId[0];
dlTtiReqPdu->pduSize = sizeof(fapi_dl_ssb_pdu_t); /* Size of SSB PDU */
-
return ROK;
}
return RFAILED;
dlDciPtr->pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
- dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
dlDciPtr->powerControlOffsetSS = sib1PdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
/* Calculating freq domain resource allocation field value and size
* Spec 38.214 Sec 5.1.2.2.2
*/
coreset0Size= sib1PdcchInfo->coresetCfg.coreSetSize;
- rbStart = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
- rbLen = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
+ rbStart = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.startPrb;
+ rbLen = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.numPrb;
if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
{
dlDciPtr->pc_and_bform.digBfInterfaces = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.digBfInterfaces;
dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.prg[0].pmIdx;
dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.prg[0].beamIdx[0];
- dlDciPtr->beta_pdcch_1_0 = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.powerValue;
+ dlDciPtr->beta_pdcch_1_0 = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.beta_pdcch_1_0;
dlDciPtr->powerControlOffsetSS = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.powerControlOffsetSS;
/* Calculating freq domain resource allocation field value and size
* Spec 38.214 Sec 5.1.2.2.2
*/
coreset0Size = dlPageAlloc->pagePdcchCfg.coresetCfg.coreSetSize;
- rbStart = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
- rbLen = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
+ rbStart = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.startPrb;
+ rbLen = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.numPrb;
if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
{
uint8_t modNCodSchemeSize = 5;
uint8_t tbScalingSize = 2;
uint8_t reservedSize = 16;
-
+
dlDciPtr->rnti = rarPdcchInfo->dci.rnti;
dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId;
dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti;
dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
- dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
dlDciPtr->powerControlOffsetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
/* Calculating freq domain resource allocation field value and size
/* TODO: Fill values of coreset0Size, rbStart and rbLen */
coreset0Size= rarPdcchInfo->coresetCfg.coreSetSize;
- rbStart = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
- rbLen = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
+ rbStart = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.startPrb;
+ rbLen = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.numPrb;
if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
{
dlDciPtr->pc_and_bform.digBfInterfaces = pdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
- dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
dlDciPtr->powerControlOffsetSS = pdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
/* Calculating freq domain resource allocation field value and size
* Spec 38.214 Sec 5.1.2.2.2
*/
coresetSize = pdcchInfo->coresetCfg.coreSetSize;
- rbStart = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
- rbLen = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
+ rbStart = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.startPrb;
+ rbLen = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.numPrb;
if((rbLen >=1) && (rbLen <= coresetSize - rbStart))
{
dlTtiReqPdu->pdu.pdsch_pdu.dmrsPorts = pdschInfo->dmrs.dmrsPorts;
dlTtiReqPdu->pdu.pdsch_pdu.resourceAlloc = pdschInfo->pdschFreqAlloc.resourceAllocType;
/* since we are using type-1, hence rbBitmap excluded */
- dlTtiReqPdu->pdu.pdsch_pdu.rbStart = pdschInfo->pdschFreqAlloc.freqAlloc.startPrb;
- dlTtiReqPdu->pdu.pdsch_pdu.rbSize = pdschInfo->pdschFreqAlloc.freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.rbStart = pdschInfo->pdschFreqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.rbSize = pdschInfo->pdschFreqAlloc.numPrb;
dlTtiReqPdu->pdu.pdsch_pdu.vrbToPrbMapping = pdschInfo->pdschFreqAlloc.vrbPrbMapping;
- dlTtiReqPdu->pdu.pdsch_pdu.startSymbIndex = pdschInfo->pdschTimeAlloc.timeAlloc.startSymb;
- dlTtiReqPdu->pdu.pdsch_pdu.nrOfSymbols = pdschInfo->pdschTimeAlloc.timeAlloc.numSymb;
+ dlTtiReqPdu->pdu.pdsch_pdu.startSymbIndex = pdschInfo->pdschTimeAlloc.startSymb;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfSymbols = pdschInfo->pdschTimeAlloc.numSymb;
dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.numPrgs = pdschInfo->beamPdschInfo.numPrgs;
dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.prgSize = pdschInfo->beamPdschInfo.prgSize;
dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.digBfInterfaces = pdschInfo->beamPdschInfo.digBfInterfaces;
if(dlSlot->dlInfo.isBroadcastPres)
{
- if(dlSlot->dlInfo.brdcstAlloc.ssbTrans)
+ if(dlSlot->dlInfo.brdcstAlloc.ssbTransmissionMode)
{
for(idx = 0; idx < dlSlot->dlInfo.brdcstAlloc.ssbIdxSupported; idx++)
{
count++;
}
}
- if(dlSlot->dlInfo.brdcstAlloc.sib1Trans)
+ if(dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode)
{
/* PDCCH and PDSCH PDU is filled */
count += 2;
{
uint8_t idx = 0, count = 0, ueIdx=0;
- if(dlSlot->dlInfo.isBroadcastPres && dlSlot->dlInfo.brdcstAlloc.sib1Trans)
+ if(dlSlot->dlInfo.isBroadcastPres && dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode)
{
count++;
}
*
* ********************************************************************/
uint8_t fillSib1TxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, MacCellCfg *macCellCfg,
- PdschCfg pdschCfg)
+ PdschCfg *pdschCfg)
{
uint32_t payloadSize = 0;
uint8_t *sib1Payload = NULLP;
pduDesc[pduIndex].num_tlvs = 1;
/* fill the TLV */
- payloadSize = pdschCfg.codeword[0].tbSize;
+ payloadSize = pdschCfg->codeword[0].tbSize;
pduDesc[pduIndex].tlvs[0].tl.tag = ((payloadSize & 0xff0000) >> 8) | FAPI_TX_DATA_PTR_TO_PAYLOAD_64;
pduDesc[pduIndex].tlvs[0].tl.length = (payloadSize & 0x0000ffff);
LWR_MAC_ALLOC(sib1Payload, payloadSize);
{
if(currDlSlot->dlInfo.isBroadcastPres)
{
- if(currDlSlot->dlInfo.brdcstAlloc.ssbTrans)
+ if(currDlSlot->dlInfo.brdcstAlloc.ssbTransmissionMode)
{
if(dlTtiReq->pdus != NULLP)
{
DU_LOG("\033[0m");
}
- if(currDlSlot->dlInfo.brdcstAlloc.sib1Trans)
+ if(currDlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode)
{
/* Filling SIB1 param */
if(numPduEncoded != nPdu)
{
- rntiType = SI_RNTI_TYPE;
+ if(currDlSlot->dlInfo.brdcstAlloc.crnti == SI_RNTI)
+ rntiType = SI_RNTI_TYPE;
/* PDCCH PDU */
fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], &vendorMsg->p7_req_vendor.dl_tti_req.pdus[numPduEncoded],
/* PDSCH PDU */
fillPdschPdu(&dlTtiReq->pdus[numPduEncoded], &vendorMsg->p7_req_vendor.dl_tti_req.pdus[numPduEncoded],
- &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg,
+ currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg.dci.pdschCfg,
currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp,
pduIndex);
dlTtiReq->ue_grp_info[dlTtiReq->nGroup].pduIdx[pduIndex] = pduIndex;
if(macCb.macCell[cellIdx]->state == CELL_TO_BE_STOPPED)
{
/* Intel L1 expects UL_DCI.request following DL_TTI.request */
- lwr_mac_procStopReqEvt(currTimingInfo, prevElem);
+ lwr_mac_procStopReqEvt(currTimingInfo, prevElem, &(vendorMsg->stop_req_vendor));
msgHeader->num_msg++;
macCb.macCell[cellIdx]->state = CELL_STOP_IN_PROGRESS;
- prevElem = prevElem->p_next;
+ prevElem = prevElem->p_next;
}
prevElem->p_next = vendorMsgQElem;
LwrMacSendToL1(headerElem);
txDataReq->sfn = currTimingInfo.sfn;
txDataReq->slot = currTimingInfo.slot;
- if(dlSlot->dlInfo.brdcstAlloc.sib1Trans)
+ if(dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode)
{
fillSib1TxDataReq(txDataReq->pdu_desc, pduIndex, &macCb.macCell[cellIdx]->macCellCfg, \
- dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg);
+ dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg.dci.pdschCfg);
pduIndex++;
txDataReq->num_pdus++;
}
ulTtiReqPdu->pdu.pusch_pdu.numDmrsCdmGrpsNoData = 1;
ulTtiReqPdu->pdu.pusch_pdu.dmrsPorts = 0;
ulTtiReqPdu->pdu.pusch_pdu.resourceAlloc = \
- currUlSlot->ulInfo.schPuschInfo.resAllocType;
+ currUlSlot->ulInfo.schPuschInfo.fdAlloc.resAllocType;
ulTtiReqPdu->pdu.pusch_pdu.rbStart = \
- currUlSlot->ulInfo.schPuschInfo.fdAlloc.startPrb;
+ currUlSlot->ulInfo.schPuschInfo.fdAlloc.resAlloc.type1.startPrb;
ulTtiReqPdu->pdu.pusch_pdu.rbSize = \
- currUlSlot->ulInfo.schPuschInfo.fdAlloc.numPrb;
+ currUlSlot->ulInfo.schPuschInfo.fdAlloc.resAlloc.type1.numPrb;
ulTtiReqPdu->pdu.pusch_pdu.vrbToPrbMapping = 0;
ulTtiReqPdu->pdu.pusch_pdu.frequencyHopping = 0;
ulTtiReqPdu->pdu.pusch_pdu.txDirectCurrentLocation = 0;
currUlSlot->ulInfo.schPuschInfo.tdAlloc.startSymb;
ulTtiReqPdu->pdu.pusch_pdu.nrOfSymbols = \
currUlSlot->ulInfo.schPuschInfo.tdAlloc.numSymb;
+#ifdef INTEL_FAPI
ulTtiReqPdu->pdu.pusch_pdu.mappingType = \
currUlSlot->ulInfo.schPuschInfo.dmrsMappingType;
ulTtiReqPdu->pdu.pusch_pdu.nrOfDmrsSymbols = \
currUlSlot->ulInfo.schPuschInfo.nrOfDmrsSymbols;
ulTtiReqPdu->pdu.pusch_pdu.dmrsAddPos = \
currUlSlot->ulInfo.schPuschInfo.dmrsAddPos;
+#endif
ulTtiReqPdu->pdu.pusch_pdu.puschData.rvIndex = \
currUlSlot->ulInfo.schPuschInfo.tbInfo.rv;
ulTtiReqPdu->pdu.pusch_pdu.puschData.harqProcessId = \
{
ulTtiReqPdu->pduType = PUCCH_PDU_TYPE;
memset(&ulTtiReqPdu->pdu.pucch_pdu, 0, sizeof(fapi_ul_pucch_pdu_t));
- ulTtiReqPdu->pdu.pucch_pdu.rnti = currUlSlot->ulInfo.schPucchInfo.rnti;
+ ulTtiReqPdu->pdu.pucch_pdu.rnti = currUlSlot->ulInfo.crnti;
/* TODO : Fill handle in raCb when scheduling pucch and access here */
ulTtiReqPdu->pdu.pucch_pdu.handle = 100;
ulTtiReqPdu->pdu.pucch_pdu.bwpSize = macCellCfg->initialUlBwp.bwp.numPrb;
ulTtiReqPdu->pdu.pucch_pdu.formatType = currUlSlot->ulInfo.schPucchInfo.pucchFormat; /* Supporting PUCCH Format 0 */
ulTtiReqPdu->pdu.pucch_pdu.multiSlotTxIndicator = 0; /* No Multi Slot transmission */
- ulTtiReqPdu->pdu.pucch_pdu.prbStart = currUlSlot->ulInfo.schPucchInfo.fdAlloc.startPrb;
- ulTtiReqPdu->pdu.pucch_pdu.prbSize = currUlSlot->ulInfo.schPucchInfo.fdAlloc.numPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.prbStart = currUlSlot->ulInfo.schPucchInfo.fdAlloc.resAlloc.type1.startPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.prbSize = currUlSlot->ulInfo.schPucchInfo.fdAlloc.resAlloc.type1.numPrb;
ulTtiReqPdu->pdu.pucch_pdu.startSymbolIndex = currUlSlot->ulInfo.schPucchInfo.tdAlloc.startSymb;
ulTtiReqPdu->pdu.pucch_pdu.nrOfSymbols = currUlSlot->ulInfo.schPucchInfo.tdAlloc.numSymb;
ulTtiReqPdu->pdu.pucch_pdu.freqHopFlag = currUlSlot->ulInfo.schPucchInfo.intraFreqHop;
ulTtiReqPdu->pdu.pucch_pdu.timeDomainOccIdx = currUlSlot->ulInfo.schPucchInfo.timeDomOCC;
ulTtiReqPdu->pdu.pucch_pdu.preDftOccIdx = currUlSlot->ulInfo.schPucchInfo.occIdx; /* Valid for Format 4 only */
ulTtiReqPdu->pdu.pucch_pdu.preDftOccLen = currUlSlot->ulInfo.schPucchInfo.occLen; /* Valid for Format 4 only */
- ulTtiReqPdu->pdu.pucch_pdu.pi2Bpsk = currUlSlot->ulInfo.schPucchInfo.cmnFormatCfg.pi2BPSK;
- ulTtiReqPdu->pdu.pucch_pdu.addDmrsFlag = currUlSlot->ulInfo.schPucchInfo.cmnFormatCfg.addDmrs;/* Valid for Format 3, 4 only */
+ ulTtiReqPdu->pdu.pucch_pdu.pi2Bpsk = currUlSlot->ulInfo.schPucchInfo.pi2BPSK;
+ ulTtiReqPdu->pdu.pucch_pdu.addDmrsFlag = currUlSlot->ulInfo.schPucchInfo.addDmrs;/* Valid for Format 3, 4 only */
ulTtiReqPdu->pdu.pucch_pdu.dmrsScramblingId = 0; /* Valid for Format 2 */
ulTtiReqPdu->pdu.pucch_pdu.dmrsCyclicShift = 0; /* Valid for Format 4 */
ulTtiReqPdu->pdu.pucch_pdu.srFlag = currUlSlot->ulInfo.schPucchInfo.srFlag;
- ulTtiReqPdu->pdu.pucch_pdu.bitLenHarq = currUlSlot->ulInfo.schPucchInfo.numHarqBits;
+ ulTtiReqPdu->pdu.pucch_pdu.bitLenHarq = currUlSlot->ulInfo.schPucchInfo.harqInfo.harqBitLength;
ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart1 = 0; /* Valid for Format 2, 3, 4 */
ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart2 = 0; /* Valid for Format 2, 3, 4 */
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.numPrgs = 0; /* Not Supported */
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.prgSize = 0;
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.digBfInterface = 0;
- ulTtiReqPdu->pdu.pucch_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = 0;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.numPrgs = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.numPrgs;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.prgSize = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.prgSize;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.digBfInterface = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.digBfInterfaces;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = currUlSlot->ulInfo.schPucchInfo.beamPucchInfo.prg[0].beamIdx[0];
ulTtiReqPdu->pduSize = sizeof(fapi_ul_pucch_pdu_t);
ulDciPtr->pc_and_bform.digBfInterfaces = schDciInfo->dciInfo.beamPdcchInfo.digBfInterfaces;
ulDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].pmIdx;
ulDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0];
- ulDciPtr->beta_pdcch_1_0 = schDciInfo->dciInfo.txPdcchPower.powerValue;
+ ulDciPtr->beta_pdcch_1_0 = schDciInfo->dciInfo.txPdcchPower.beta_pdcch_1_0;
ulDciPtr->powerControlOffsetSS = schDciInfo->dciInfo.txPdcchPower.powerControlOffsetSS;
/* Calculating freq domain resource allocation field value and size
* RBLen = length of contiguously allocted RBs
* Spec 38.214 Sec 5.1.2.2.2
*/
- if(schDciInfo->formatType == FORMAT0_0)
+ if(schDciInfo->dciFormatInfo.formatType == FORMAT0_0)
{
coreset1Size = schDciInfo->coresetCfg.coreSetSize;
- rbLen = schDciInfo->format.format0_0.freqAlloc.numPrb;
- rbStart = schDciInfo->format.format0_0.freqAlloc.startPrb;
+ rbLen = schDciInfo->dciFormatInfo.format.format0_0.freqAlloc.resAlloc.type1.numPrb;
+ rbStart = schDciInfo->dciFormatInfo.format.format0_0.freqAlloc.resAlloc.type1.startPrb;
if((rbLen >=1) && (rbLen <= coreset1Size - rbStart))
{
freqDomResAssignSize = ceil(log2(coreset1Size * (coreset1Size + 1) / 2));
}
/* Fetching DCI field values */
- dciFormatId = schDciInfo->formatType; /* DCI indentifier for UL DCI */
- timeDomResAssign = schDciInfo->format.format0_0.rowIndex;
- freqHopFlag = schDciInfo->format.format0_0.freqHopFlag;
- modNCodScheme = schDciInfo->format.format0_0.mcs;
- ndi = schDciInfo->format.format0_0.ndi;
- redundancyVer = schDciInfo->format.format0_0.rv;
- harqProcessNum = schDciInfo->format.format0_0.harqProcId;
- puschTpc = schDciInfo->format.format0_0.tpcCmd;
- ul_SlInd = schDciInfo->format.format0_0.sUlCfgd;
+ dciFormatId = schDciInfo->dciFormatInfo.formatType; /* DCI indentifier for UL DCI */
+ timeDomResAssign = schDciInfo->dciFormatInfo.format.format0_0.rowIndex;
+ freqHopFlag = schDciInfo->dciFormatInfo.format.format0_0.freqHopFlag;
+ modNCodScheme = schDciInfo->dciFormatInfo.format.format0_0.mcs;
+ ndi = schDciInfo->dciFormatInfo.format.format0_0.ndi;
+ redundancyVer = schDciInfo->dciFormatInfo.format.format0_0.rvIndex;
+ harqProcessNum = schDciInfo->dciFormatInfo.format.format0_0.harqProcId;
+ puschTpc = schDciInfo->dciFormatInfo.format.format0_0.tpcCmd;
+ ul_SlInd = schDciInfo->dciFormatInfo.format.format0_0.sulIndicator;
/* Reversing bits in each DCI field */
dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
Code Review / o-du / l2.git / blobdiff