+/* MACRO definitions for modulcation order */
+#define MOD_ORDER_QPSK 2
+#define MOD_ORDER_QAM16 4
+#define MOD_ORDER_QAM64 6
+#define MOD_ORDER_QAM256 8
+#define PDSCH_MCS_INDEX 20 /* For 64QAM, valid mcs index: 17-28 in 38.214 - Table 5.1.3.1-1*/
+#define PUSCH_MCS_INDEX 10 /* For 16QAM, valid mcs index: 10-16 in 38.214 - Table 5.1.3.1-1*/
+
+/*VALID Tunnel ID*/
+#define MIN_TEID 1 /*[Spec 29.281,Sec 5.1]: All Zero TEIDs are never assigned for setting up GTP-U Tunnel*/
+#define MAX_TEID MAX_NUM_DRB * MAX_NUM_UE /*[Spec 29.281]: Max limit is not mentioned but as per GTP-U Header Format, TEID occupies 4 octets */
+
+/* Slice Ratio */
+#define MAX_RATIO 30
+#define MIN_RATIO 20
+#define DEDICATED_RATIO 10
+#define NUM_OF_SUPPORTED_SLICE 2
+
+#ifdef NR_DRX
+/* Macros for Drx configuration */
+#define DRX_ONDURATION_TIMER_VALUE_PRESENT_IN_MS true
+#define DRX_ONDURATION_TIMER_VALUE_IN_SUBMS 32
+#define DRX_ONDURATION_TIMER_VALUE_IN_MS 10
+#define DRX_INACTIVITY_TIMER 2
+#define DRX_HARQ_RTT_TIMER_DL 56
+#define DRX_HARQ_RTT_TIMER_UL 56
+#define DRX_RETRANSMISSION_TIMER_DL 4
+#define DRX_RETRANSMISSION_TIMER_UL 4
+#define DRX_LONG_CYCLE_START_OFFSET_CHOICE 40
+#define DRX_LONG_CYCLE_START_OFFSET_VAL 8
+#define DRX_SHORT_CYCLE_PRESENT true
+#define DRX_SHORT_CYCLE 2
+#define DRX_SHORT_CYCLE_TIMER 2
+#define DRX_SLOT_OFFSET 0