+ /* Fill received Ue Configuration in UeCb */
+ memset(ueCb, 0, sizeof(SchUeCb));
+ ueCb->ueId = ueCfg->ueId;
+ ueCb->crnti = ueCfg->crnti;
+ if(ueCb->crnti)
+ ueCb->state = SCH_UE_STATE_ACTIVE;
+ else
+ ueCb->state = SCH_UE_HANDIN_IN_PROGRESS;
+
+ ret = fillSchUeCb(inst, ueCb, ueCfg);
+ if(ret == ROK)
+ {
+ if(ueCb->state == SCH_UE_STATE_ACTIVE)
+ {
+ cellCb->numActvUe++;
+ SET_ONE_BIT(ueCb->ueId, cellCb->actvUeBitMap);
+ }
+ ueCb->cellCb = cellCb;
+ ueCb->srRcvd = false;
+ ueCb->bsrRcvd = false;
+ for(lcIdx=0; lcIdx<MAX_NUM_LOGICAL_CHANNEL_GROUPS; lcIdx++)
+ ueCb->bsrInfo[lcIdx].dataVol = 0;
+
+ SchSendUeCfgRspToMac(pst->event, ueCfg, inst, RSP_OK, &cfgRsp);
+ }
+ return ret;
+}
+
+/*******************************************************************
+*
+* @brief Fills PUSCH UL allocation
+*
+* @details
+*
+* Function : schFillPuschAlloc
+*
+* Functionality: fills PUSCH info
+*
+* @params[in]
+* @return ROK - success
+* RFAILED - failure
+*
+* ****************************************************************/
+uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
+ uint8_t startSymb, uint8_t symbLen, uint16_t startPrb)
+{
+ uint8_t numRb = 0;
+ SchCellCb *cellCb = NULLP;
+ SchUlSlotInfo *schUlSlotInfo = NULLP;
+ SchPuschInfo puschInfo;
+
+ if(ueCb == NULLP)
+ {
+ DU_LOG("\nERROR --> SCH: UE CB is empty");
+ return RFAILED;
+ }
+
+ cellCb = ueCb->cellCb;
+ if(cellCb == NULLP)
+ {
+ DU_LOG("\nERROR --> SCH: CELL CB is empty");
+ return RFAILED;
+ }
+
+ tbSize += UL_TX_BUFFER_SIZE; /* 2 bytes header + some buffer */
+ numRb = schCalcNumPrb(tbSize, ueCb->ueCfg.ulModInfo.mcsIndex, symbLen);
+ allocatePrbUl(cellCb, puschTime, startSymb, symbLen, &startPrb, numRb);
+
+ puschInfo.crnti = ueCb->crnti;
+ puschInfo.harqProcId = SCH_HARQ_PROC_ID;
+ puschInfo.resAllocType = SCH_ALLOC_TYPE_1;
+ puschInfo.fdAlloc.startPrb = startPrb;
+ puschInfo.fdAlloc.numPrb = numRb;
+ puschInfo.tdAlloc.startSymb = startSymb;
+ puschInfo.tdAlloc.numSymb = symbLen;
+ puschInfo.tbInfo.qamOrder = ueCb->ueCfg.ulModInfo.modOrder;
+ puschInfo.tbInfo.mcs = ueCb->ueCfg.ulModInfo.mcsIndex;
+ puschInfo.tbInfo.mcsTable = ueCb->ueCfg.ulModInfo.mcsTable;
+ puschInfo.tbInfo.ndi = 1; /* new transmission */
+ puschInfo.tbInfo.rv = 0;
+ puschInfo.tbInfo.tbSize = tbSize;
+ puschInfo.dmrsMappingType = DMRS_MAP_TYPE_A; /* Setting Type-A */
+ puschInfo.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
+ puschInfo.dmrsAddPos = DMRS_ADDITIONAL_POS;
+
+ schUlSlotInfo = cellCb->schUlSlotInfo[puschTime.slot];
+ SCH_ALLOC(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
+ if(!schUlSlotInfo->schPuschInfo)
+ {
+ DU_LOG("\nERROR --> SCH: Memory allocation failed in schAllocMsg3Pusch");
+ return RFAILED;
+ }
+ memcpy(schUlSlotInfo->schPuschInfo, &puschInfo, sizeof(SchPuschInfo));
+
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief Fills DCI for UL grant
+ *
+ * @details
+ *
+ * Function : schFillUlDci
+ *
+ * Functionality: fills DCI for UL grant in response to BSR
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo)
+{
+ SchCellCb *cellCb = ueCb->cellCb;
+ SchControlRsrcSet coreset1 ;
+
+ memset(&coreset1, 0, sizeof(SchControlRsrcSet));
+ if(ueCb->ueCfg.spCellCfgPres == true)
+ {
+ coreset1 = ueCb->ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
+ }
+
+ dciInfo->cellId = cellCb->cellId;
+ dciInfo->crnti = ueCb->crnti;
+
+ /* fill bwp cfg */
+ dciInfo->bwpCfg.subcarrierSpacing = cellCb->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
+ dciInfo->bwpCfg.cyclicPrefix = cellCb->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
+ dciInfo->bwpCfg.freqAlloc.startPrb = cellCb->cellCfg.schInitialDlBwp.bwp.freqAlloc.startPrb;
+ dciInfo->bwpCfg.freqAlloc.numPrb = cellCb->cellCfg.schInitialDlBwp.bwp.freqAlloc.numPrb;
+
+ /*fill coreset cfg */
+ //Considering number of RBs in coreset1 is same as coreset0
+ dciInfo->coresetCfg.coreSetSize = coresetIdxTable[0][1];
+ //Considering coreset1 also starts from same symbol as coreset0
+ dciInfo->coresetCfg.startSymbolIndex = searchSpaceIdxTable[0][3];
+ dciInfo->coresetCfg.durationSymbols = coreset1.duration;
+ memcpy(dciInfo->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
+
+ dciInfo->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
+ dciInfo->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
+ dciInfo->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
+ dciInfo->coresetCfg.coreSetType = 1; /* non PBCH coreset */
+ dciInfo->coresetCfg.shiftIndex = cellCb->cellCfg.phyCellId;
+ dciInfo->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
+ dciInfo->coresetCfg.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
+ dciInfo->coresetCfg.aggregationLevel = 4; /* same as for sib1 */
+
+ dciInfo->formatType = FORMAT0_0;
+
+ /* fill UL grant */
+ dciInfo->format.format0_0.resourceAllocType = puschInfo->resAllocType;
+ dciInfo->format.format0_0.freqAlloc.startPrb = puschInfo->fdAlloc.startPrb;
+ dciInfo->format.format0_0.freqAlloc.numPrb = puschInfo->fdAlloc.numPrb;
+ dciInfo->format.format0_0.timeAlloc.startSymb = puschInfo->tdAlloc.startSymb;
+ dciInfo->format.format0_0.timeAlloc.numSymb = puschInfo->tdAlloc.numSymb;
+ dciInfo->format.format0_0.rowIndex = 0; /* row Index */
+ dciInfo->format.format0_0.mcs = puschInfo->tbInfo.mcs;
+ dciInfo->format.format0_0.harqProcId = puschInfo->harqProcId;
+ dciInfo->format.format0_0.puschHopFlag = FALSE; /* disabled */
+ dciInfo->format.format0_0.freqHopFlag = FALSE; /* disabled */
+ dciInfo->format.format0_0.ndi = puschInfo->tbInfo.ndi; /* new transmission */
+ dciInfo->format.format0_0.rv = puschInfo->tbInfo.rv;
+ dciInfo->format.format0_0.tpcCmd = 0; //Sphoorthi TODO: check
+ dciInfo->format.format0_0.sUlCfgd = FALSE; /* SUL not configured */
+
+ /* Fill DCI Structure */
+ dciInfo->dciInfo.rnti = ueCb->crnti;
+ dciInfo->dciInfo.scramblingId = cellCb->cellCfg.phyCellId;
+ dciInfo->dciInfo.scramblingRnti = 0;
+ dciInfo->dciInfo.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
+ dciInfo->dciInfo.aggregLevel = 4;
+ dciInfo->dciInfo.beamPdcchInfo.numPrgs = 1;
+ dciInfo->dciInfo.beamPdcchInfo.prgSize = 1;
+ dciInfo->dciInfo.beamPdcchInfo.digBfInterfaces = 0;
+ dciInfo->dciInfo.beamPdcchInfo.prg[0].pmIdx = 0;
+ dciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0] = 0;
+ dciInfo->dciInfo.txPdcchPower.powerValue = 0;
+ dciInfo->dciInfo.txPdcchPower.powerControlOffsetSS = 0;
+ dciInfo->dciInfo.pdschCfg = NULL; /* No DL data being sent */
+
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief Function to Modify Ue Config request from MAC
+ *
+ * @details
+ *
+ * Function : MacSchModUeConfigReq
+ *
+ * Functionality: Function to modify Ue Config request from MAC
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t MacSchModUeConfigReq(Pst *pst, SchUeCfg *ueCfg)
+{
+ uint8_t ueId, lcIdx, ret = ROK;
+ SchCellCb *cellCb = NULLP;
+ SchUeCb *ueCb = NULLP;
+ SchUeCfgRsp cfgRsp;
+ Inst inst = pst->dstInst - SCH_INST_START;
+ memset(&cfgRsp, 0, sizeof(SchUeCfgRsp));
+
+#ifdef CALL_FLOW_DEBUG_LOG
+ DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_MODIFY_UE_CONFIG_REQ_TO_SCH\n");
+#endif
+
+ if(!ueCfg)
+ {
+ DU_LOG("\nERROR --> SCH : Modifying Ue Config request failed at MacSchModUeConfigReq()");
+ return RFAILED;
+ }
+ DU_LOG("\nDEBUG --> SCH : Modifying Ue Config Request for CRNTI[%d]", ueCfg->crnti);
+ cellCb = getSchCellCb(pst->event, inst, ueCfg);
+