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[Epic-ID: ODUHIGH-406][Task-ID: ODUHIGH-423]Fix for incorrect access of schCb instance
[o-du/l2.git]
/
src
/
5gnrsch
/
sch_slot_ind.c
diff --git
a/src/5gnrsch/sch_slot_ind.c
b/src/5gnrsch/sch_slot_ind.c
index
29a9480
..
b0a5bbd
100644
(file)
--- a/
src/5gnrsch/sch_slot_ind.c
+++ b/
src/5gnrsch/sch_slot_ind.c
@@
-664,7
+664,7
@@
uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst schInst)
if(cell->raReq[ueId-1] != NULLP)
{
isRarPending = true;
if(cell->raReq[ueId-1] != NULLP)
{
isRarPending = true;
- isRarScheduled = schProcessRaReq(cell, *slotInd, ueId);
+ isRarScheduled = schProcessRaReq(
schInst,
cell, *slotInd, ueId);
}
/* If MSG4 is pending for this UE, schedule PDCCH,PDSCH to send MSG4 and
}
/* If MSG4 is pending for this UE, schedule PDCCH,PDSCH to send MSG4 and