+
+/*******************************************************************
+ *
+ * @brief Fills pdcch and pdsch info for msg4
+ *
+ * @details
+ *
+ * Function : schDlRsrcAllocMsg4
+ *
+ * Functionality:
+ * Fills pdcch and pdsch info for msg4
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t schDlRsrcAllocMsg4(Msg4Alloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
+{
+ uint8_t coreset0Idx = 0;
+ uint8_t numRbs = 0;
+ uint8_t firstSymbol = 0;
+ uint8_t numSymbols = 0;
+ uint8_t offset = 0;
+ uint8_t offsetPointA;
+ uint8_t FreqDomainResource[6] = {0};
+ uint16_t tbSize = 0;
+ uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
+ uint8_t mcs = 4; /* MCS fixed to 4 */
+ SchBwpDlCfg *initialBwp;
+
+ PdcchCfg *pdcch = &msg4Alloc->msg4PdcchCfg;
+ PdschCfg *pdsch = &msg4Alloc->msg4PdschCfg;
+ BwpCfg *bwp = &msg4Alloc->bwp;
+
+ initialBwp = &cell->cellCfg.schInitialDlBwp;
+ offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
+ coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
+
+ /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
+ numRbs = coresetIdxTable[coreset0Idx][1];
+ numSymbols = coresetIdxTable[coreset0Idx][2];
+ offset = coresetIdxTable[coreset0Idx][3];
+
+ /* calculate time domain parameters */
+ uint16_t mask = 0x2000;
+ for(firstSymbol=0; firstSymbol<14;firstSymbol++)
+ {
+ if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
+ break;
+ else
+ mask = mask>>1;
+ }
+
+ /* calculate the PRBs */
+ schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
+
+ /* fill BWP */
+ bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
+ bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
+ bwp->subcarrierSpacing = initialBwp->bwp.scs;
+ bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
+
+ /* fill the PDCCH PDU */
+ pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
+ pdcch->coreset0Cfg.durationSymbols = numSymbols;
+ memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
+ pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
+ pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->coreset0Cfg.coreSetType = 0;
+ pdcch->coreset0Cfg.coreSet0Size = numRbs;
+ pdcch->coreset0Cfg.shiftIndex = cell->cellCfg.phyCellId;
+ pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
+ pdcch->numDlDci = 1;
+ pdcch->dci.rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
+ pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
+ pdcch->dci.scramblingRnti = 0;
+ pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
+ pdcch->dci.aggregLevel = 4;
+ pdcch->dci.beamPdcchInfo.numPrgs = 1;
+ pdcch->dci.beamPdcchInfo.prgSize = 1;
+ pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
+ pdcch->dci.txPdcchPower.powerValue = 0;
+ pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
+
+ /* fill the PDSCH PDU */
+ uint8_t cwCount = 0;
+ pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
+ pdsch->rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
+ pdsch->pduIndex = 0;
+ pdsch->numCodewords = 1;
+ for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
+ {
+ pdsch->codeword[cwCount].targetCodeRate = 308;
+ pdsch->codeword[cwCount].qamModOrder = 2;
+ pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
+ pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
+ pdsch->codeword[cwCount].rvIndex = 0;
+ /* 38.214: Table 5.1.3.2-1, divided by 8 to get the value in bytes */
+ /* TODO : Calculate tbSize based of DL CCCH msg size */
+ tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
+ pdsch->codeword[cwCount].tbSize = tbSize;
+ }
+ pdsch->dataScramblingId = cell->cellCfg.phyCellId;
+ pdsch->numLayers = 1;
+ pdsch->transmissionScheme = 0;
+ pdsch->refPoint = 0;
+ pdsch->dmrs.dlDmrsSymbPos = 2;
+ pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
+ pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
+ pdsch->dmrs.scid = 0;
+ pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
+ pdsch->dmrs.dmrsPorts = 0;
+ pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
+ pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
+ pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
+ pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
+ /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
+ pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
+ pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
+ pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
+ pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
+ pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
+ pdsch->beamPdschInfo.numPrgs = 1;
+ pdsch->beamPdschInfo.prgSize = 1;
+ pdsch->beamPdschInfo.digBfInterfaces = 0;
+ pdsch->beamPdschInfo.prg[0].pmIdx = 0;
+ pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
+ pdsch->txPdschPower.powerControlOffset = 0;
+ pdsch->txPdschPower.powerControlOffsetSS = 0;
+
+ pdcch->dci.pdschCfg = pdsch;
+ return ROK;
+}
+
+uint16_t schAllocPucchResource(SchCellCb *cell,uint16_t crnti, uint16_t slot)
+{
+ uint8_t k1 = 1; /* dl-DataToUL-ACK RRC parameter will received from DU-APP msg4-pucch config */
+ uint16_t pucchSlot = (slot + k1) % SCH_NUM_SLOTS;
+ SchUlSlotInfo *schUlSlotInfo = NULLP;
+
+ schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
+ memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
+
+ schUlSlotInfo->pucchPres = true;
+ schUlSlotInfo->schPucchInfo.rnti = crnti;
+
+ return ROK;
+}
+