+ initialUlBwp = &cell->cellCfg.ulCfgCommon.schInitialUlBwp;
+
+ /*As per Spec 38.213, Sec 9.2.1, StartPrb is determined by by DCI and PDCCH CCE location
+ * N_cce = Num of CCEs in COreset used for PDCCH
+ * n_cce = first index of CCE used for PDCCH
+ * val_pri = PUCCH resource indicator field in DCI format 1_0/1_1*/
+ /* derive pucchResourceSet from schCellCfg */
+ if(pdcchAllocInfo != NULLP)
+ {
+ for(cRSetIdx = 0; cRSetIdx < MAX_NUM_CRSET; cRSetIdx++ )
+ {
+ if(ueCb->pdcchInfo[cRSetIdx].cRSetRef->cRSetId == pdcchAllocInfo->cRSetId)
+ {
+ N_cce = ueCb->pdcchInfo[cRSetIdx].totalCceCount;
+ break;
+ }
+ }
+ n_cce = pdcchAllocInfo->cceIndex;
+ }
+ else
+ {
+ initialDlBwp = &cell->cellCfg.dlCfgCommon.schInitialDlBwp;
+ /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
+ N_cce = coresetIdxTable[initialDlBwp->pdcchCommon.commonSearchSpace.coresetId][1] * \
+ coresetIdxTable[initialDlBwp->pdcchCommon.commonSearchSpace.coresetId][2];
+ n_cce = 4;/*As per current Implementation, default value of cceIndex for CORESET0 is 4*/
+ }
+ val_pri = PUCCH_RES_IND;
+
+ /*Following calculation are derived from Spec 38.213, Sec 9.2.1*/
+ r_pucch = (floor((2 * n_cce)/N_cce)) + (2 * val_pri);
+
+ if((floor(r_pucch/8)) == 0)
+ {
+ startPrb = pucchResourceSet[pucchIdx][3] + (floor(r_pucch/pucchResourceSet[pucchIdx][4]));
+ }
+ else if((floor(r_pucch/8)) == 1)
+ {
+ startPrb = initialUlBwp->bwp.freqAlloc.numPrb - 1 - pucchResourceSet[pucchIdx][3] - \
+ (floor((r_pucch - 8)/pucchResourceSet[pucchIdx][4]));
+ }
+ else
+ {
+ DU_LOG("\nERROR --> SCH: Invalid value of r_pucch:%d (greater than 15) ", r_pucch);
+ memset(schPucchInfo, 0, sizeof(SchPucchInfo));
+ return ret;
+ }