+ SchUlSlotInfo *schUlSlotInfo = NULLP;
+
+ schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
+ memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
+
+ schUlSlotInfo->pucchPres = true;
+ schUlSlotInfo->schPucchInfo.rnti = crnti;
+
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief Fills pdcch and pdsch info for dedicated DL msg
+ *
+ * @details
+ *
+ * Function : schDlRsrcAllocDlMsg
+ *
+ * Functionality:
+ * Fills pdcch and pdsch info for dl msg
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
+ uint16_t accumalatedSize, uint16_t slot)
+{
+ uint8_t ueIdx;
+ uint16_t tbSize = 0;
+ uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
+ uint8_t mcs = 4; /* MCS fixed to 4 */
+ PdcchCfg *pdcch = NULLP;
+ PdschCfg *pdsch = NULLP;
+ BwpCfg *bwp = NULLP;
+ SchUeCb ueCb;
+ SchControlRsrcSet coreset1;
+ SchPdschConfig pdschCfg;
+
+ pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
+ pdsch = &dlMsgAlloc->dlMsgPdschCfg;
+ bwp = &dlMsgAlloc->bwp;
+
+ GET_UE_IDX(crnti, ueIdx);
+ ueCb = cell->ueCb[ueIdx-1];
+ coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
+ pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
+
+ /* fill BWP */
+ bwp->freqAlloc.numPrb = MAX_NUM_RB;
+ bwp->freqAlloc.startPrb = 0;
+ bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
+ bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
+
+ /* fill the PDCCH PDU */
+ //Considering coreset1 also starts from same symbol as coreset0
+ pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
+ pdcch->coresetCfg.durationSymbols = coreset1.duration;
+ memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
+ pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
+ pdcch->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
+ pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
+ pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
+ //Considering number of RBs in coreset1 is same as coreset0
+ pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
+ pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
+ pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
+ pdcch->numDlDci = 1;
+ pdcch->dci.rnti = ueCb.crnti;
+ pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
+ pdcch->dci.scramblingRnti = 0;
+ pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
+ pdcch->dci.aggregLevel = 4;
+ pdcch->dci.beamPdcchInfo.numPrgs = 1;
+ pdcch->dci.beamPdcchInfo.prgSize = 1;
+ pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
+ pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
+ pdcch->dci.txPdcchPower.powerValue = 0;
+ pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;