+
+/*******************************************************************
+ *
+ * @brief fills Dl DCI PDU for Paging required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillPageDlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU for Paging
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to dlPageAlloc
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc, MacCellCfg *macCellCfg)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes=0;
+ uint8_t bytePos=0;
+ uint8_t bitPos=0;
+
+ uint16_t coreset0Size = 0;
+ uint16_t rbStart = 0;
+ uint16_t rbLen = 0;
+ uint8_t shortMsgInd = 0;
+ uint8_t shortMsg = 0;
+ uint32_t freqDomResAssign = 0;
+ uint32_t timeDomResAssign = 0;
+ uint8_t VRB2PRBMap = 0;
+ uint32_t modNCodScheme = 0;
+ uint8_t tbScaling = 0;
+ uint32_t reserved = 0;
+
+ /* Size(in bits) of each field in DCI format 1_0
+ * as mentioned in spec 38.214 */
+ uint8_t shortMsgIndSize = 2;
+ uint8_t shortMsgSize = 8;
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t tbScalingSize = 2;
+ uint8_t reservedSize = 6;
+
+ dlDciPtr[0].rnti = P_RNTI;
+ dlDciPtr[0].scramblingId = macCellCfg->cellCfg.phyCellId;
+ dlDciPtr[0].scramblingRnti = 0;
+ dlDciPtr[0].cceIndex = dlPageAlloc->pageDlDci.cceIndex;
+ dlDciPtr[0].aggregationLevel = dlPageAlloc->pageDlDci.aggregLevel;
+ dlDciPtr[0].pc_and_bform.numPrgs = 1;
+ dlDciPtr[0].pc_and_bform.prgSize = 1;
+ dlDciPtr[0].pc_and_bform.digBfInterfaces = 0;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].pmIdx = 0;
+ dlDciPtr[0].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = 0;
+ dlDciPtr[0].beta_pdcch_1_0 = 0;
+ dlDciPtr[0].powerControlOffsetSS = 0;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ coreset0Size = dlPageAlloc->pageDlDci.coreSetSize;
+ rbStart = dlPageAlloc->pageDlSch.freqAlloc.startPrb;
+ rbLen = dlPageAlloc->pageDlSch.freqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /*Fetching DCI field values */
+
+ /*Refer:38.212 - Table 7.3.1.2.1-1: Short Message indicator >*/
+ if(dlPageAlloc->shortMsgInd != TRUE)
+ {
+ /*When Short Msg is absent*/
+ shortMsgInd = 1;
+ shortMsg = 0;
+ }
+ else
+ {
+ /*Short Msg is Present*/
+ if(dlPageAlloc->pageDlSch.dlPagePduLen == 0 || dlPageAlloc->pageDlSch.dlPagePdu == NULLP)
+ {
+ /*When Paging Msg is absent*/
+ shortMsgInd = 2;
+ }
+ else
+ {
+ /*Both Short and Paging is present*/
+ shortMsgInd = 3;
+ }
+ shortMsg = dlPageAlloc->shortMsg;
+ }
+
+ timeDomResAssign = 0;
+ VRB2PRBMap = dlPageAlloc->pageDlSch.vrbPrbMapping;
+ modNCodScheme = dlPageAlloc->pageDlSch.tbInfo.mcs;
+ tbScaling = 0;
+ reserved = 0;
+
+ /* Reversing bits in each DCI field */
+ shortMsgInd = reverseBits(shortMsgInd, shortMsgIndSize);
+ shortMsg = reverseBits(shortMsg, shortMsgSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ tbScaling = reverseBits(tbScaling, tbScalingSize);
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr[0].payloadSizeBits = shortMsgIndSize + shortMsgSize + freqDomResAssignSize\
+ + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
+ + tbScaling + reservedSize;
+
+ numBytes = dlDciPtr[0].payloadSizeBits / 8;
+ if(dlDciPtr[0].payloadSizeBits % 8)
+ {
+ numBytes += 1;
+ }
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ {
+ dlDciPtr[0].payload[bytePos] = 0;
+ }
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ shortMsgInd, shortMsgIndSize);
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ shortMsg, shortMsgSize);
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ tbScaling, tbScalingSize);
+ fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\
+ reserved, reservedSize);
+ }
+} /* fillPageDlDciPdu */
+