+ cellId = (uint16_t *)msg;
+ GET_CELL_IDX(*cellId, cellIdx);
+ macCfgParams = macCb.macCell[cellIdx]->macCellCfg;
+
+ /* Fill Cell Configuration in lwrMacCb */
+ memset(&lwrMacCb.cellCb[lwrMacCb.numCell], 0, sizeof(LwrMacCellCb));
+ lwrMacCb.cellCb[lwrMacCb.numCell].cellId = macCfgParams.cellId;
+ lwrMacCb.cellCb[lwrMacCb.numCell].phyCellId = macCfgParams.cellCfg.phyCellId;
+ lwrMacCb.numCell++;
+
+ /* Allocte And fill Vendor msg */
+ LWR_MAC_ALLOC(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ if(!vendorMsgQElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(vendorMsgQElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
+ vendorMsg = (fapi_vendor_msg_t *)(vendorMsgQElem + 1);
+ fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
+ vendorMsg->config_req_vendor.hopping_id = 0;
+ vendorMsg->config_req_vendor.carrier_aggregation_level = 0;
+ vendorMsg->config_req_vendor.group_hop_flag = 0;
+ vendorMsg->config_req_vendor.sequence_hop_flag = 0;
+ vendorMsg->config_req_vendor.urllc_capable = 0;
+ vendorMsg->config_req_vendor.urllc_mini_slot_mask =0;
+ vendorMsg->config_req_vendor.nr_of_dl_ports =1;
+ vendorMsg->config_req_vendor.nr_of_ul_ports =1;
+ vendorMsg->config_req_vendor.prach_nr_of_rx_ru =1;
+ vendorMsg->config_req_vendor.ssb_subc_spacing =1;
+ vendorMsg->config_req_vendor.use_vendor_EpreXSSB = USE_VENDOR_EPREXSSB;
+ vendorMsg->start_req_vendor.sfn = 0;
+ vendorMsg->start_req_vendor.slot = 0;
+ vendorMsg->start_req_vendor.mode = 4;
+#ifdef DEBUG_MODE
+ vendorMsg->start_req_vendor.count = 0;
+ vendorMsg->start_req_vendor.period = 1;
+#endif
+ /* Fill FAPI config req */
+ LWR_MAC_ALLOC(cfgReqQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_config_req_t)));
+ if(!cfgReqQElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for config req");
+ LWR_MAC_FREE(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(cfgReqQElem, vendorMsgQElem, FAPI_CONFIG_REQUEST, 1, \
+ sizeof(fapi_config_req_t));
+
+ configReq = (fapi_config_req_t *)(cfgReqQElem + 1);
+ memset(configReq, 0, sizeof(fapi_config_req_t));
+ fillMsgHeader(&configReq->header, FAPI_CONFIG_REQUEST, sizeof(fapi_config_req_t));
+#ifndef NR_TDD
+ configReq->number_of_tlvs = 25;
+#else
+ configReq->number_of_tlvs = 25 + 1 + MAX_TDD_PERIODICITY_SLOTS * MAX_SYMB_PER_SLOT;
+#endif
+
+ msgLen = sizeof(configReq->number_of_tlvs);
+
+ fillTlvs(&configReq->tlvs[index++], FAPI_DL_BANDWIDTH_TAG, \
+ sizeof(uint32_t), macCfgParams.carrCfg.dlBw, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_DL_FREQUENCY_TAG, \
+ sizeof(uint32_t), macCfgParams.carrCfg.dlFreq, &msgLen);
+ /* Due to bug in Intel FT code, commenting TLVs that are are not
+ * needed to avoid error. Must be uncommented when FT bug is fixed */
+ //fillTlvs(&configReq->tlvs[index++], FAPI_DL_K0_TAG, \
+ sizeof(uint16_t), macCfgParams.dlCarrCfg.k0[0], &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_DL_GRIDSIZE_TAG, \
+ sizeof(uint16_t), macCfgParams.dlCarrCfg.gridSize[0], &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_NUM_TX_ANT_TAG, \
+ sizeof(uint16_t), macCfgParams.carrCfg.numTxAnt, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_UPLINK_BANDWIDTH_TAG, \
+ sizeof(uint32_t), macCfgParams.carrCfg.ulBw, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_UPLINK_FREQUENCY_TAG, \
+ sizeof(uint32_t), macCfgParams.carrCfg.ulFreq, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_UL_K0_TAG, \
+ sizeof(uint16_t), macCfgParams.ulCarrCfg.k0[0], &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_UL_GRID_SIZE_TAG, \
+ sizeof(uint16_t), macCfgParams.ulCarrCfg.gridSize[0], &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_NUM_RX_ANT_TAG, \
+ sizeof(uint16_t), macCfgParams.carrCfg.numRxAnt, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_FREQUENCY_SHIFT_7P5_KHZ_TAG, \
+ sizeof(uint8_t), macCfgParams.freqShft, &msgLen);
+
+ /* fill cell config */
+ fillTlvs(&configReq->tlvs[index++], FAPI_PHY_CELL_ID_TAG, \
+ sizeof(uint8_t), macCfgParams.cellCfg.phyCellId, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_FRAME_DUPLEX_TYPE_TAG, \
+ sizeof(uint8_t), macCfgParams.cellCfg.dupType, &msgLen);
+
+ /* fill SSB configuration */
+ fillTlvs(&configReq->tlvs[index++], FAPI_SS_PBCH_POWER_TAG, \
+ sizeof(uint32_t), macCfgParams.ssbCfg.ssbPbchPwr, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_BCH_PAYLOAD_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.bchPayloadFlag, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_SCS_COMMON_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.scsCmn, &msgLen);
+
+ /* fill PRACH configuration */
+ //fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_SEQUENCE_LENGTH_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.prachSeqLen, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_SUBC_SPACING_TAG, \
+ sizeof(uint8_t), convertScsValToScsEnum(macCfgParams.prachCfg.prachSubcSpacing), &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_RESTRICTED_SET_CONFIG_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.prachRstSetCfg, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_NUM_PRACH_FD_OCCASIONS_TAG,
+ sizeof(uint8_t), macCfgParams.prachCfg.msg1Fdm, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_CONFIG_INDEX_TAG,
+ sizeof(uint8_t), macCfgParams.prachCfg.prachCfgIdx, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ROOT_SEQUENCE_INDEX_TAG, \
+ sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].rootSeqIdx, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_NUM_ROOT_SEQUENCES_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numRootSeq, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_K1_TAG, \
+ sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].k1, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ZERO_CORR_CONF_TAG , \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].zeroCorrZoneCfg, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_NUM_UNUSED_ROOT_SEQUENCES_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numUnusedRootSeq, &msgLen);
+ /* if(macCfgParams.prachCfg.fdm[0].numUnusedRootSeq)
+ {
+ for(idx = 0; idx < macCfgParams.prachCfg.fdm[0].numUnusedRootSeq; idx++)
+ fillTlvs(&configReq->tlvs[index++], FAPI_UNUSED_ROOT_SEQUENCES_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].unsuedRootSeq[idx], \
+ &msgLen);
+ }
+ else
+ {
+ macCfgParams.prachCfg.fdm[0].unsuedRootSeq = NULL;
+ }*/
+
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_PER_RACH_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.ssbPerRach, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_MULTIPLE_CARRIERS_IN_A_BAND_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.prachMultCarrBand, &msgLen);
+
+ /* fill SSB table */
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_OFFSET_POINT_A_TAG, \
+ sizeof(uint16_t), macCfgParams.ssbCfg.ssbOffsetPointA, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_BETA_PSS_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.betaPss, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_PERIOD_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.ssbPeriod, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_SUBCARRIER_OFFSET_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.ssbScOffset, &msgLen);
+
+ setMibPdu(macCfgParams.ssbCfg.mibPdu, &mib, 0);
+ fillTlvs(&configReq->tlvs[index++], FAPI_MIB_TAG , \
+ sizeof(uint32_t), mib, &msgLen);
+
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_MASK_TAG, \
+ sizeof(uint32_t), macCfgParams.ssbCfg.ssbMask[0], &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_BEAM_ID_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.beamId[0], &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_SS_PBCH_MULTIPLE_CARRIERS_IN_A_BAND_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.multCarrBand, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_MULTIPLE_CELLS_SS_PBCH_IN_A_CARRIER_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.multCellCarr, &msgLen);
+
+#ifdef NR_TDD
+ /* fill TDD table */
+ fillTlvs(&configReq->tlvs[index++], FAPI_TDD_PERIOD_TAG, \
+ sizeof(uint8_t), macCfgParams.tddCfg.tddPeriod, &msgLen);
+
+ for(slotIdx =0 ;slotIdx < MAX_TDD_PERIODICITY_SLOTS; slotIdx++)
+ {
+ for(symbolIdx = 0; symbolIdx < MAX_SYMB_PER_SLOT; symbolIdx++)
+ {
+ /*Fill Full-DL Slots as well as DL symbols ini 1st Flexi Slo*/
+ if(slotIdx < macCfgParams.tddCfg.nrOfDlSlots || \
+ (slotIdx == macCfgParams.tddCfg.nrOfDlSlots && symbolIdx < macCfgParams.tddCfg.nrOfDlSymbols))
+ {
+ fillTlvs(&configReq->tlvs[index++], FAPI_SLOT_CONFIG_TAG, \
+ sizeof(uint8_t), DL_SYMBOL, &msgLen);
+ }
+
+ /*Fill Full-FLEXI SLOT and as well as Flexi Symbols in 1 slot preceding FULL-UL slot*/
+ else if(slotIdx < (MAX_TDD_PERIODICITY_SLOTS - macCfgParams.tddCfg.nrOfUlSlots -1) || \
+ (slotIdx == (MAX_TDD_PERIODICITY_SLOTS - macCfgParams.tddCfg.nrOfUlSlots -1) && \
+ symbolIdx < (MAX_SYMB_PER_SLOT - macCfgParams.tddCfg.nrOfUlSymbols)))
+ {
+ fillTlvs(&configReq->tlvs[index++], FAPI_SLOT_CONFIG_TAG, \
+ sizeof(uint8_t), FLEXI_SYMBOL, &msgLen);
+ }
+ /*Fill Partial UL symbols and Full-UL slot*/
+ else
+ {
+ fillTlvs(&configReq->tlvs[index++], FAPI_SLOT_CONFIG_TAG, \
+ sizeof(uint8_t), UL_SYMBOL, &msgLen);
+ }
+ }
+ }
+#endif
+
+ /* fill measurement config */
+ //fillTlvs(&configReq->tlvs[index++], FAPI_RSSI_MEASUREMENT_TAG, \
+ sizeof(uint8_t), macCfgParams.rssiUnit, &msgLen);
+
+ /* fill DMRS Type A Pos */
+ fillTlvs(&configReq->tlvs[index++], FAPI_DMRS_TYPE_A_POS_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.dmrsTypeAPos, &msgLen);
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
+ LWR_MAC_FREE(cfgReqQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_config_req_t)));
+ LWR_MAC_FREE(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, cfgReqQElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 2; /* Config req msg and vendor specific msg */
+ msgHeader->handle = 0;
+
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending Config Request to Phy");
+ LwrMacSendToL1(headerElem);
+#endif
+
+ return ROK;
+} /* lwr_mac_handleConfigReqEvt */
+
+/*******************************************************************
+ *
+ * @brief Processes config response from phy
+ *
+ * @details
+ *
+ * Function : lwr_mac_procConfigRspEvt
+ *
+ * Functionality:
+ * Processes config response from phy
+ *
+ * @params[in] FAPI message pointer
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+
+uint8_t lwr_mac_procConfigRspEvt(void *msg)
+{
+#ifdef INTEL_FAPI
+ fapi_config_resp_t *configRsp;
+ configRsp = (fapi_config_resp_t *)msg;
+
+ DU_LOG("\nINFO --> LWR_MAC: Received EVENT[%d] at STATE[%d]", lwrMacCb.event, \
+ lwrMacCb.phyState);
+
+ if(configRsp != NULL)
+ {
+ if(configRsp->error_code == MSG_OK)
+ {
+ DU_LOG("\nDEBUG --> LWR_MAC: PHY has moved to Configured state \n");
+ lwrMacCb.phyState = PHY_STATE_CONFIGURED;
+ lwrMacCb.cellCb[0].state = PHY_STATE_CONFIGURED;
+ /* TODO :
+ * Store config response into an intermediate struture and send to MAC
+ * Support LC and LWLC for sending config rsp to MAC
+ */
+ fapiMacConfigRsp(lwrMacCb.cellCb[0].cellId);
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Invalid error code %d", configRsp->error_code);
+ return RFAILED;
+ }
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Config Response received from PHY is NULL");
+ return RFAILED;
+ }
+#endif
+
+ return ROK;
+} /* lwr_mac_procConfigRspEvt */
+
+/*******************************************************************
+ *
+ * @brief Build and send start request to phy
+ *
+ * @details
+ *
+ * Function : lwr_mac_procStartReqEvt
+ *
+ * Functionality:
+ * Build and send start request to phy
+ *
+ * @params[in] FAPI message pointer
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t lwr_mac_procStartReqEvt(void *msg)
+{
+#ifdef INTEL_FAPI
+#ifdef CALL_FLOW_DEBUG_LOG
+ DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : START_REQ\n");
+#endif
+ fapi_msg_header_t *msgHeader;
+ fapi_start_req_t *startReq;
+ fapi_vendor_msg_t *vendorMsg;
+ p_fapi_api_queue_elem_t headerElem;
+ p_fapi_api_queue_elem_t startReqElem;
+ p_fapi_api_queue_elem_t vendorMsgElem;
+
+ /* Allocte And fill Vendor msg */
+ LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ if(!vendorMsgElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in start req");
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(vendorMsgElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
+ vendorMsg = (fapi_vendor_msg_t *)(vendorMsgElem + 1);
+ fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
+ vendorMsg->start_req_vendor.sfn = 0;
+ vendorMsg->start_req_vendor.slot = 0;
+ vendorMsg->start_req_vendor.mode = 4; /* for Radio mode */
+#ifdef DEBUG_MODE
+ vendorMsg->start_req_vendor.count = 0;
+ vendorMsg->start_req_vendor.period = 1;
+#endif
+
+ /* Fill FAPI config req */
+ LWR_MAC_ALLOC(startReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_start_req_t)));
+ if(!startReqElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for start req");
+ LWR_MAC_FREE(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(startReqElem, vendorMsgElem, FAPI_START_REQUEST, 1, \
+ sizeof(fapi_start_req_t));
+
+ startReq = (fapi_start_req_t *)(startReqElem + 1);
+ memset(startReq, 0, sizeof(fapi_start_req_t));
+ fillMsgHeader(&startReq->header, FAPI_START_REQUEST, sizeof(fapi_start_req_t));
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
+ LWR_MAC_FREE(startReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_start_req_t)));
+ LWR_MAC_FREE(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, startReqElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 2; /* Start req msg and vendor specific msg */
+ msgHeader->handle = 0;
+
+ /* Send to PHY */
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending Start Request to Phy");
+ LwrMacSendToL1(headerElem);
+#endif
+ return ROK;
+} /* lwr_mac_procStartReqEvt */
+
+/*******************************************************************
+ *
+ * @brief Sends FAPI Stop Req to PHY
+ *
+ * @details
+ *
+ * Function : lwr_mac_procStopReqEvt
+ *
+ * Functionality:
+ * -Sends FAPI Stop Req to PHY
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ ********************************************************************/
+
+uint8_t lwr_mac_procStopReqEvt(SlotTimingInfo slotInfo, p_fapi_api_queue_elem_t prevElem, fapi_stop_req_vendor_msg_t *vendorMsg)
+{
+#ifdef INTEL_FAPI
+#ifdef CALL_FLOW_DEBUG_LOG
+ DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : STOP_REQ\n");
+#endif
+
+ fapi_stop_req_t *stopReq;
+ p_fapi_api_queue_elem_t stopReqElem;
+
+ vendorMsg->sfn = slotInfo.sfn;
+ vendorMsg->slot = slotInfo.slot;
+
+ /* Fill FAPI stop req */
+ LWR_MAC_ALLOC(stopReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_stop_req_t)));
+ if(!stopReqElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for stop req");
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(stopReqElem, NULLP, FAPI_STOP_REQUEST, 1, sizeof(fapi_stop_req_t));
+ stopReq = (fapi_stop_req_t *)(stopReqElem + 1);
+ memset(stopReq, 0, sizeof(fapi_stop_req_t));
+ fillMsgHeader(&stopReq->header, FAPI_STOP_REQUEST, sizeof(fapi_stop_req_t));
+
+ /* Send to PHY */
+ DU_LOG("\nINFO --> LWR_MAC: Sending Stop Request to Phy");
+ prevElem->p_next = stopReqElem;
+
+#endif
+ return ROK;
+}
+
+#ifdef INTEL_FAPI
+/*******************************************************************
+ *
+ * @brief fills SSB PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillSsbPdu
+ *
+ * Functionality:
+ * -Fills the SSB PDU info
+ * stored in MAC
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to RgCellCb
+ * Pointer to msgLen of DL TTI Info
+ * @return ROK
+ *
+ ******************************************************************/
+
+uint8_t fillSsbPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, MacCellCfg *macCellCfg,
+ MacDlSlot *currDlSlot, uint8_t ssbIdxCount, uint16_t sfn)
+{
+ uint32_t mibPayload = 0;
+ if(dlTtiReqPdu != NULL)
+ {
+ dlTtiReqPdu->pduType = SSB_PDU_TYPE; /* SSB PDU */
+ dlTtiReqPdu->pdu.ssb_pdu.physCellId = macCellCfg->cellCfg.phyCellId;
+ dlTtiReqPdu->pdu.ssb_pdu.betaPss = macCellCfg->ssbCfg.betaPss;
+ dlTtiReqPdu->pdu.ssb_pdu.ssbBlockIndex = currDlSlot->dlInfo.brdcstAlloc.ssbInfo[ssbIdxCount].ssbIdx;
+ dlTtiReqPdu->pdu.ssb_pdu.ssbSubCarrierOffset = macCellCfg->ssbCfg.ssbScOffset;;
+ /* ssbOfPdufstA to be filled in ssbCfg */
+ dlTtiReqPdu->pdu.ssb_pdu.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;;
+ dlTtiReqPdu->pdu.ssb_pdu.bchPayloadFlag = macCellCfg->ssbCfg.bchPayloadFlag;
+ /* Bit manipulation for SFN */
+ setMibPdu(macCellCfg->ssbCfg.mibPdu, &mibPayload, sfn);
+ dlTtiReqPdu->pdu.ssb_pdu.bchPayload.bchPayload = mibPayload;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.numPrgs = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.prgSize = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.digBfInterfaces = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.pmi_bfi[0].pmIdx = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming. \
+ pmi_bfi[0].beamIdx[0].beamidx = macCellCfg->ssbCfg.beamId[0];
+ dlTtiReqPdu->pduSize = sizeof(fapi_dl_ssb_pdu_t); /* Size of SSB PDU */
+ return ROK;
+ }
+ return RFAILED;
+}
+
+/*******************************************************************
+ *
+ * @brief fills Dl DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillSib1DlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes=0;
+ uint8_t bytePos=0;
+ uint8_t bitPos=0;
+
+ uint16_t coreset0Size=0;
+ uint16_t rbStart=0;
+ uint16_t rbLen=0;
+ uint32_t freqDomResAssign=0;
+ uint32_t timeDomResAssign=0;
+ uint8_t VRB2PRBMap=0;
+ uint32_t modNCodScheme=0;
+ uint8_t redundancyVer=0;
+ uint32_t sysInfoInd=0;
+ uint32_t reserved=0;
+
+ /* Size(in bits) of each field in DCI format 0_1
+ * as mentioned in spec 38.214 */
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t redundancyVerSize = 2;
+ uint8_t sysInfoIndSize = 1;
+ uint8_t reservedSize = 15;
+
+ dlDciPtr->rnti = sib1PdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = sib1PdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = sib1PdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = sib1PdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = sib1PdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = sib1PdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = sib1PdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
+ dlDciPtr->powerControlOffsetSS = sib1PdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ coreset0Size= sib1PdcchInfo->coresetCfg.coreSetSize;
+ rbStart = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb;
+ rbLen = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ timeDomResAssign = sib1PdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex -1;
+ VRB2PRBMap = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = sib1PdcchInfo->dci.pdschCfg.codeword[0].mcsIndex;
+ redundancyVer = sib1PdcchInfo->dci.pdschCfg.codeword[0].rvIndex;
+ sysInfoInd = 0; /* 0 for SIB1; 1 for SI messages */
+ reserved = 0;
+
+ /* Reversing bits in each DCI field */
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
+ sysInfoInd = reverseBits(sysInfoInd, sysInfoIndSize);
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ + VRB2PRBMapSize + modNCodSchemeSize + redundancyVerSize\
+ + sysInfoIndSize + reservedSize;
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ sysInfoInd, sysInfoIndSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ reserved, reservedSize);
+
+ }
+} /* fillSib1DlDciPdu */
+
+
+/*******************************************************************
+ *
+ * @brief fills Dl DCI PDU for Paging required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillPageDlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU for Paging
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to dlPageAlloc
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc, MacCellCfg *macCellCfg)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes=0;
+ uint8_t bytePos=0;
+ uint8_t bitPos=0;
+
+ uint16_t coreset0Size = 0;
+ uint16_t rbStart = 0;
+ uint16_t rbLen = 0;
+ uint8_t shortMsgInd = 0;
+ uint8_t shortMsg = 0;
+ uint32_t freqDomResAssign = 0;
+ uint32_t timeDomResAssign = 0;
+ uint8_t VRB2PRBMap = 0;
+ uint32_t modNCodScheme = 0;
+ uint8_t tbScaling = 0;
+ uint32_t reserved = 0;
+
+ /* Size(in bits) of each field in DCI format 1_0
+ * as mentioned in spec 38.214 */
+ uint8_t shortMsgIndSize = 2;
+ uint8_t shortMsgSize = 8;
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t tbScalingSize = 2;
+ uint8_t reservedSize = 6;
+
+ dlDciPtr->rnti = P_RNTI;
+ dlDciPtr->scramblingId = macCellCfg->cellCfg.phyCellId;
+ dlDciPtr->scramblingRnti = 0;
+ dlDciPtr->cceIndex = dlPageAlloc->pageDlDci.cceIndex;
+ dlDciPtr->aggregationLevel = dlPageAlloc->pageDlDci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = 1;
+ dlDciPtr->pc_and_bform.prgSize = 1;
+ dlDciPtr->pc_and_bform.digBfInterfaces = 0;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = 0;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = 0;
+ dlDciPtr->beta_pdcch_1_0 = 0;
+ dlDciPtr->powerControlOffsetSS = 0;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ coreset0Size = dlPageAlloc->pageDlDci.coreSetSize;
+ rbStart = dlPageAlloc->pageDlSch.freqAlloc.startPrb;
+ rbLen = dlPageAlloc->pageDlSch.freqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /*Fetching DCI field values */
+
+ /*Refer:38.212 - Table 7.3.1.2.1-1: Short Message indicator >*/
+ if(dlPageAlloc->shortMsgInd != TRUE)
+ {
+ /*When Short Msg is absent*/
+ shortMsgInd = 1;
+ shortMsg = 0;
+ }
+ else
+ {
+ /*Short Msg is Present*/
+ if(dlPageAlloc->pageDlSch.dlPagePduLen == 0 || dlPageAlloc->pageDlSch.dlPagePdu == NULLP)
+ {
+ /*When Paging Msg is absent*/
+ shortMsgInd = 2;
+ }
+ else
+ {
+ /*Both Short and Paging is present*/
+ shortMsgInd = 3;
+ }
+ shortMsg = dlPageAlloc->shortMsg;
+ }
+
+ timeDomResAssign = 0;
+ VRB2PRBMap = dlPageAlloc->pageDlSch.vrbPrbMapping;
+ modNCodScheme = dlPageAlloc->pageDlSch.tbInfo.mcs;
+ tbScaling = 0;
+ reserved = 0;
+
+ /* Reversing bits in each DCI field */
+ shortMsgInd = reverseBits(shortMsgInd, shortMsgIndSize);
+ shortMsg = reverseBits(shortMsg, shortMsgSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ tbScaling = reverseBits(tbScaling, tbScalingSize);
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = shortMsgIndSize + shortMsgSize + freqDomResAssignSize\
+ + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
+ + tbScaling + reservedSize;
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ {
+ numBytes += 1;
+ }
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ {
+ dlDciPtr->payload[bytePos] = 0;
+ }
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ shortMsgInd, shortMsgIndSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ shortMsg, shortMsgSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ tbScaling, tbScalingSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ reserved, reservedSize);
+ }
+} /* fillPageDlDciPdu */
+
+/*******************************************************************
+ *
+ * @brief fills Dl DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillRarDlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes =0;
+ uint8_t bytePos =0;
+ uint8_t bitPos =0;
+
+ uint16_t coreset0Size =0;
+ uint16_t rbStart =0;
+ uint16_t rbLen =0;
+ uint32_t freqDomResAssign =0;
+ uint8_t timeDomResAssign =0;
+ uint8_t VRB2PRBMap =0;
+ uint8_t modNCodScheme =0;
+ uint8_t tbScaling =0;
+ uint32_t reserved =0;
+
+ /* Size(in bits) of each field in DCI format 1_0 */
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t tbScalingSize = 2;
+ uint8_t reservedSize = 16;
+
+ dlDciPtr->rnti = rarPdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = rarPdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = rarPdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = rarPdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = rarPdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
+ dlDciPtr->powerControlOffsetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+
+ /* TODO: Fill values of coreset0Size, rbStart and rbLen */
+ coreset0Size= rarPdcchInfo->coresetCfg.coreSetSize;
+ rbStart = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb;
+ rbLen = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ timeDomResAssign = rarPdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex;
+ VRB2PRBMap = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = rarPdcchInfo->dci.pdschCfg.codeword[0].mcsIndex;
+ tbScaling = 0; /* configured to 0 scaling */
+ reserved = 0;
+
+ /* Reversing bits in each DCI field */
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ tbScaling = reverseBits(tbScaling, tbScalingSize);
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ + VRB2PRBMapSize + modNCodSchemeSize + tbScalingSize + reservedSize;
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ tbScaling, tbScalingSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ reserved, reservedSize);
+ }
+} /* fillRarDlDciPdu */
+
+/*******************************************************************
+ *
+ * @brief fills DL DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillDlMsgDlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\
+ DlMsgSchInfo *dlMsgSchInfo)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes;
+ uint8_t bytePos;
+ uint8_t bitPos;
+
+ uint16_t coresetSize = 0;
+ uint16_t rbStart = 0;
+ uint16_t rbLen = 0;
+ uint8_t dciFormatId;
+ uint32_t freqDomResAssign;
+ uint8_t timeDomResAssign;
+ uint8_t VRB2PRBMap;
+ uint8_t modNCodScheme;
+ uint8_t ndi = 0;
+ uint8_t redundancyVer = 0;
+ uint8_t harqProcessNum = 0;
+ uint8_t dlAssignmentIdx = 0;
+ uint8_t pucchTpc = 0;
+ uint8_t pucchResoInd = 0;
+ uint8_t harqFeedbackInd = 0;
+
+ /* Size(in bits) of each field in DCI format 1_0 */
+ uint8_t dciFormatIdSize = 1;
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t ndiSize = 1;
+ uint8_t redundancyVerSize = 2;
+ uint8_t harqProcessNumSize = 4;
+ uint8_t dlAssignmentIdxSize = 2;
+ uint8_t pucchTpcSize = 2;
+ uint8_t pucchResoIndSize = 3;
+ uint8_t harqFeedbackIndSize = 3;
+
+ dlDciPtr->rnti = pdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = pdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = pdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = pdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = pdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = pdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = pdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = pdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.beta_pdcch_1_0;
+ dlDciPtr->powerControlOffsetSS = pdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ coresetSize = pdcchInfo->coresetCfg.coreSetSize;
+ rbStart = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb;
+ rbLen = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coresetSize - rbStart))
+ {
+ if((rbLen - 1) <= floor(coresetSize / 2))
+ freqDomResAssign = (coresetSize * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coresetSize * (coresetSize - rbLen + 1)) \
+ + (coresetSize - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coresetSize * (coresetSize + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ dciFormatId = dlMsgSchInfo->dciFormatId; /* Always set to 1 for DL */
+ timeDomResAssign = pdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex -1;
+ VRB2PRBMap = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = pdcchInfo->dci.pdschCfg.codeword[0].mcsIndex;
+ ndi = dlMsgSchInfo->transportBlock[0].ndi;
+ redundancyVer = pdcchInfo->dci.pdschCfg.codeword[0].rvIndex;
+ harqProcessNum = dlMsgSchInfo->harqProcNum;
+ dlAssignmentIdx = dlMsgSchInfo->dlAssignIdx;
+ pucchTpc = dlMsgSchInfo->pucchTpc;
+ pucchResoInd = dlMsgSchInfo->pucchResInd;
+ harqFeedbackInd = dlMsgSchInfo->harqFeedbackInd;
+
+ /* Reversing bits in each DCI field */
+ dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ ndi = reverseBits(ndi, ndiSize);
+ redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
+ harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
+ dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize);
+ pucchTpc = reverseBits(pucchTpc, pucchTpcSize);
+ pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize);
+ harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize);
+
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
+ + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
+ + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\
+ + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize);
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ dciFormatId, dciFormatIdSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ ndi, ndiSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ harqProcessNum, harqProcessNumSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ dlAssignmentIdx, dlAssignmentIdxSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ pucchTpc, pucchTpcSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ pucchResoInd, pucchResoIndSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ harqFeedbackInd, harqFeedbackIndSize);
+ }
+}
+
+/*******************************************************************
+ *
+ * @brief fills Dl PDCCH Info from DL PageAlloc
+ *
+ * @details
+ *
+ * Function : fillPdcchInfoFrmPageAlloc
+ *
+ * Functionality:
+ * -Fills the PdcchInfo
+ *
+ * @params[in] Pointer to DlPageAlloc
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+void fillPagePdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_pdu_t *dlTtiVendorPdu, DlPageAlloc *pageAlloc, MacCellCfg *macCellCfg)
+{
+ if(dlTtiReqPdu != NULLP)
+ {
+ BwpCfg *bwp = NULLP;
+
+ memset(&dlTtiReqPdu->pdu.pdcch_pdu, 0, sizeof(fapi_dl_pdcch_pdu_t));
+ bwp = &pageAlloc->bwp;
+ fillPageDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pageAlloc, macCellCfg);
+
+ dlTtiReqPdu->pduType = PDCCH_PDU_TYPE;
+
+ dlTtiReqPdu->pdu.pdcch_pdu.bwpSize = bwp->freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdcch_pdu.bwpStart = bwp->freqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdcch_pdu.subCarrierSpacing = bwp->subcarrierSpacing;
+ dlTtiReqPdu->pdu.pdcch_pdu.cyclicPrefix = bwp->cyclicPrefix;
+
+ dlTtiReqPdu->pdu.pdcch_pdu.startSymbolIndex = pageAlloc->pageDlDci.ssStartSymbolIndex;
+ dlTtiReqPdu->pdu.pdcch_pdu.durationSymbols = pageAlloc->pageDlDci.durationSymbols;
+ memcpy(dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource, pageAlloc->pageDlDci.freqDomainResource, 6*sizeof(uint8_t));
+ dlTtiReqPdu->pdu.pdcch_pdu.cceRegMappingType = pageAlloc->pageDlDci.cceRegMappingType;
+ dlTtiReqPdu->pdu.pdcch_pdu.regBundleSize = pageAlloc->pageDlDci.cceReg.interleaved.regBundleSize;
+ dlTtiReqPdu->pdu.pdcch_pdu.interleaverSize = pageAlloc->pageDlDci.cceReg.interleaved.interleaverSize;
+ dlTtiReqPdu->pdu.pdcch_pdu.shiftIndex = pageAlloc->pageDlDci.cceReg.interleaved.shiftIndex;
+ dlTtiReqPdu->pdu.pdcch_pdu.precoderGranularity = pageAlloc->pageDlDci.precoderGranularity;
+ dlTtiReqPdu->pdu.pdcch_pdu.numDlDci = 1;
+ dlTtiReqPdu->pdu.pdcch_pdu.coreSetType = CORESET_TYPE0;
+
+ /* Calculating PDU length. Considering only one dl dci pdu for now */
+ dlTtiReqPdu->pduSize = sizeof(fapi_dl_pdcch_pdu_t);
+
+ /* Filling Vendor message PDU */
+ dlTtiVendorPdu->pdu_type = FAPI_PDCCH_PDU_TYPE;
+ dlTtiVendorPdu->pdu_size = sizeof(fapi_vendor_dl_pdcch_pdu_t);
+ dlTtiVendorPdu->pdu.pdcch_pdu.num_dl_dci = dlTtiReqPdu->pdu.pdcch_pdu.numDlDci;
+ dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_pdcch_to_ssb = 0;
+ dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_dmrs_to_ssb = 0;
+ }
+}
+
+/*******************************************************************
+ *
+ * @brief fills PDCCH PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillPdcchPdu
+ *
+ * Functionality:
+ * -Fills the Pdcch PDU info
+ * stored in MAC
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_pdu_t *dlTtiVendorPdu, MacDlSlot *dlSlot, int8_t dlMsgSchInfoIdx, \
+ RntiType rntiType, uint8_t coreSetType, uint8_t ueIdx)
+{
+ if(dlTtiReqPdu != NULLP)
+ {
+ PdcchCfg *pdcchInfo = NULLP;
+ BwpCfg *bwp = NULLP;
+
+ memset(&dlTtiReqPdu->pdu.pdcch_pdu, 0, sizeof(fapi_dl_pdcch_pdu_t));
+ if(rntiType == SI_RNTI_TYPE)
+ {
+ pdcchInfo = dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg;
+ bwp = &dlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp;
+ fillSib1DlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo);
+ }
+ else if(rntiType == RA_RNTI_TYPE)
+ {
+ pdcchInfo = dlSlot->dlInfo.rarAlloc[ueIdx]->rarPdcchCfg;
+ bwp = &dlSlot->dlInfo.rarAlloc[ueIdx]->bwp;
+ fillRarDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo);
+ }
+ else if(rntiType == TC_RNTI_TYPE || rntiType == C_RNTI_TYPE)
+ {
+ pdcchInfo = dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgPdcchCfg;
+ bwp = &dlSlot->dlInfo.dlMsgAlloc[ueIdx]->bwp;
+ fillDlMsgDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo,\
+ dlSlot->dlInfo.dlMsgAlloc[ueIdx]);
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Failed filling PDCCH Pdu");
+ return RFAILED;
+ }
+
+ dlTtiReqPdu->pduType = PDCCH_PDU_TYPE;
+ dlTtiReqPdu->pdu.pdcch_pdu.bwpSize = bwp->freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdcch_pdu.bwpStart = bwp->freqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdcch_pdu.subCarrierSpacing = bwp->subcarrierSpacing;
+ dlTtiReqPdu->pdu.pdcch_pdu.cyclicPrefix = bwp->cyclicPrefix;
+
+ dlTtiReqPdu->pdu.pdcch_pdu.startSymbolIndex = pdcchInfo->coresetCfg.startSymbolIndex;
+ dlTtiReqPdu->pdu.pdcch_pdu.durationSymbols = pdcchInfo->coresetCfg.durationSymbols;
+ memcpy(dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource, pdcchInfo->coresetCfg.freqDomainResource, 6);
+ dlTtiReqPdu->pdu.pdcch_pdu.cceRegMappingType = pdcchInfo->coresetCfg.cceRegMappingType;
+ dlTtiReqPdu->pdu.pdcch_pdu.regBundleSize = pdcchInfo->coresetCfg.regBundleSize;
+ dlTtiReqPdu->pdu.pdcch_pdu.interleaverSize = pdcchInfo->coresetCfg.interleaverSize;
+ dlTtiReqPdu->pdu.pdcch_pdu.shiftIndex = pdcchInfo->coresetCfg.shiftIndex;
+ dlTtiReqPdu->pdu.pdcch_pdu.precoderGranularity = pdcchInfo->coresetCfg.precoderGranularity;
+ dlTtiReqPdu->pdu.pdcch_pdu.numDlDci = pdcchInfo->numDlDci;
+ dlTtiReqPdu->pdu.pdcch_pdu.coreSetType = coreSetType;
+
+ /* Calculating PDU length. Considering only one dl dci pdu for now */
+ dlTtiReqPdu->pduSize = sizeof(fapi_dl_pdcch_pdu_t);
+
+ /* Filling Vendor message PDU */
+ dlTtiVendorPdu->pdu_type = FAPI_PDCCH_PDU_TYPE;
+ dlTtiVendorPdu->pdu_size = sizeof(fapi_vendor_dl_pdcch_pdu_t);
+ dlTtiVendorPdu->pdu.pdcch_pdu.num_dl_dci = dlTtiReqPdu->pdu.pdcch_pdu.numDlDci;
+ dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_pdcch_to_ssb = 0;
+ dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_dmrs_to_ssb = 0;
+ }
+
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief fills PDSCH PDU from PageAlloc required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillPagePdschPdu
+ *
+ * Functionality:
+ * -Fills the Pdsch PDU info
+ * stored in MAC
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to PdschCfg
+ * Pointer to msgLen of DL TTI Info
+ * @return ROK
+ *
+ ******************************************************************/
+void fillPagePdschPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_pdu_t *dlTtiVendorPdu, DlPageAlloc *pageAlloc,
+ uint16_t pduIndex, MacCellCfg *macCellCfg)
+{
+ uint8_t idx;
+
+ if(dlTtiReqPdu != NULLP)
+ {
+ dlTtiReqPdu->pduType = PDSCH_PDU_TYPE;
+ memset(&dlTtiReqPdu->pdu.pdsch_pdu, 0, sizeof(fapi_dl_pdsch_pdu_t));
+ dlTtiReqPdu->pdu.pdsch_pdu.pduBitMap = 0; /* PTRS and CBG params are excluded */
+ dlTtiReqPdu->pdu.pdsch_pdu.rnti = P_RNTI;
+ dlTtiReqPdu->pdu.pdsch_pdu.pdu_index = pduIndex;
+ dlTtiReqPdu->pdu.pdsch_pdu.bwpSize = pageAlloc->bwp.freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.bwpStart = pageAlloc->bwp.freqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.subCarrierSpacing = pageAlloc->bwp.subcarrierSpacing;
+ dlTtiReqPdu->pdu.pdsch_pdu.cyclicPrefix = pageAlloc->bwp.cyclicPrefix;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfCodeWords = 1;
+ for(idx = 0; idx < MAX_CODEWORDS ; idx++)
+ {
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].targetCodeRate = 308;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].qamModOrder = 2;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].mcsIndex = pageAlloc->pageDlSch.tbInfo.mcs;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].mcsTable = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].rvIndex = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].tbSize = pageAlloc->pageDlSch.tbInfo.tbSize;
+ }
+ dlTtiReqPdu->pdu.pdsch_pdu.dataScramblingId = macCellCfg->cellCfg.phyCellId;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfLayers = 1;
+ dlTtiReqPdu->pdu.pdsch_pdu.transmissionScheme = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.refPoint = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.dlDmrsSymbPos = DL_DMRS_SYMBOL_POS;
+ dlTtiReqPdu->pdu.pdsch_pdu.dmrsConfigType = pageAlloc->pageDlSch.dmrs.dmrsType;
+ dlTtiReqPdu->pdu.pdsch_pdu.dlDmrsScramblingId = macCellCfg->cellCfg.phyCellId;
+ dlTtiReqPdu->pdu.pdsch_pdu.scid = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.numDmrsCdmGrpsNoData = 1;
+ dlTtiReqPdu->pdu.pdsch_pdu.dmrsPorts = 0x0001;
+ dlTtiReqPdu->pdu.pdsch_pdu.resourceAlloc = 1;
+ /* since we are using type-1, hence rbBitmap excluded */
+ dlTtiReqPdu->pdu.pdsch_pdu.rbStart = pageAlloc->pageDlSch.freqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.rbSize = pageAlloc->pageDlSch.freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.vrbToPrbMapping = pageAlloc->pageDlSch.vrbPrbMapping;
+ dlTtiReqPdu->pdu.pdsch_pdu.startSymbIndex = pageAlloc->pageDlSch.timeAlloc.startSymb;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfSymbols = pageAlloc->pageDlSch.timeAlloc.numSymb;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.numPrgs = 1;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.prgSize = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.digBfInterfaces = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.pmi_bfi[0].pmIdx = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.pmi_bfi[0].beamIdx[0].beamidx = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.powerControlOffset = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.powerControlOffsetSS = 0;
+ dlTtiReqPdu->pdu.pdsch_pdu.mappingType = pageAlloc->pageDlSch.timeAlloc.mappingType;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfDmrsSymbols = pageAlloc->pageDlSch.dmrs.nrOfDmrsSymbols;
+ dlTtiReqPdu->pdu.pdsch_pdu.dmrsAddPos = pageAlloc->pageDlSch.dmrs.dmrsAddPos;
+
+ dlTtiReqPdu->pduSize = sizeof(fapi_dl_pdsch_pdu_t);
+
+ /* DL TTI Request vendor message */
+ dlTtiVendorPdu->pdu_type = FAPI_PDSCH_PDU_TYPE;
+ dlTtiVendorPdu->pdu_size = sizeof(fapi_vendor_dl_pdsch_pdu_t);
+ dlTtiVendorPdu->pdu.pdsch_pdu.nr_of_antenna_ports = 1;
+ for(int i =0; i< FAPI_VENDOR_MAX_TXRU_NUM; i++)
+ {
+ dlTtiVendorPdu->pdu.pdsch_pdu.tx_ru_idx[i] =0;
+ }
+ }
+}
+
+/*******************************************************************
+ *
+ * @brief fills PDSCH PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillPdschPdu
+ *
+ * Functionality:
+ * -Fills the Pdsch PDU info
+ * stored in MAC
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to PdschCfg
+ * Pointer to msgLen of DL TTI Info
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillPdschPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_pdu_t *dlTtiVendorPdu, PdschCfg *pdschInfo,
+ BwpCfg bwp, uint16_t pduIndex)
+{
+ uint8_t idx;