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Cell and Network slicing configuration over o1.
[o-du/l2.git]
/
src
/
5gnrmac
/
lwr_mac_fsm.c
diff --git
a/src/5gnrmac/lwr_mac_fsm.c
b/src/5gnrmac/lwr_mac_fsm.c
index
a5c92b7
..
5f8e049
100644
(file)
--- a/
src/5gnrmac/lwr_mac_fsm.c
+++ b/
src/5gnrmac/lwr_mac_fsm.c
@@
-3463,7
+3463,6
@@
uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo)
pduIndex++;
numPduEncoded++;
}
pduIndex++;
numPduEncoded++;
}
-
DU_LOG("\033[1;34m");
DU_LOG("\nDEBUG --> LWR_MAC: SIB1 sent...");
DU_LOG("\033[0m");
DU_LOG("\033[1;34m");
DU_LOG("\nDEBUG --> LWR_MAC: SIB1 sent...");
DU_LOG("\033[0m");
@@
-3569,7
+3568,7
@@
uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo)
msgHeader->num_msg++;
/* Intel L1 expects UL_DCI.request following DL_TTI.request */
msgHeader->num_msg++;
/* Intel L1 expects UL_DCI.request following DL_TTI.request */
- fillUlDciReq(
curr
TimingInfo, dlTtiElem->p_next);
+ fillUlDciReq(
dlTtiReq
TimingInfo, dlTtiElem->p_next);
msgHeader->num_msg++;
/* send Tx-DATA req message */
msgHeader->num_msg++;
/* send Tx-DATA req message */
@@
-3593,7
+3592,7
@@
uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo)
msgHeader->num_msg++;
/* Intel L1 expects UL_DCI.request following DL_TTI.request */
msgHeader->num_msg++;
/* Intel L1 expects UL_DCI.request following DL_TTI.request */
- fillUlDciReq(
curr
TimingInfo, dlTtiElem->p_next);
+ fillUlDciReq(
dlTtiReq
TimingInfo, dlTtiElem->p_next);
msgHeader->num_msg++;
prevElem = dlTtiElem->p_next->p_next;
msgHeader->num_msg++;
prevElem = dlTtiElem->p_next->p_next;
@@
-3705,7
+3704,7
@@
uint16_t sendTxDataReq(SlotTimingInfo currTimingInfo, DlSchedInfo *dlInfo, p_fap
for(schInfoIdx=0; schInfoIdx < dlInfo->dlMsgAlloc[ueIdx]->numSchedInfo; schInfoIdx++)
{
if((dlInfo->dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].pduPres == BOTH) || \
for(schInfoIdx=0; schInfoIdx < dlInfo->dlMsgAlloc[ueIdx]->numSchedInfo; schInfoIdx++)
{
if((dlInfo->dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].pduPres == BOTH) || \
- (dlInfo->dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].pduPres == PDSCH_PDU))
+
(dlInfo->dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].pduPres == PDSCH_PDU))
{
fillDlMsgTxDataReq(txDataReq->pdu_desc, pduIndex, \
&dlInfo->dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].dlMsgInfo, \
{
fillDlMsgTxDataReq(txDataReq->pdu_desc, pduIndex, \
&dlInfo->dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].dlMsgInfo, \
@@
-4344,7
+4343,6
@@
uint16_t fillUlDciReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t pre
numPduEncoded++;
/* free UL GRANT at SCH */
MAC_FREE(currDlSlot->dlInfo.ulGrant, sizeof(DciInfo));
numPduEncoded++;
/* free UL GRANT at SCH */
MAC_FREE(currDlSlot->dlInfo.ulGrant, sizeof(DciInfo));
- currDlSlot->dlInfo.ulGrant = NULLP;
}
#ifdef ODU_SLOT_IND_DEBUG_LOG
DU_LOG("\nDEBUG --> LWR_MAC: Sending UL DCI Request");
}
#ifdef ODU_SLOT_IND_DEBUG_LOG
DU_LOG("\nDEBUG --> LWR_MAC: Sending UL DCI Request");