+ /* Fill Cell Configuration in lwrMacCb */
+ memset(&lwrMacCb.cellCb[lwrMacCb.numCell], 0, sizeof(LwrMacCellCb));
+ lwrMacCb.cellCb[lwrMacCb.numCell].cellId = macCfgParams.cellId;
+ lwrMacCb.cellCb[lwrMacCb.numCell].phyCellId = macCfgParams.phyCellId;
+ lwrMacCb.numCell++;
+
+ /* Allocte And fill Vendor msg */
+ LWR_MAC_ALLOC(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ if(!vendorMsgQElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(vendorMsgQElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
+ vendorMsg = (fapi_vendor_msg_t *)(vendorMsgQElem + 1);
+ fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
+ vendorMsg->config_req_vendor.hopping_id = 0;
+ vendorMsg->config_req_vendor.carrier_aggregation_level = 0;
+ vendorMsg->config_req_vendor.group_hop_flag = 0;
+ vendorMsg->config_req_vendor.sequence_hop_flag = 0;
+
+ /* Fill FAPI config req */
+ LWR_MAC_ALLOC(cfgReqQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_config_req_t)));
+ if(!cfgReqQElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for config req");
+ LWR_MAC_ALLOC(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(cfgReqQElem, vendorMsgQElem, FAPI_CONFIG_REQUEST, 1, \
+ sizeof(fapi_config_req_t));
+
+ configReq = (fapi_config_req_t *)(cfgReqQElem + 1);
+ memset(configReq, 0, sizeof(fapi_config_req_t));
+ fillMsgHeader(&configReq->header, FAPI_CONFIG_REQUEST, sizeof(fapi_config_req_t));
+ configReq->number_of_tlvs = 25;
+ msgLen = sizeof(configReq->number_of_tlvs);
+
+ if(macCfgParams.dlCarrCfg.pres)
+ {
+ fillTlvs(&configReq->tlvs[index++], FAPI_DL_BANDWIDTH_TAG, \
+ sizeof(uint32_t), macCfgParams.dlCarrCfg.bw, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_DL_FREQUENCY_TAG, \
+ sizeof(uint32_t), macCfgParams.dlCarrCfg.freq, &msgLen);
+ /* Due to bug in Intel FT code, commenting TLVs that are are not
+ * needed to avoid error. Must be uncommented when FT bug is fixed */
+ //fillTlvs(&configReq->tlvs[index++], FAPI_DL_K0_TAG, \
+ sizeof(uint16_t), macCfgParams.dlCarrCfg.k0[0], &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_DL_GRIDSIZE_TAG, \
+ sizeof(uint16_t), macCfgParams.dlCarrCfg.gridSize[0], &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_NUM_TX_ANT_TAG, \
+ sizeof(uint16_t), macCfgParams.dlCarrCfg.numAnt, &msgLen);
+ }
+ if(macCfgParams.ulCarrCfg.pres)
+ {
+ fillTlvs(&configReq->tlvs[index++], FAPI_UPLINK_BANDWIDTH_TAG, \
+ sizeof(uint32_t), macCfgParams.ulCarrCfg.bw, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_UPLINK_FREQUENCY_TAG, \
+ sizeof(uint32_t), macCfgParams.ulCarrCfg.freq, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_UL_K0_TAG, \
+ sizeof(uint16_t), macCfgParams.ulCarrCfg.k0[0], &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_UL_GRID_SIZE_TAG, \
+ sizeof(uint16_t), macCfgParams.ulCarrCfg.gridSize[0], &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_NUM_RX_ANT_TAG, \
+ sizeof(uint16_t), macCfgParams.ulCarrCfg.numAnt, &msgLen);
+ }
+ //fillTlvs(&configReq->tlvs[index++], FAPI_FREQUENCY_SHIFT_7P5_KHZ_TAG, \
+ sizeof(uint8_t), macCfgParams.freqShft, &msgLen);
+
+ /* fill cell config */
+ fillTlvs(&configReq->tlvs[index++], FAPI_PHY_CELL_ID_TAG, \
+ sizeof(uint8_t), macCfgParams.phyCellId, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_FRAME_DUPLEX_TYPE_TAG, \
+ sizeof(uint8_t), macCfgParams.dupType, &msgLen);
+
+ /* fill SSB configuration */
+ fillTlvs(&configReq->tlvs[index++], FAPI_SS_PBCH_POWER_TAG, \
+ sizeof(uint32_t), macCfgParams.ssbCfg.ssbPbchPwr, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_BCH_PAYLOAD_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.bchPayloadFlag, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_SCS_COMMON_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.scsCmn, &msgLen);
+
+ /* fill PRACH configuration */
+ //fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_SEQUENCE_LENGTH_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.prachSeqLen, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_SUBC_SPACING_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.prachSubcSpacing, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_RESTRICTED_SET_CONFIG_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.prachRstSetCfg, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_NUM_PRACH_FD_OCCASIONS_TAG,
+ sizeof(uint8_t), macCfgParams.prachCfg.msg1Fdm, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_CONFIG_INDEX_TAG,
+ sizeof(uint8_t), macCfgParams.prachCfg.prachCfgIdx, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ROOT_SEQUENCE_INDEX_TAG, \
+ sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].rootSeqIdx, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_NUM_ROOT_SEQUENCES_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numRootSeq, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_K1_TAG, \
+ sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].k1, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ZERO_CORR_CONF_TAG , \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].zeroCorrZoneCfg, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_NUM_UNUSED_ROOT_SEQUENCES_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numUnusedRootSeq, &msgLen);
+ /* if(macCfgParams.prachCfg.fdm[0].numUnusedRootSeq)
+ {
+ for(idx = 0; idx < macCfgParams.prachCfg.fdm[0].numUnusedRootSeq; idx++)
+ fillTlvs(&configReq->tlvs[index++], FAPI_UNUSED_ROOT_SEQUENCES_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].unsuedRootSeq[idx], \
+ &msgLen);
+ }
+ else
+ {
+ macCfgParams.prachCfg.fdm[0].unsuedRootSeq = NULL;
+ }*/
+
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_PER_RACH_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.ssbPerRach, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_MULTIPLE_CARRIERS_IN_A_BAND_TAG, \
+ sizeof(uint8_t), macCfgParams.prachCfg.prachMultCarrBand, &msgLen);
+
+ /* fill SSB table */
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_OFFSET_POINT_A_TAG, \
+ sizeof(uint16_t), macCfgParams.ssbCfg.ssbOffsetPointA, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_BETA_PSS_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.betaPss, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_PERIOD_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.ssbPeriod, &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_SUBCARRIER_OFFSET_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.ssbScOffset, &msgLen);
+
+ setMibPdu(macCfgParams.ssbCfg.mibPdu, &mib, 0);
+ fillTlvs(&configReq->tlvs[index++], FAPI_MIB_TAG , \
+ sizeof(uint32_t), mib, &msgLen);
+
+ fillTlvs(&configReq->tlvs[index++], FAPI_SSB_MASK_TAG, \
+ sizeof(uint32_t), macCfgParams.ssbCfg.ssbMask[0], &msgLen);
+ fillTlvs(&configReq->tlvs[index++], FAPI_BEAM_ID_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.beamId[0], &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_SS_PBCH_MULTIPLE_CARRIERS_IN_A_BAND_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.multCarrBand, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_MULTIPLE_CELLS_SS_PBCH_IN_A_CARRIER_TAG, \
+ sizeof(uint8_t), macCfgParams.ssbCfg.multCellCarr, &msgLen);
+
+ /* fill TDD table */
+ //fillTlvs(&configReq->tlvs[index++], FAPI_TDD_PERIOD_TAG, \
+ sizeof(uint8_t), macCfgParams.tddCfg.tddPeriod, &msgLen);
+ //fillTlvs(&configReq->tlvs[index++], FAPI_SLOT_CONFIG_TAG, \
+ sizeof(uint8_t), macCfgParams.tddCfg.slotCfg[0][0], &msgLen);
+
+ /* fill measurement config */
+ //fillTlvs(&configReq->tlvs[index++], FAPI_RSSI_MEASUREMENT_TAG, \
+ sizeof(uint8_t), macCfgParams.rssiUnit, &msgLen);
+
+ /* fill DMRS Type A Pos */
+ fillTlvs(&configReq->tlvs[index++], FAPI_DMRS_TYPE_A_POS_TAG, \
+ sizeof(uint8_t), macCfgParams.dmrsTypeAPos, &msgLen);
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
+ LWR_MAC_ALLOC(cfgReqQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_config_req_t)));
+ LWR_MAC_ALLOC(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, cfgReqQElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 2; /* Config req msg and vendor specific msg */
+ msgHeader->handle = 0;
+
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending Config Request to Phy");
+ LwrMacSendToL1(headerElem);
+#endif
+
+ return ROK;
+} /* lwr_mac_handleConfigReqEvt */
+
+/*******************************************************************
+ *
+ * @brief Processes config response from phy
+ *
+ * @details
+ *
+ * Function : lwr_mac_procConfigRspEvt
+ *
+ * Functionality:
+ * Processes config response from phy
+ *
+ * @params[in] FAPI message pointer
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+
+uint8_t lwr_mac_procConfigRspEvt(void *msg)
+{
+#ifdef INTEL_FAPI
+ fapi_config_resp_t *configRsp;
+ configRsp = (fapi_config_resp_t *)msg;
+
+ DU_LOG("\nINFO --> LWR_MAC: Received EVENT[%d] at STATE[%d]", lwrMacCb.event, \
+ lwrMacCb.phyState);
+
+ if(configRsp != NULL)
+ {
+ if(configRsp->error_code == MSG_OK)
+ {
+ DU_LOG("\nDEBUG --> LWR_MAC: PHY has moved to Configured state \n");
+ lwrMacCb.phyState = PHY_STATE_CONFIGURED;
+ lwrMacCb.cellCb[0].state = PHY_STATE_CONFIGURED;
+ /* TODO :
+ * Store config response into an intermediate struture and send to MAC
+ * Support LC and LWLC for sending config rsp to MAC
+ */
+ fapiMacConfigRsp(lwrMacCb.cellCb[0].cellId);
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Invalid error code %d", configRsp->error_code);
+ return RFAILED;
+ }
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Config Response received from PHY is NULL");
+ return RFAILED;
+ }
+#endif
+
+ return ROK;
+} /* lwr_mac_procConfigRspEvt */
+
+/*******************************************************************
+ *
+ * @brief Build and send start request to phy
+ *
+ * @details
+ *
+ * Function : lwr_mac_procStartReqEvt
+ *
+ * Functionality:
+ * Build and send start request to phy
+ *
+ * @params[in] FAPI message pointer
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint8_t lwr_mac_procStartReqEvt(void *msg)
+{
+#ifdef INTEL_FAPI
+ fapi_msg_header_t *msgHeader;
+ fapi_start_req_t *startReq;
+ fapi_vendor_msg_t *vendorMsg;
+ p_fapi_api_queue_elem_t headerElem;
+ p_fapi_api_queue_elem_t startReqElem;
+ p_fapi_api_queue_elem_t vendorMsgElem;
+
+ /* Allocte And fill Vendor msg */
+ LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ if(!vendorMsgElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in start req");
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(vendorMsgElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
+ vendorMsg = (fapi_vendor_msg_t *)(vendorMsgElem + 1);
+ fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
+ vendorMsg->start_req_vendor.sfn = 0;
+ vendorMsg->start_req_vendor.slot = 0;
+ vendorMsg->start_req_vendor.mode = 1; /* for FDD */
+#ifdef DEBUG_MODE
+ vendorMsg->start_req_vendor.count = 0;
+ vendorMsg->start_req_vendor.period = 1;
+#endif
+
+ /* Fill FAPI config req */
+ LWR_MAC_ALLOC(startReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_start_req_t)));
+ if(!startReqElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for start req");
+ LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(startReqElem, vendorMsgElem, FAPI_START_REQUEST, 1, \
+ sizeof(fapi_start_req_t));
+
+ startReq = (fapi_start_req_t *)(startReqElem + 1);
+ memset(startReq, 0, sizeof(fapi_start_req_t));
+ fillMsgHeader(&startReq->header, FAPI_START_REQUEST, sizeof(fapi_start_req_t));
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
+ LWR_MAC_ALLOC(startReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_start_req_t)));
+ LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, startReqElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 2; /* Start req msg and vendor specific msg */
+ msgHeader->handle = 0;
+
+ /* Send to PHY */
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending Start Request to Phy");
+ LwrMacSendToL1(headerElem);
+#endif
+ return ROK;
+} /* lwr_mac_procStartReqEvt */
+
+/*******************************************************************
+ *
+ * @brief Sends FAPI Stop Req to PHY
+ *
+ * @details
+ *
+ * Function : lwr_mac_procStopReqEvt
+ *
+ * Functionality:
+ * -Sends FAPI Stop Req to PHY
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ ********************************************************************/
+
+uint8_t lwr_mac_procStopReqEvt(void *msg)
+{
+#ifdef INTEL_FAPI
+ SlotIndInfo *slotInfo;
+ fapi_msg_header_t *msgHeader;
+ fapi_stop_req_t *stopReq;
+ fapi_vendor_msg_t *vendorMsg;
+ p_fapi_api_queue_elem_t headerElem;
+ p_fapi_api_queue_elem_t stopReqElem;
+ p_fapi_api_queue_elem_t vendorMsgElem;
+
+ slotInfo = (SlotIndInfo *)msg;
+
+ /* Allocte And fill Vendor msg */
+ LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ if(!vendorMsgElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in stop req");
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(vendorMsgElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
+ vendorMsg = (fapi_vendor_msg_t *)(vendorMsgElem + 1);
+ fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
+ vendorMsg->stop_req_vendor.sfn = slotInfo->sfn;
+ vendorMsg->stop_req_vendor.slot = slotInfo->slot;
+
+ /* Fill FAPI stop req */
+ LWR_MAC_ALLOC(stopReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_stop_req_t)));
+ if(!stopReqElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for stop req");
+ LWR_MAC_FREE(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(stopReqElem, vendorMsgElem, FAPI_STOP_REQUEST, 1, \
+ sizeof(fapi_stop_req_t));
+ stopReq = (fapi_stop_req_t *)(stopReqElem + 1);
+ memset(stopReq, 0, sizeof(fapi_stop_req_t));
+ fillMsgHeader(&stopReq->header, FAPI_STOP_REQUEST, sizeof(fapi_stop_req_t));
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for header in stop req");
+ LWR_MAC_FREE(stopReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_stop_req_t)));
+ LWR_MAC_FREE(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, stopReqElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 2; /* Stop req msg and vendor specific msg */
+ msgHeader->handle = 0;
+
+ /* Send to PHY */
+ DU_LOG("\nINFO --> LWR_MAC: Sending Stop Request to Phy");
+ LwrMacSendToL1(headerElem);
+
+#endif
+ return ROK;
+}
+
+#ifdef INTEL_FAPI
+/*******************************************************************
+ *
+ * @brief fills SSB PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillSsbPdu
+ *
+ * Functionality:
+ * -Fills the SSB PDU info
+ * stored in MAC
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to RgCellCb
+ * Pointer to msgLen of DL TTI Info
+ * @return ROK
+ *
+ ******************************************************************/
+
+uint8_t fillSsbPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, MacCellCfg *macCellCfg,
+ MacDlSlot *currDlSlot, uint8_t ssbIdxCount, uint16_t sfn)
+{
+ uint32_t mibPayload = 0;
+ if(dlTtiReqPdu != NULL)
+ {
+ dlTtiReqPdu->pduType = SSB_PDU_TYPE; /* SSB PDU */
+ dlTtiReqPdu->pdu.ssb_pdu.physCellId = macCellCfg->phyCellId;
+ dlTtiReqPdu->pdu.ssb_pdu.betaPss = macCellCfg->ssbCfg.betaPss;
+ dlTtiReqPdu->pdu.ssb_pdu.ssbBlockIndex = currDlSlot->dlInfo.brdcstAlloc.ssbInfo[ssbIdxCount].ssbIdx;
+ dlTtiReqPdu->pdu.ssb_pdu.ssbSubCarrierOffset = macCellCfg->ssbCfg.ssbScOffset;
+ /* ssbOfPdufstA to be filled in ssbCfg */
+ dlTtiReqPdu->pdu.ssb_pdu.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;
+ dlTtiReqPdu->pdu.ssb_pdu.bchPayloadFlag = macCellCfg->ssbCfg.bchPayloadFlag;
+ /* Bit manipulation for SFN */
+ setMibPdu(macCellCfg->ssbCfg.mibPdu, &mibPayload, sfn);
+ dlTtiReqPdu->pdu.ssb_pdu.bchPayload.bchPayload = mibPayload;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.numPrgs = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.prgSize = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.digBfInterfaces = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.pmi_bfi[0].pmIdx = 0;
+ dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming. \
+ pmi_bfi[0].beamIdx[0].beamidx = macCellCfg->ssbCfg.beamId[0];
+ dlTtiReqPdu->pduSize = sizeof(fapi_dl_ssb_pdu_t); /* Size of SSB PDU */
+
+ return ROK;
+ }
+ return RFAILED;
+}
+
+/*******************************************************************
+ *
+ * @brief fills Dl DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillSib1DlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes=0;
+ uint8_t bytePos=0;
+ uint8_t bitPos=0;
+
+ uint16_t coreset0Size=0;
+ uint16_t rbStart=0;
+ uint16_t rbLen=0;
+ uint32_t freqDomResAssign=0;
+ uint32_t timeDomResAssign=0;
+ uint8_t VRB2PRBMap=0;
+ uint32_t modNCodScheme=0;
+ uint8_t redundancyVer=0;
+ uint32_t sysInfoInd=0;
+ uint32_t reserved=0;
+
+ /* Size(in bits) of each field in DCI format 0_1
+ * as mentioned in spec 38.214 */
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t redundancyVerSize = 2;
+ uint8_t sysInfoIndSize = 1;
+ uint8_t reservedSize = 15;
+
+ dlDciPtr->rnti = sib1PdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = sib1PdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = sib1PdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = sib1PdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = sib1PdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = sib1PdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = sib1PdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->powerControlOffsetSS = sib1PdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ coreset0Size= sib1PdcchInfo->coresetCfg.coreSetSize;
+ rbStart = 0; /* For SIB1 */
+ //rbStart = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
+ rbLen = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ timeDomResAssign = sib1PdcchInfo->dci.pdschCfg->pdschTimeAlloc.
+ rowIndex -1;
+ VRB2PRBMap = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.\
+ vrbPrbMapping;
+ modNCodScheme = sib1PdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
+ redundancyVer = sib1PdcchInfo->dci.pdschCfg->codeword[0].rvIndex;
+ sysInfoInd = 0; /* 0 for SIB1; 1 for SI messages */
+ reserved = 0;
+
+ /* Reversing bits in each DCI field */
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
+ sysInfoInd = reverseBits(sysInfoInd, sysInfoIndSize);
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ + VRB2PRBMapSize + modNCodSchemeSize + redundancyVerSize\
+ + sysInfoIndSize + reservedSize;
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ sysInfoInd, sysInfoIndSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ reserved, reservedSize);
+
+ }
+} /* fillSib1DlDciPdu */
+
+/*******************************************************************
+ *
+ * @brief fills Dl DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillRarDlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes =0;
+ uint8_t bytePos =0;
+ uint8_t bitPos =0;
+
+ uint16_t coreset0Size =0;
+ uint16_t rbStart =0;
+ uint16_t rbLen =0;
+ uint32_t freqDomResAssign =0;
+ uint8_t timeDomResAssign =0;
+ uint8_t VRB2PRBMap =0;
+ uint8_t modNCodScheme =0;
+ uint8_t tbScaling =0;
+ uint32_t reserved =0;
+
+ /* Size(in bits) of each field in DCI format 1_0 */
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t tbScalingSize = 2;
+ uint8_t reservedSize = 16;
+
+ dlDciPtr->rnti = rarPdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = rarPdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = rarPdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = rarPdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = rarPdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->powerControlOffsetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+
+ /* TODO: Fill values of coreset0Size, rbStart and rbLen */
+ coreset0Size= rarPdcchInfo->coresetCfg.coreSetSize;
+ rbStart = 0; /* For SIB1 */
+ //rbStart = rarPdcchInfo->dci.pdschCfg->freqAlloc.rbStart;
+ rbLen = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ timeDomResAssign = rarPdcchInfo->dci.pdschCfg->pdschTimeAlloc.rowIndex -1;
+ VRB2PRBMap = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = rarPdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
+ tbScaling = 0; /* configured to 0 scaling */
+ reserved = 0;
+
+ /* Reversing bits in each DCI field */
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ tbScaling = reverseBits(tbScaling, tbScalingSize);
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ + VRB2PRBMapSize + modNCodSchemeSize + tbScalingSize + reservedSize;
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ tbScaling, tbScalingSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ reserved, reservedSize);
+ }
+} /* fillRarDlDciPdu */
+
+/*******************************************************************
+ *
+ * @brief fills DL DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillDlMsgDlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\
+ DlMsgInfo *dlMsgInfo)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes;
+ uint8_t bytePos;
+ uint8_t bitPos;
+
+ uint16_t coresetSize = 0;
+ uint16_t rbStart = 0;
+ uint16_t rbLen = 0;
+ uint8_t dciFormatId;
+ uint32_t freqDomResAssign;
+ uint8_t timeDomResAssign;
+ uint8_t VRB2PRBMap;
+ uint8_t modNCodScheme;
+ uint8_t ndi = 0;
+ uint8_t redundancyVer = 0;
+ uint8_t harqProcessNum = 0;
+ uint8_t dlAssignmentIdx = 0;
+ uint8_t pucchTpc = 0;
+ uint8_t pucchResoInd = 0;
+ uint8_t harqFeedbackInd = 0;
+
+ /* Size(in bits) of each field in DCI format 1_0 */
+ uint8_t dciFormatIdSize = 1;
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t ndiSize = 1;
+ uint8_t redundancyVerSize = 2;
+ uint8_t harqProcessNumSize = 4;
+ uint8_t dlAssignmentIdxSize = 2;
+ uint8_t pucchTpcSize = 2;
+ uint8_t pucchResoIndSize = 3;
+ uint8_t harqFeedbackIndSize = 3;
+
+ dlDciPtr->rnti = pdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = pdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = pdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = pdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = pdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = pdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = pdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = pdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->powerControlOffsetSS = pdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ coresetSize = pdcchInfo->coresetCfg.coreSetSize;
+ rbStart = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
+ rbLen = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
+
+ if((rbLen >=1) && (rbLen <= coresetSize - rbStart))
+ {
+ if((rbLen - 1) <= floor(coresetSize / 2))
+ freqDomResAssign = (coresetSize * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coresetSize * (coresetSize - rbLen + 1)) \
+ + (coresetSize - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coresetSize * (coresetSize + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ dciFormatId = dlMsgInfo->dciFormatId; /* Always set to 1 for DL */
+ timeDomResAssign = pdcchInfo->dci.pdschCfg->pdschTimeAlloc.rowIndex -1;
+ VRB2PRBMap = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.vrbPrbMapping;
+ modNCodScheme = pdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
+ ndi = dlMsgInfo->ndi;
+ redundancyVer = pdcchInfo->dci.pdschCfg->codeword[0].rvIndex;
+ harqProcessNum = dlMsgInfo->harqProcNum;
+ dlAssignmentIdx = dlMsgInfo->dlAssignIdx;
+ pucchTpc = dlMsgInfo->pucchTpc;
+ pucchResoInd = dlMsgInfo->pucchResInd;
+ harqFeedbackInd = dlMsgInfo->harqFeedbackInd;
+
+ /* Reversing bits in each DCI field */
+ dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ ndi = reverseBits(ndi, ndiSize);
+ redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
+ harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
+ dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize);
+ pucchTpc = reverseBits(pucchTpc, pucchTpcSize);
+ pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize);
+ harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize);
+
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
+ + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
+ + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\
+ + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize);
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ dciFormatId, dciFormatIdSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ ndi, ndiSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ harqProcessNum, harqProcessNumSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ dlAssignmentIdx, dlAssignmentIdxSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ pucchTpc, pucchTpcSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ pucchResoInd, pucchResoIndSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ harqFeedbackInd, harqFeedbackIndSize);
+ }
+}
+
+/*******************************************************************
+ *
+ * @brief fills PDCCH PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillPdcchPdu
+ *
+ * Functionality:
+ * -Fills the Pdcch PDU info
+ * stored in MAC
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, DlSchedInfo *dlInfo, \
+ RntiType rntiType, uint8_t coreSetType)
+{
+ if(dlTtiReqPdu != NULLP)
+ {
+ PdcchCfg *pdcchInfo = NULLP;
+ BwpCfg *bwp = NULLP;
+
+ memset(&dlTtiReqPdu->pdu.pdcch_pdu, 0, sizeof(fapi_dl_pdcch_pdu_t));
+ if(rntiType == SI_RNTI_TYPE)
+ {
+ pdcchInfo = &dlInfo->brdcstAlloc.sib1Alloc.sib1PdcchCfg;
+ bwp = &dlInfo->brdcstAlloc.sib1Alloc.bwp;
+ fillSib1DlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo);
+ }
+ else if(rntiType == RA_RNTI_TYPE)
+ {
+ pdcchInfo = &dlInfo->rarAlloc->rarPdcchCfg;
+ bwp = &dlInfo->rarAlloc->bwp;
+ fillRarDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo);
+ }
+ else if(rntiType == TC_RNTI_TYPE || rntiType == C_RNTI_TYPE)
+ {
+ pdcchInfo = &dlInfo->dlMsgAlloc->dlMsgPdcchCfg;
+ bwp = &dlInfo->dlMsgAlloc->bwp;
+ fillDlMsgDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo,\
+ &dlInfo->dlMsgAlloc->dlMsgInfo);
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Failed filling PDCCH Pdu");
+ return RFAILED;
+ }
+ dlTtiReqPdu->pduType = PDCCH_PDU_TYPE;
+ dlTtiReqPdu->pdu.pdcch_pdu.bwpSize = bwp->freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdcch_pdu.bwpStart = bwp->freqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdcch_pdu.subCarrierSpacing = bwp->subcarrierSpacing;
+ dlTtiReqPdu->pdu.pdcch_pdu.cyclicPrefix = bwp->cyclicPrefix;
+ dlTtiReqPdu->pdu.pdcch_pdu.startSymbolIndex = pdcchInfo->coresetCfg.startSymbolIndex;
+ dlTtiReqPdu->pdu.pdcch_pdu.durationSymbols = pdcchInfo->coresetCfg.durationSymbols;
+ memcpy(dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource, pdcchInfo->coresetCfg.freqDomainResource, 6);
+ dlTtiReqPdu->pdu.pdcch_pdu.cceRegMappingType = pdcchInfo->coresetCfg.cceRegMappingType;
+ dlTtiReqPdu->pdu.pdcch_pdu.regBundleSize = pdcchInfo->coresetCfg.regBundleSize;
+ dlTtiReqPdu->pdu.pdcch_pdu.interleaverSize = pdcchInfo->coresetCfg.interleaverSize;
+ dlTtiReqPdu->pdu.pdcch_pdu.shiftIndex = pdcchInfo->coresetCfg.shiftIndex;
+ dlTtiReqPdu->pdu.pdcch_pdu.precoderGranularity = pdcchInfo->coresetCfg.precoderGranularity;
+ dlTtiReqPdu->pdu.pdcch_pdu.numDlDci = pdcchInfo->numDlDci;
+ dlTtiReqPdu->pdu.pdcch_pdu.coreSetType = coreSetType;
+
+ /* Calculating PDU length. Considering only one dl dci pdu for now */
+ dlTtiReqPdu->pduSize = sizeof(fapi_dl_pdcch_pdu_t);
+ }
+
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief fills PDSCH PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillPdschPdu
+ *
+ * Functionality:
+ * -Fills the Pdsch PDU info
+ * stored in MAC
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to PdschCfg
+ * Pointer to msgLen of DL TTI Info
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillPdschPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, PdschCfg *pdschInfo,
+ BwpCfg bwp, uint16_t pduIndex)
+{
+ uint8_t idx;
+
+ if(dlTtiReqPdu != NULLP)
+ {
+ dlTtiReqPdu->pduType = PDSCH_PDU_TYPE;
+ memset(&dlTtiReqPdu->pdu.pdsch_pdu, 0, sizeof(fapi_dl_pdsch_pdu_t));
+ dlTtiReqPdu->pdu.pdsch_pdu.pduBitMap = pdschInfo->pduBitmap;
+ dlTtiReqPdu->pdu.pdsch_pdu.rnti = pdschInfo->rnti;
+ dlTtiReqPdu->pdu.pdsch_pdu.pdu_index = pduIndex;
+ dlTtiReqPdu->pdu.pdsch_pdu.bwpSize = bwp.freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.bwpStart = bwp.freqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.subCarrierSpacing = bwp.subcarrierSpacing;
+ dlTtiReqPdu->pdu.pdsch_pdu.cyclicPrefix = bwp.cyclicPrefix;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfCodeWords = pdschInfo->numCodewords;
+ for(idx = 0; idx < MAX_CODEWORDS ; idx++)
+ {
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].targetCodeRate = pdschInfo->codeword[idx].targetCodeRate;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].qamModOrder = pdschInfo->codeword[idx].qamModOrder;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].mcsIndex = pdschInfo->codeword[idx].mcsIndex;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].mcsTable = pdschInfo->codeword[idx].mcsTable;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].rvIndex = pdschInfo->codeword[idx].rvIndex;
+ dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].tbSize = pdschInfo->codeword[idx].tbSize;
+ }
+ dlTtiReqPdu->pdu.pdsch_pdu.dataScramblingId = pdschInfo->dataScramblingId;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfLayers = pdschInfo->numLayers;
+ dlTtiReqPdu->pdu.pdsch_pdu.transmissionScheme = pdschInfo->transmissionScheme;
+ dlTtiReqPdu->pdu.pdsch_pdu.refPoint = pdschInfo->refPoint;
+ dlTtiReqPdu->pdu.pdsch_pdu.dlDmrsSymbPos = pdschInfo->dmrs.dlDmrsSymbPos;
+ dlTtiReqPdu->pdu.pdsch_pdu.dmrsConfigType = pdschInfo->dmrs.dmrsConfigType;
+ dlTtiReqPdu->pdu.pdsch_pdu.dlDmrsScramblingId = pdschInfo->dmrs.dlDmrsScramblingId;
+ dlTtiReqPdu->pdu.pdsch_pdu.scid = pdschInfo->dmrs.scid;
+ dlTtiReqPdu->pdu.pdsch_pdu.numDmrsCdmGrpsNoData = pdschInfo->dmrs.numDmrsCdmGrpsNoData;
+ dlTtiReqPdu->pdu.pdsch_pdu.dmrsPorts = pdschInfo->dmrs.dmrsPorts;
+ dlTtiReqPdu->pdu.pdsch_pdu.resourceAlloc = pdschInfo->pdschFreqAlloc.resourceAllocType;
+ /* since we are using type-1, hence rbBitmap excluded */
+ dlTtiReqPdu->pdu.pdsch_pdu.rbStart = pdschInfo->pdschFreqAlloc.freqAlloc.startPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.rbSize = pdschInfo->pdschFreqAlloc.freqAlloc.numPrb;
+ dlTtiReqPdu->pdu.pdsch_pdu.vrbToPrbMapping = pdschInfo->pdschFreqAlloc.vrbPrbMapping;
+ dlTtiReqPdu->pdu.pdsch_pdu.startSymbIndex = pdschInfo->pdschTimeAlloc.timeAlloc.startSymb;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfSymbols = pdschInfo->pdschTimeAlloc.timeAlloc.numSymb;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.numPrgs = pdschInfo->beamPdschInfo.numPrgs;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.prgSize = pdschInfo->beamPdschInfo.prgSize;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.digBfInterfaces = pdschInfo->beamPdschInfo.digBfInterfaces;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.pmi_bfi[0]. \
+ pmIdx = pdschInfo->beamPdschInfo.prg[0].pmIdx;
+ dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.pmi_bfi[0]. \
+ beamIdx[0].beamidx = pdschInfo->beamPdschInfo.prg[0].beamIdx[0];
+ dlTtiReqPdu->pdu.pdsch_pdu.powerControlOffset = pdschInfo->txPdschPower.powerControlOffset;
+ dlTtiReqPdu->pdu.pdsch_pdu.powerControlOffsetSS = pdschInfo->txPdschPower.powerControlOffsetSS;
+ dlTtiReqPdu->pdu.pdsch_pdu.mappingType = pdschInfo->dmrs.mappingType;
+ dlTtiReqPdu->pdu.pdsch_pdu.nrOfDmrsSymbols = pdschInfo->dmrs.nrOfDmrsSymbols;
+ dlTtiReqPdu->pdu.pdsch_pdu.dmrsAddPos = pdschInfo->dmrs.dmrsAddPos;
+
+ dlTtiReqPdu->pduSize = sizeof(fapi_dl_pdsch_pdu_t);
+ }
+}
+
+/***********************************************************************
+ *
+ * @brief calculates the total size to be allocated for DL TTI Req
+ *
+ * @details
+ *
+ * Function : calcDlTtiReqPduCount
+ *
+ * Functionality:
+ * -calculates the total pdu count to be allocated for DL TTI Req
+ *
+ * @params[in] DlBrdcstAlloc *cellBroadcastInfo
+ * @return count
+ *
+ * ********************************************************************/
+uint8_t calcDlTtiReqPduCount(DlSchedInfo *dlInfo)
+{
+ uint8_t count = 0;
+ uint8_t idx = 0;
+
+ if(dlInfo->isBroadcastPres)
+ {
+ if(dlInfo->brdcstAlloc.ssbTrans)
+ {
+ for(idx = 0; idx < dlInfo->brdcstAlloc.ssbIdxSupported; idx++)
+ {
+ /* SSB PDU is filled */
+ count++;
+ }
+ }
+ if(dlInfo->brdcstAlloc.sib1Trans)
+ {
+ /* PDCCH and PDSCH PDU is filled */
+ count += 2;
+ }
+ }
+ if(dlInfo->rarAlloc != NULLP)
+ {
+ /* PDCCH and PDSCH PDU is filled */
+ count += 2;
+ }
+ if(dlInfo->dlMsgAlloc != NULLP)
+ {
+ /* PDCCH and PDSCH PDU is filled */
+ count += 2;
+ }
+ return count;
+}
+
+/***********************************************************************
+ *
+ * @brief calculates the total size to be allocated for DL TTI Req
+ *
+ * @details
+ *
+ * Function : calcTxDataReqPduCount
+ *
+ * Functionality:
+ * -calculates the total pdu count to be allocated for DL TTI Req
+ *
+ * @params[in] DlBrdcstAlloc *cellBroadcastInfo
+ * @return count
+ *
+ * ********************************************************************/
+uint8_t calcTxDataReqPduCount(DlSchedInfo *dlInfo)
+{
+ uint8_t count = 0;
+
+ if(dlInfo->isBroadcastPres && dlInfo->brdcstAlloc.sib1Trans)
+ {
+ count++;
+ }
+ if(dlInfo->rarAlloc != NULLP)
+ {
+ count++;
+ }
+ if(dlInfo->dlMsgAlloc != NULLP)
+ {
+ count++;
+ }
+ return count;
+}
+/***********************************************************************
+ *
+ * @brief fills the SIB1 TX-DATA request message
+ *
+ * @details
+ *
+ * Function : fillSib1TxDataReq
+ *
+ * Functionality:
+ * - fills the SIB1 TX-DATA request message
+ *
+ * @params[in] fapi_tx_pdu_desc_t *pduDesc
+ * @params[in] macCellCfg consist of SIB1 pdu
+ * @params[in] uint32_t *msgLen
+ * @params[in] uint16_t pduIndex
+ * @return ROK
+ *
+ * ********************************************************************/
+uint8_t fillSib1TxDataReq(fapi_tx_pdu_desc_t *pduDesc,MacCellCfg *macCellCfg,
+ uint16_t pduIndex)
+{
+ uint32_t pduLen = 0;
+ uint8_t *sib1TxdataValue = NULLP;
+
+ pduDesc[pduIndex].pdu_index = pduIndex;
+ pduDesc[pduIndex].num_tlvs = 1;
+
+ /* fill the TLV */
+ /* as of now, memory is allocated from SSI, later WLS memory needs to be taken */
+ pduDesc[pduIndex].tlvs[0].tl.tag = 1; /* pointer to be sent */
+ pduDesc[pduIndex].tlvs[0].tl.length = macCellCfg->sib1Cfg.sib1PduLen;
+ LWR_MAC_ALLOC(sib1TxdataValue,macCellCfg->sib1Cfg.sib1PduLen);
+ if(sib1TxdataValue == NULLP)
+ {
+ return RFAILED;
+ }
+ memcpy(sib1TxdataValue,macCellCfg->sib1Cfg.sib1Pdu,
+ macCellCfg->sib1Cfg.sib1PduLen);
+ pduDesc[pduIndex].tlvs[0].value = sib1TxdataValue;
+
+ /* The total length of the PDU description and PDU data */
+ pduLen += 8; /* size of PDU length 2 bytes, PDU index 2 bytes, numTLV 4 bytes */
+ pduLen += sizeof(fapi_uint8_ptr_tlv_t); /* only 1 TLV is present */
+ pduDesc[pduIndex].pdu_length = pduLen;
+
+#ifdef INTEL_WLS_MEM
+ addWlsBlockToFree(sib1TxdataValue, macCellCfg->sib1Cfg.sib1PduLen, (slotIndIdx-1));
+#else
+ LWR_MAC_FREE(sib1TxdataValue, macCellCfg->sib1Cfg.sib1PduLen);
+#endif
+
+ return ROK;
+}
+
+/***********************************************************************
+ *
+ * @brief fills the RAR TX-DATA request message
+ *
+ * @details
+ *
+ * Function : fillRarTxDataReq
+ *
+ * Functionality:
+ * - fills the RAR TX-DATA request message
+ *
+ * @params[in] fapi_tx_pdu_desc_t *pduDesc
+ * @params[in] RarInfo *rarInfo
+ * @params[in] uint32_t *msgLen
+ * @params[in] uint16_t pduIndex
+ * @return ROK
+ *
+ * ********************************************************************/
+uint8_t fillRarTxDataReq(fapi_tx_pdu_desc_t *pduDesc, RarInfo *rarInfo,
+ uint16_t pduIndex)
+{
+ uint32_t pduLen = 0;
+ uint8_t *rarTxdataValue = NULLP;
+
+ pduDesc[pduIndex].pdu_index = pduIndex;
+ pduDesc[pduIndex].num_tlvs = 1;
+
+ /* fill the TLV */
+ /* as of now, memory is allocated from SSI, later WLS memory needs to be taken */
+ pduDesc[pduIndex].tlvs[0].tl.tag = 1; /* pointer to be sent */
+ pduDesc[pduIndex].tlvs[0].tl.length = rarInfo->rarPduLen;
+ LWR_MAC_ALLOC(rarTxdataValue,rarInfo->rarPduLen);
+ if(rarTxdataValue == NULLP)
+ {
+ return RFAILED;
+ }
+ memcpy(rarTxdataValue,rarInfo->rarPdu,rarInfo->rarPduLen);
+ pduDesc[pduIndex].tlvs[0].value = rarTxdataValue;
+
+ /* The total length of the PDU description and PDU data */
+ pduLen += 8; /* size of PDU length 2 bytes, PDU index 2 bytes, numTLV 4 bytes */
+ pduLen += sizeof(fapi_uint8_ptr_tlv_t); /* only 1 TLV is present */
+ pduDesc[pduIndex].pdu_length = pduLen;
+
+ /* TODO: The pointer value which was stored, needs to be free-ed at PHY *
+ * But since we did not implement WLS, this has to be done here
+ */
+#ifdef INTEL_WLS_MEM
+ addWlsBlockToFree(rarTxdataValue, rarInfo->rarPduLen, (slotIndIdx-1));
+#else
+ LWR_MAC_FREE(rarTxdataValue, rarInfo->rarPduLen);
+#endif
+
+ return ROK;
+}
+
+/***********************************************************************
+ *
+ * @brief fills the DL dedicated Msg TX-DATA request message
+ *
+ * @details
+ *
+ * Function : fillDlMsgTxDataReq
+ *
+ * Functionality:
+ * - fills the Dl Dedicated Msg TX-DATA request message
+ *
+ * @params[in] fapi_tx_pdu_desc_t *pduDesc
+ * @params[in] DlMsgInfo *dlMsgInfo
+ * @params[in] uint32_t *msgLen
+ * @params[in] uint16_t pduIndex
+ * @return ROK
+ *
+ * ********************************************************************/
+uint8_t fillDlMsgTxDataReq(fapi_tx_pdu_desc_t *pduDesc, DlMsgInfo *dlMsgInfo,
+ uint16_t pduIndex)
+{
+ uint32_t pduLen = 0;
+ uint8_t *dedMsgTxDataValue = NULLP;
+
+ pduDesc[pduIndex].pdu_index = pduIndex;
+ pduDesc[pduIndex].num_tlvs = 1;
+
+ /* fill the TLV */
+ /* as of now, memory is allocated from SSI, later WLS memory needs to be taken */
+ pduDesc[pduIndex].tlvs[0].tl.tag = 1; /* pointer to be sent */
+ pduDesc[pduIndex].tlvs[0].tl.length = dlMsgInfo->dlMsgPduLen;
+ LWR_MAC_ALLOC(dedMsgTxDataValue, dlMsgInfo->dlMsgPduLen);
+ if(dedMsgTxDataValue == NULLP)
+ {
+ return RFAILED;
+ }
+ memcpy(dedMsgTxDataValue, dlMsgInfo->dlMsgPdu, dlMsgInfo->dlMsgPduLen);
+ pduDesc[pduIndex].tlvs[0].value = dedMsgTxDataValue;
+
+ /* The total length of the PDU description and PDU data */
+ pduLen += 8; /* size of PDU length 2 bytes, PDU index 2 bytes, numTLV 4 bytes */
+ pduLen += sizeof(fapi_uint8_ptr_tlv_t); /* only 1 TLV is present */
+ pduDesc[pduIndex].pdu_length = pduLen;
+
+ /* TODO: The pointer value which was stored, needs to be free-ed at PHY *
+ * But since we did not implement WLS, this has to be done here
+ */
+#ifdef INTEL_WLS_MEM
+ addWlsBlockToFree(dedMsgTxDataValue, dlMsgInfo->dlMsgPduLen, (slotIndIdx-1));
+#else
+ LWR_MAC_FREE(dedMsgTxDataValue, dlMsgInfo->dlMsgPduLen);
+#endif
+
+ return ROK;
+}
+
+
+#endif /* FAPI */
+/*******************************************************************
+ *
+ * @brief Sends DL TTI Request to PHY
+ *
+ * @details
+ *
+ * Function : fillDlTtiReq
+ *
+ * Functionality:
+ * -Sends FAPI DL TTI req to PHY
+ *
+ * @params[in] timing info
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint16_t fillDlTtiReq(SlotIndInfo currTimingInfo)
+{
+#ifdef INTEL_FAPI
+ uint8_t idx =0;
+ uint8_t nPdu = 0;
+ uint8_t numPduEncoded = 0;
+ uint16_t cellIdx =0;
+ uint16_t pduIndex = 0;
+
+ SlotIndInfo dlTtiReqTimingInfo;
+ MacDlSlot *currDlSlot = NULLP;
+ MacCellCfg macCellCfg;
+ RntiType rntiType;
+ fapi_dl_tti_req_t *dlTtiReq = NULLP;
+ fapi_msg_header_t *msgHeader = NULLP;
+ p_fapi_api_queue_elem_t dlTtiElem;
+ p_fapi_api_queue_elem_t headerElem;
+
+ if(lwrMacCb.phyState == PHY_STATE_RUNNING)
+ {
+ GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
+ /* consider phy delay */
+ ADD_DELTA_TO_TIME(currTimingInfo,dlTtiReqTimingInfo,PHY_DELTA);
+
+ macCellCfg = macCb.macCell[cellIdx]->macCellCfg;
+
+ currDlSlot = &macCb.macCell[cellIdx]->dlSlot[dlTtiReqTimingInfo.slot];
+ nPdu = calcDlTtiReqPduCount(&currDlSlot->dlInfo);
+
+ LWR_MAC_ALLOC(dlTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_dl_tti_req_t)));
+ if(dlTtiElem)
+ {
+ FILL_FAPI_LIST_ELEM(dlTtiElem, NULLP, FAPI_DL_TTI_REQUEST, 1, \
+ sizeof(fapi_dl_tti_req_t));
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for header in DL TTI req");
+ LWR_MAC_FREE(dlTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_dl_tti_req_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, dlTtiElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 1;
+ msgHeader->handle = 0;
+
+ /* Fill Dl TTI Request */
+ dlTtiReq = (fapi_dl_tti_req_t *)(dlTtiElem +1);
+ memset(dlTtiReq, 0, sizeof(fapi_dl_tti_req_t));
+ fillMsgHeader(&dlTtiReq->header, FAPI_DL_TTI_REQUEST, sizeof(fapi_dl_tti_req_t));
+
+ dlTtiReq->sfn = dlTtiReqTimingInfo.sfn;
+ dlTtiReq->slot = dlTtiReqTimingInfo.slot;
+ dlTtiReq->nPdus = calcDlTtiReqPduCount(&currDlSlot->dlInfo); /* get total Pdus */
+ nPdu = dlTtiReq->nPdus;
+ dlTtiReq->nGroup = 0;
+
+ if(dlTtiReq->nPdus > 0)
+ {
+ if(currDlSlot->dlInfo.isBroadcastPres)
+ {
+ if(currDlSlot->dlInfo.brdcstAlloc.ssbTrans)
+ {
+ if(dlTtiReq->pdus != NULLP)
+ {
+ for(idx = 0; idx < currDlSlot->dlInfo.brdcstAlloc.ssbIdxSupported; idx++)
+ {
+ fillSsbPdu(&dlTtiReq->pdus[numPduEncoded], &macCellCfg,\
+ currDlSlot, idx, dlTtiReq->sfn);
+ numPduEncoded++;
+ }
+ }
+ DU_LOG("\033[1;31m");
+ DU_LOG("\nDEBUG --> LWR_MAC: MIB sent..");
+ DU_LOG("\033[0m");
+ }
+ if(currDlSlot->dlInfo.brdcstAlloc.sib1Trans)
+ {
+ /* Filling SIB1 param */
+ if(numPduEncoded != nPdu)
+ {
+ rntiType = SI_RNTI_TYPE;
+ fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded],&currDlSlot->dlInfo,\
+ rntiType, CORESET_TYPE0);
+ numPduEncoded++;
+ fillPdschPdu(&dlTtiReq->pdus[numPduEncoded],
+ &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg,
+ currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp,
+ pduIndex);
+ pduIndex++;
+ numPduEncoded++;
+ }
+ DU_LOG("\033[1;34m");
+ DU_LOG("\nDEBUG --> LWR_MAC: SIB1 sent...");
+ DU_LOG("\033[0m");
+ }
+ }
+ if(currDlSlot->dlInfo.rarAlloc != NULLP)
+ {
+ /* Filling RAR param */
+ rntiType = RA_RNTI_TYPE;
+ fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], \
+ &currDlSlot->dlInfo, rntiType, CORESET_TYPE0);
+ numPduEncoded++;
+ fillPdschPdu(&dlTtiReq->pdus[numPduEncoded],
+ &currDlSlot->dlInfo.rarAlloc->rarPdschCfg,
+ currDlSlot->dlInfo.rarAlloc->bwp,
+ pduIndex);
+ numPduEncoded++;
+ pduIndex++;
+
+ DU_LOG("\033[1;32m");
+ DU_LOG("\nDEBUG --> LWR_MAC: RAR sent...");
+ DU_LOG("\033[0m");
+ }
+ if(currDlSlot->dlInfo.dlMsgAlloc != NULLP)
+ {
+ if(currDlSlot->dlInfo.dlMsgAlloc->dlMsgInfo.dlMsgPdu != NULLP)
+ {
+ /* Filling Msg4 param */
+ DU_LOG("\033[1;32m");
+ if(currDlSlot->dlInfo.dlMsgAlloc->dlMsgInfo.isMsg4Pdu)
+ {
+ rntiType = TC_RNTI_TYPE;
+ fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], \
+ &currDlSlot->dlInfo, rntiType, CORESET_TYPE0);
+ DU_LOG("\nDEBUG --> LWR_MAC: MSG4 sent...");
+ }
+ else
+ {
+ /* Filling other DL msg params */
+ rntiType = C_RNTI_TYPE;
+ fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], \
+ &currDlSlot->dlInfo, rntiType, CORESET_TYPE1);
+ DU_LOG("\nDEBUG --> LWR_MAC: DL MSG sent...");
+ }
+ DU_LOG("\033[0m");
+
+ numPduEncoded++;
+ fillPdschPdu(&dlTtiReq->pdus[numPduEncoded],
+ &currDlSlot->dlInfo.dlMsgAlloc->dlMsgPdschCfg,
+ currDlSlot->dlInfo.dlMsgAlloc->bwp,
+ pduIndex);
+ numPduEncoded++;
+ pduIndex++;
+ }
+ else
+ {
+ MAC_FREE(currDlSlot->dlInfo.dlMsgAlloc, sizeof(DlMsgAlloc));
+ currDlSlot->dlInfo.dlMsgAlloc = NULLP;
+ }
+ }
+
+#ifdef ODU_SLOT_IND_DEBUG_LOG
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending DL TTI Request");
+#endif
+ LwrMacSendToL1(headerElem);
+
+ /* send Tx-DATA req message */
+ sendTxDataReq(currTimingInfo, &currDlSlot->dlInfo);
+ }
+ else
+ {
+#ifdef ODU_SLOT_IND_DEBUG_LOG
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending DL TTI Request");
+#endif
+ LwrMacSendToL1(headerElem);
+ }
+ memset(currDlSlot, 0, sizeof(MacDlSlot));
+ return ROK;
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for DL TTI Request");
+ memset(currDlSlot, 0, sizeof(MacDlSlot));
+ return RFAILED;
+ }
+ }
+ else
+ {
+ lwr_mac_procInvalidEvt(&currTimingInfo);
+ return RFAILED;
+ }
+#endif
+ return ROK;
+}
+
+/*******************************************************************
+ *
+ * @brief Sends TX data Request to PHY
+ *
+ * @details
+ *
+ * Function : sendTxDataReq
+ *
+ * Functionality:
+ * -Sends FAPI TX data req to PHY
+ *
+ * @params[in] timing info
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+uint16_t sendTxDataReq(SlotIndInfo currTimingInfo, DlSchedInfo *dlInfo)
+{
+#ifdef INTEL_FAPI
+ uint8_t nPdu = 0;
+ uint16_t cellIdx;
+ uint16_t pduIndex = 0;
+ fapi_tx_data_req_t *txDataReq =NULLP;
+ fapi_msg_header_t *msgHeader =NULLP;
+ p_fapi_api_queue_elem_t txDataElem = 0;
+ p_fapi_api_queue_elem_t headerElem =0;
+
+ GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
+
+ /* send TX_Data request message */
+ nPdu = calcTxDataReqPduCount(dlInfo);
+ if(nPdu > 0)
+ {
+ LWR_MAC_ALLOC(txDataElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_tx_data_req_t)));
+ if(txDataElem == NULLP)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for TX data Request");
+ return RFAILED;
+ }
+
+ FILL_FAPI_LIST_ELEM(txDataElem, NULLP, FAPI_TX_DATA_REQUEST, 1, \
+ sizeof(fapi_tx_data_req_t));
+ txDataReq = (fapi_tx_data_req_t *)(txDataElem +1);
+ memset(txDataReq, 0, sizeof(fapi_tx_data_req_t));
+ fillMsgHeader(&txDataReq->header, FAPI_TX_DATA_REQUEST, sizeof(fapi_tx_data_req_t));
+
+ txDataReq->sfn = currTimingInfo.sfn;
+ txDataReq->slot = currTimingInfo.slot;
+ if(dlInfo->brdcstAlloc.sib1Trans)
+ {
+ fillSib1TxDataReq(txDataReq->pdu_desc,
+ &macCb.macCell[cellIdx]->macCellCfg, pduIndex);
+ pduIndex++;
+ txDataReq->num_pdus++;
+ }
+ if(dlInfo->rarAlloc != NULLP)
+ {
+ fillRarTxDataReq(txDataReq->pdu_desc, &dlInfo->rarAlloc->rarInfo, pduIndex);
+ pduIndex++;
+ txDataReq->num_pdus++;
+
+ MAC_FREE(dlInfo->rarAlloc,sizeof(RarAlloc));
+ dlInfo->rarAlloc = NULLP;
+ }
+ if(dlInfo->dlMsgAlloc != NULLP)
+ {
+ fillDlMsgTxDataReq(txDataReq->pdu_desc, \
+ &dlInfo->dlMsgAlloc->dlMsgInfo, pduIndex);
+ pduIndex++;
+ txDataReq->num_pdus++;
+
+ MAC_FREE(dlInfo->dlMsgAlloc->dlMsgInfo.dlMsgPdu,\
+ dlInfo->dlMsgAlloc->dlMsgInfo.dlMsgPduLen);
+ dlInfo->dlMsgAlloc->dlMsgInfo.dlMsgPdu = NULLP;
+ MAC_FREE(dlInfo->dlMsgAlloc, sizeof(DlMsgAlloc));
+ dlInfo->dlMsgAlloc = NULLP;
+ }
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for TxDataReq header");
+ LWR_MAC_FREE(txDataElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_tx_data_req_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, txDataElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 1;
+ msgHeader->handle = 0;
+
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending TX DATA Request");
+ LwrMacSendToL1(headerElem);
+ }
+#endif
+ return ROK;
+}
+
+/***********************************************************************
+ *
+ * @brief calculates the total size to be allocated for UL TTI Req
+ *
+ * @details
+ *
+ * Function : getnPdus
+ *
+ * Functionality:
+ * -calculates the total pdu count to be allocated for UL TTI Req
+ *
+ * @params[in] Pointer to fapi Ul TTI Req
+ * Pointer to CurrUlSlot
+ * @return count
+ * ********************************************************************/
+#ifdef INTEL_FAPI
+uint8_t getnPdus(fapi_ul_tti_req_t *ulTtiReq, MacUlSlot *currUlSlot)
+{
+ uint8_t pduCount = 0;
+
+ if(ulTtiReq && currUlSlot)
+ {
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PRACH)
+ {
+ pduCount++;
+ ulTtiReq->rachPresent++;
+ }
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH)
+ {
+ pduCount++;
+ ulTtiReq->nUlsch++;
+ }
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH_UCI)
+ {
+ pduCount++;
+ ulTtiReq->nUlsch++;
+ }
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_UCI)
+ {
+ pduCount++;
+ ulTtiReq->nUlcch++;
+ }
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_SRS)
+ {
+ pduCount++;
+ }
+ }
+ return pduCount;
+}
+#endif
+
+/***********************************************************************
+ *
+ * @brief Set the value of zero correlation config in PRACH PDU
+ *
+ * @details
+ *
+ * Function : setNumCs
+ *
+ * Functionality:
+ * -Set the value of zero correlation config in PRACH PDU
+ *
+ * @params[in] Pointer to zero correlation config
+ * Pointer to MacCellCfg
+ * ********************************************************************/
+
+void setNumCs(uint16_t *numCs, MacCellCfg *macCellCfg)
+{
+#ifdef INTEL_FAPI
+ uint8_t idx;
+ if(macCellCfg != NULLP)
+ {
+ idx = macCellCfg->prachCfg.fdm[0].zeroCorrZoneCfg;
+ *numCs = UnrestrictedSetNcsTable[idx];
+ }
+#endif
+}
+
+/***********************************************************************
+ *
+ * @brief Fills the PRACH PDU in UL TTI Request
+ *
+ * @details
+ *
+ * Function : fillPrachPdu
+ *
+ * Functionality:
+ * -Fills the PRACH PDU in UL TTI Request
+ *
+ * @params[in] Pointer to Prach Pdu
+ * Pointer to CurrUlSlot
+ * Pointer to macCellCfg
+ * Pointer to msgLen
+ * ********************************************************************/
+
+#ifdef INTEL_FAPI
+void fillPrachPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, MacCellCfg *macCellCfg, MacUlSlot *currUlSlot)
+{
+ if(ulTtiReqPdu != NULLP)
+ {
+ ulTtiReqPdu->pduType = PRACH_PDU_TYPE;
+ ulTtiReqPdu->pdu.prach_pdu.physCellId = macCellCfg->phyCellId;
+ ulTtiReqPdu->pdu.prach_pdu.numPrachOcas = \
+ currUlSlot->ulInfo.prachSchInfo.numPrachOcas;
+ ulTtiReqPdu->pdu.prach_pdu.prachFormat = \
+ currUlSlot->ulInfo.prachSchInfo.prachFormat;
+ ulTtiReqPdu->pdu.prach_pdu.numRa = currUlSlot->ulInfo.prachSchInfo.numRa;
+ ulTtiReqPdu->pdu.prach_pdu.prachStartSymbol = \
+ currUlSlot->ulInfo.prachSchInfo.prachStartSymb;
+ setNumCs(&ulTtiReqPdu->pdu.prach_pdu.numCs, macCellCfg);
+ ulTtiReqPdu->pdu.prach_pdu.beamforming.numPrgs = 0;
+ ulTtiReqPdu->pdu.prach_pdu.beamforming.prgSize = 0;
+ ulTtiReqPdu->pdu.prach_pdu.beamforming.digBfInterface = 0;
+ ulTtiReqPdu->pdu.prach_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = 0;
+ ulTtiReqPdu->pduSize = sizeof(fapi_ul_prach_pdu_t);
+ }
+}
+
+/*******************************************************************
+ *
+ * @brief Filling PUSCH PDU in UL TTI Request
+ *
+ * @details
+ *
+ * Function : fillPuschPdu
+ *
+ * Functionality: Filling PUSCH PDU in UL TTI Request
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+void fillPuschPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, MacCellCfg *macCellCfg, MacUlSlot *currUlSlot)
+{
+ if(ulTtiReqPdu != NULLP)
+ {
+ ulTtiReqPdu->pduType = PUSCH_PDU_TYPE;
+ memset(&ulTtiReqPdu->pdu.pusch_pdu, 0, sizeof(fapi_ul_pusch_pdu_t));
+ ulTtiReqPdu->pdu.pusch_pdu.pduBitMap = 1;
+ ulTtiReqPdu->pdu.pusch_pdu.rnti = currUlSlot->ulInfo.crnti;
+ /* TODO : Fill handle in raCb when scheduling pusch and access here */
+ ulTtiReqPdu->pdu.pusch_pdu.handle = 100;
+ ulTtiReqPdu->pdu.pusch_pdu.bwpSize = macCellCfg->initialUlBwp.bwp.numPrb;
+ ulTtiReqPdu->pdu.pusch_pdu.bwpStart = macCellCfg->initialUlBwp.bwp.firstPrb;
+ ulTtiReqPdu->pdu.pusch_pdu.subCarrierSpacing = \
+ macCellCfg->initialUlBwp.bwp.scs;
+ ulTtiReqPdu->pdu.pusch_pdu.cyclicPrefix = \
+ macCellCfg->initialUlBwp.bwp.cyclicPrefix;
+ ulTtiReqPdu->pdu.pusch_pdu.targetCodeRate = 308;
+ ulTtiReqPdu->pdu.pusch_pdu.qamModOrder = currUlSlot->ulInfo.schPuschInfo.tbInfo.qamOrder;
+ ulTtiReqPdu->pdu.pusch_pdu.mcsIndex = currUlSlot->ulInfo.schPuschInfo.tbInfo.mcs;
+ ulTtiReqPdu->pdu.pusch_pdu.mcsTable = currUlSlot->ulInfo.schPuschInfo.tbInfo.mcsTable;
+ ulTtiReqPdu->pdu.pusch_pdu.transformPrecoding = 1;
+ ulTtiReqPdu->pdu.pusch_pdu.dataScramblingId = currUlSlot->ulInfo.cellId;
+ ulTtiReqPdu->pdu.pusch_pdu.nrOfLayers = 1;
+ ulTtiReqPdu->pdu.pusch_pdu.ulDmrsSymbPos = 4;
+ ulTtiReqPdu->pdu.pusch_pdu.dmrsConfigType = 0;
+ ulTtiReqPdu->pdu.pusch_pdu.ulDmrsScramblingId = currUlSlot->ulInfo.cellId;
+ ulTtiReqPdu->pdu.pusch_pdu.scid = 0;
+ ulTtiReqPdu->pdu.pusch_pdu.numDmrsCdmGrpsNoData = 1;
+ ulTtiReqPdu->pdu.pusch_pdu.dmrsPorts = 0;
+ ulTtiReqPdu->pdu.pusch_pdu.resourceAlloc = \
+ currUlSlot->ulInfo.schPuschInfo.resAllocType;
+ ulTtiReqPdu->pdu.pusch_pdu.rbStart = \
+ currUlSlot->ulInfo.schPuschInfo.fdAlloc.startPrb;
+ ulTtiReqPdu->pdu.pusch_pdu.rbSize = \
+ currUlSlot->ulInfo.schPuschInfo.fdAlloc.numPrb;
+ ulTtiReqPdu->pdu.pusch_pdu.vrbToPrbMapping = 0;
+ ulTtiReqPdu->pdu.pusch_pdu.frequencyHopping = 0;
+ ulTtiReqPdu->pdu.pusch_pdu.txDirectCurrentLocation = 0;
+ ulTtiReqPdu->pdu.pusch_pdu.uplinkFrequencyShift7p5khz = 0;
+ ulTtiReqPdu->pdu.pusch_pdu.startSymbIndex = \
+ currUlSlot->ulInfo.schPuschInfo.tdAlloc.startSymb;
+ ulTtiReqPdu->pdu.pusch_pdu.nrOfSymbols = \
+ currUlSlot->ulInfo.schPuschInfo.tdAlloc.numSymb;
+ ulTtiReqPdu->pdu.pusch_pdu.mappingType = \
+ currUlSlot->ulInfo.schPuschInfo.dmrsMappingType;
+ ulTtiReqPdu->pdu.pusch_pdu.nrOfDmrsSymbols = \
+ currUlSlot->ulInfo.schPuschInfo.nrOfDmrsSymbols;
+ ulTtiReqPdu->pdu.pusch_pdu.dmrsAddPos = \
+ currUlSlot->ulInfo.schPuschInfo.dmrsAddPos;
+ ulTtiReqPdu->pdu.pusch_pdu.puschData.rvIndex = \
+ currUlSlot->ulInfo.schPuschInfo.tbInfo.rv;
+ ulTtiReqPdu->pdu.pusch_pdu.puschData.harqProcessId = \
+ currUlSlot->ulInfo.schPuschInfo.harqProcId;
+ ulTtiReqPdu->pdu.pusch_pdu.puschData.newDataIndicator = \
+ currUlSlot->ulInfo.schPuschInfo.tbInfo.ndi;
+ ulTtiReqPdu->pdu.pusch_pdu.puschData.tbSize = \
+ currUlSlot->ulInfo.schPuschInfo.tbInfo.tbSize;
+ /* numCb is 0 for new transmission */
+ ulTtiReqPdu->pdu.pusch_pdu.puschData.numCb = 0;
+
+ ulTtiReqPdu->pduSize = sizeof(fapi_ul_pusch_pdu_t);
+ }
+}
+
+/*******************************************************************
+ *
+ * @brief Fill PUCCH PDU in Ul TTI Request
+ *
+ * @details
+ *
+ * Function : fillPucchPdu
+ *
+ * Functionality: Fill PUCCH PDU in Ul TTI Request
+ *
+ * @params[in]
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ * ****************************************************************/
+void fillPucchPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, MacCellCfg *macCellCfg,\
+ MacUlSlot *currUlSlot)
+{
+ if(ulTtiReqPdu != NULLP)
+ {
+ ulTtiReqPdu->pduType = PUCCH_PDU_TYPE;
+ memset(&ulTtiReqPdu->pdu.pucch_pdu, 0, sizeof(fapi_ul_pucch_pdu_t));
+ ulTtiReqPdu->pdu.pucch_pdu.rnti = currUlSlot->ulInfo.schPucchInfo.rnti;
+ /* TODO : Fill handle in raCb when scheduling pucch and access here */
+ ulTtiReqPdu->pdu.pucch_pdu.handle = 100;
+ ulTtiReqPdu->pdu.pucch_pdu.bwpSize = macCellCfg->initialUlBwp.bwp.numPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.bwpStart = macCellCfg->initialUlBwp.bwp.firstPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.subCarrierSpacing = macCellCfg->initialUlBwp.bwp.scs;
+ ulTtiReqPdu->pdu.pucch_pdu.cyclicPrefix = macCellCfg->initialUlBwp.bwp.cyclicPrefix;
+ ulTtiReqPdu->pdu.pucch_pdu.formatType = currUlSlot->ulInfo.schPucchInfo.pucchFormat; /* Supporting PUCCH Format 0 */
+ ulTtiReqPdu->pdu.pucch_pdu.multiSlotTxIndicator = 0; /* No Multi Slot transmission */
+
+ ulTtiReqPdu->pdu.pucch_pdu.prbStart = currUlSlot->ulInfo.schPucchInfo.fdAlloc.startPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.prbSize = currUlSlot->ulInfo.schPucchInfo.fdAlloc.numPrb;
+ ulTtiReqPdu->pdu.pucch_pdu.startSymbolIndex = currUlSlot->ulInfo.schPucchInfo.tdAlloc.startSymb;
+ ulTtiReqPdu->pdu.pucch_pdu.nrOfSymbols = currUlSlot->ulInfo.schPucchInfo.tdAlloc.numSymb;
+ ulTtiReqPdu->pdu.pucch_pdu.freqHopFlag = currUlSlot->ulInfo.schPucchInfo.intraFreqHop;
+ ulTtiReqPdu->pdu.pucch_pdu.secondHopPrb = currUlSlot->ulInfo.schPucchInfo.secondPrbHop;
+ ulTtiReqPdu->pdu.pucch_pdu.groupHopFlag = 0;
+ ulTtiReqPdu->pdu.pucch_pdu.sequenceHopFlag = 0;
+ ulTtiReqPdu->pdu.pucch_pdu.hoppingId = 0;
+
+ ulTtiReqPdu->pdu.pucch_pdu.initialCyclicShift = currUlSlot->ulInfo.schPucchInfo.initialCyclicShift;
+
+ ulTtiReqPdu->pdu.pucch_pdu.dataScramblingId = 0; /* Valid for Format 2, 3, 4 */
+ ulTtiReqPdu->pdu.pucch_pdu.timeDomainOccIdx = currUlSlot->ulInfo.schPucchInfo.timeDomOCC;
+ ulTtiReqPdu->pdu.pucch_pdu.preDftOccIdx = currUlSlot->ulInfo.schPucchInfo.occIdx; /* Valid for Format 4 only */
+ ulTtiReqPdu->pdu.pucch_pdu.preDftOccLen = currUlSlot->ulInfo.schPucchInfo.occLen; /* Valid for Format 4 only */
+ ulTtiReqPdu->pdu.pucch_pdu.pi2Bpsk = currUlSlot->ulInfo.schPucchInfo.cmnFormatCfg.pi2BPSK;
+ ulTtiReqPdu->pdu.pucch_pdu.addDmrsFlag = currUlSlot->ulInfo.schPucchInfo.cmnFormatCfg.addDmrs;/* Valid for Format 3, 4 only */
+ ulTtiReqPdu->pdu.pucch_pdu.dmrsScramblingId = 0; /* Valid for Format 2 */
+ ulTtiReqPdu->pdu.pucch_pdu.dmrsCyclicShift = 0; /* Valid for Format 4 */
+ ulTtiReqPdu->pdu.pucch_pdu.srFlag = currUlSlot->ulInfo.schPucchInfo.srFlag;
+ ulTtiReqPdu->pdu.pucch_pdu.bitLenHarq = currUlSlot->ulInfo.schPucchInfo.numHarqBits;
+ ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart1 = 0; /* Valid for Format 2, 3, 4 */
+ ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart2 = 0; /* Valid for Format 2, 3, 4 */
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.numPrgs = 0; /* Not Supported */
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.prgSize = 0;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.digBfInterface = 0;
+ ulTtiReqPdu->pdu.pucch_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = 0;
+
+ ulTtiReqPdu->pduSize = sizeof(fapi_ul_pucch_pdu_t);
+ }
+}
+
+#endif
+
+/*******************************************************************
+ *
+ * @brief Sends UL TTI Request to PHY
+ *
+ * @details
+ *
+ * Function : fillUlTtiReq
+ *
+ * Functionality:
+ * -Sends FAPI Param req to PHY
+ *
+ * @params[in] Pointer to CmLteTimingInfo
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ ******************************************************************/
+uint16_t fillUlTtiReq(SlotIndInfo currTimingInfo)
+{
+#ifdef INTEL_FAPI
+ uint16_t cellIdx =0;
+ uint8_t pduIdx = -1;
+ SlotIndInfo ulTtiReqTimingInfo;
+ MacUlSlot *currUlSlot = NULLP;
+ MacCellCfg macCellCfg;
+ fapi_ul_tti_req_t *ulTtiReq = NULLP;
+ fapi_msg_header_t *msgHeader = NULLP;
+ p_fapi_api_queue_elem_t ulTtiElem;
+ p_fapi_api_queue_elem_t headerElem;
+
+ if(lwrMacCb.phyState == PHY_STATE_RUNNING)
+ {
+ GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
+ macCellCfg = macCb.macCell[cellIdx]->macCellCfg;
+
+ /* add PHY delta */
+ ADD_DELTA_TO_TIME(currTimingInfo,ulTtiReqTimingInfo,PHY_DELTA);
+ currUlSlot = &macCb.macCell[cellIdx]->ulSlot[ulTtiReqTimingInfo.slot % MAX_SLOT_SUPPORTED];
+
+ LWR_MAC_ALLOC(ulTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_ul_tti_req_t)));
+ if(ulTtiElem)
+ {
+ FILL_FAPI_LIST_ELEM(ulTtiElem, NULLP, FAPI_UL_TTI_REQUEST, 1, \
+ sizeof(fapi_ul_tti_req_t));
+ ulTtiReq = (fapi_ul_tti_req_t *)(ulTtiElem +1);
+ memset(ulTtiReq, 0, sizeof(fapi_ul_tti_req_t));
+ fillMsgHeader(&ulTtiReq->header, FAPI_UL_TTI_REQUEST, sizeof(fapi_ul_tti_req_t));
+ ulTtiReq->sfn = ulTtiReqTimingInfo.sfn;
+ ulTtiReq->slot = ulTtiReqTimingInfo.slot;
+ ulTtiReq->nPdus = getnPdus(ulTtiReq, currUlSlot);
+ ulTtiReq->nGroup = 0;
+ if(ulTtiReq->nPdus > 0)
+ {
+ /* Fill Prach Pdu */
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PRACH)
+ {
+ pduIdx++;
+ fillPrachPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
+ }
+
+ /* Fill PUSCH PDU */
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH)
+ {
+ pduIdx++;
+ fillPuschPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
+ }
+ /* Fill PUCCH PDU */
+ if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_UCI)
+ {
+ pduIdx++;
+ fillPucchPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
+ }
+ }
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for UL TTI req header");
+ LWR_MAC_FREE(ulTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_ul_tti_req_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, ulTtiElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 1;
+ msgHeader->handle = 0;
+#ifdef ODU_SLOT_IND_DEBUG_LOG
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending UL TTI Request");
+#endif
+ LwrMacSendToL1(headerElem);
+
+ memset(currUlSlot, 0, sizeof(MacUlSlot));
+ return ROK;
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for UL TTI Request");
+ memset(currUlSlot, 0, sizeof(MacUlSlot));
+ return RFAILED;
+ }
+ }
+ else
+ {
+ lwr_mac_procInvalidEvt(&currTimingInfo);
+ }
+#endif
+ return ROK;
+}
+
+#ifdef INTEL_FAPI
+/*******************************************************************
+ *
+ * @brief fills bsr Ul DCI PDU required for UL DCI Request to PHY
+ *
+ * @details
+ *
+ * Function : fillUlDciPdu
+ *
+ * Functionality:
+ * -Fills the Ul DCI PDU, spec Ref:38.212, Table 7.3.1-1
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to DciInfo
+ * @return ROK
+ *
+ ******************************************************************/
+void fillUlDciPdu(fapi_dl_dci_t *ulDciPtr, DciInfo *schDciInfo)
+{
+ if(ulDciPtr != NULLP)
+ {
+ uint8_t numBytes =0;
+ uint8_t bytePos =0;
+ uint8_t bitPos =0;
+
+ uint8_t coreset1Size = 0;
+ uint16_t rbStart = 0;
+ uint16_t rbLen = 0;
+ uint8_t dciFormatId = 0;
+ uint32_t freqDomResAssign =0;
+ uint8_t timeDomResAssign =0;
+ uint8_t freqHopFlag =0;
+ uint8_t modNCodScheme =0;
+ uint8_t ndi =0;
+ uint8_t redundancyVer = 0;
+ uint8_t harqProcessNum = 0;
+ uint8_t puschTpc = 0;
+ uint8_t ul_SlInd = 0;
+
+ /* Size(in bits) of each field in DCI format 0_0 */
+ uint8_t dciFormatIdSize = 1;
+ uint8_t freqDomResAssignSize = 0;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t freqHopFlagSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t ndiSize = 1;
+ uint8_t redundancyVerSize = 2;
+ uint8_t harqProcessNumSize = 4;
+ uint8_t puschTpcSize = 2;
+ uint8_t ul_SlIndSize = 1;
+
+ ulDciPtr->rnti = schDciInfo->dciInfo.rnti;
+ ulDciPtr->scramblingId = schDciInfo->dciInfo.scramblingId;
+ ulDciPtr->scramblingRnti = schDciInfo->dciInfo.scramblingRnti;
+ ulDciPtr->cceIndex = schDciInfo->dciInfo.cceIndex;
+ ulDciPtr->aggregationLevel = schDciInfo->dciInfo.aggregLevel;
+ ulDciPtr->pc_and_bform.numPrgs = schDciInfo->dciInfo.beamPdcchInfo.numPrgs;
+ ulDciPtr->pc_and_bform.prgSize = schDciInfo->dciInfo.beamPdcchInfo.prgSize;
+ ulDciPtr->pc_and_bform.digBfInterfaces = schDciInfo->dciInfo.beamPdcchInfo.digBfInterfaces;
+ ulDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].pmIdx;
+ ulDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0];
+ ulDciPtr->beta_pdcch_1_0 = schDciInfo->dciInfo.txPdcchPower.powerValue;
+ ulDciPtr->powerControlOffsetSS = schDciInfo->dciInfo.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset1Size = Size of coreset 1
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+ if(schDciInfo->formatType == FORMAT0_0)
+ {
+ coreset1Size = schDciInfo->coresetCfg.coreSetSize;
+ rbLen = schDciInfo->format.format0_0.freqAlloc.numPrb;
+ rbStart = schDciInfo->format.format0_0.freqAlloc.startPrb;
+
+ if((rbLen >=1) && (rbLen <= coreset1Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset1Size / 2))
+ freqDomResAssign = (coreset1Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset1Size * (coreset1Size - rbLen + 1)) \
+ + (coreset1Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset1Size * (coreset1Size + 1) / 2));
+ }
+ /* Fetching DCI field values */
+ dciFormatId = schDciInfo->formatType; /* DCI indentifier for UL DCI */
+ timeDomResAssign = schDciInfo->format.format0_0.rowIndex;
+ freqHopFlag = schDciInfo->format.format0_0.freqHopFlag;
+ modNCodScheme = schDciInfo->format.format0_0.mcs;
+ ndi = schDciInfo->format.format0_0.ndi;
+ redundancyVer = schDciInfo->format.format0_0.rv;
+ harqProcessNum = schDciInfo->format.format0_0.harqProcId;
+ puschTpc = schDciInfo->format.format0_0.tpcCmd;
+ ul_SlInd = schDciInfo->format.format0_0.sUlCfgd;
+
+ /* Reversing bits in each DCI field */
+ dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
+ harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
+ puschTpc = reverseBits(puschTpc, puschTpcSize);
+ ul_SlInd = reverseBits(ul_SlInd, ul_SlIndSize);
+ }
+ /* Calulating total number of bytes in buffer */
+ ulDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
+ + timeDomResAssignSize + freqHopFlagSize + modNCodSchemeSize + ndi \
+ + redundancyVerSize + harqProcessNumSize + puschTpcSize + ul_SlIndSize);
+
+ numBytes = ulDciPtr->payloadSizeBits / 8;
+ if(ulDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ ulDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ dciFormatId, dciFormatIdSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ freqHopFlag, freqHopFlagSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ ndi, ndiSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ harqProcessNum, harqProcessNumSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ puschTpc, puschTpcSize);
+ fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
+ ul_SlInd, ul_SlIndSize);
+ }
+} /* fillUlDciPdu */
+
+/*******************************************************************
+ *
+ * @brief fills PDCCH PDU required for UL DCI REQ to PHY
+ *
+ * @details
+ *
+ * Function : fillUlDciPdcchPdu
+ *
+ * Functionality:
+ * -Fills the Pdcch PDU info
+ *
+ * @params[in] Pointer to FAPI DL TTI Req
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+uint8_t fillUlDciPdcchPdu(fapi_dci_pdu_t *ulDciReqPdu, DlSchedInfo *dlInfo, uint8_t coreSetType)
+{
+ if(ulDciReqPdu != NULLP)
+ {
+ memset(&ulDciReqPdu->pdcchPduConfig, 0, sizeof(fapi_dl_pdcch_pdu_t));
+ fillUlDciPdu(ulDciReqPdu->pdcchPduConfig.dlDci, dlInfo->ulGrant);
+ ulDciReqPdu->pduType = PDCCH_PDU_TYPE;
+ ulDciReqPdu->pdcchPduConfig.bwpSize = dlInfo->ulGrant->bwpCfg.freqAlloc.numPrb;
+ ulDciReqPdu->pdcchPduConfig.bwpStart = dlInfo->ulGrant->bwpCfg.freqAlloc.startPrb;
+ ulDciReqPdu->pdcchPduConfig.subCarrierSpacing = dlInfo->ulGrant->bwpCfg.subcarrierSpacing;
+ ulDciReqPdu->pdcchPduConfig.cyclicPrefix = dlInfo->ulGrant->bwpCfg.cyclicPrefix;
+ ulDciReqPdu->pdcchPduConfig.startSymbolIndex = dlInfo->ulGrant->coresetCfg.startSymbolIndex;
+ ulDciReqPdu->pdcchPduConfig.durationSymbols = dlInfo->ulGrant->coresetCfg.durationSymbols;
+ memcpy(ulDciReqPdu->pdcchPduConfig.freqDomainResource, dlInfo->ulGrant->coresetCfg.freqDomainResource, 6);
+ ulDciReqPdu->pdcchPduConfig.cceRegMappingType = dlInfo->ulGrant->coresetCfg.cceRegMappingType;
+ ulDciReqPdu->pdcchPduConfig.regBundleSize = dlInfo->ulGrant->coresetCfg.regBundleSize;
+ ulDciReqPdu->pdcchPduConfig.interleaverSize = dlInfo->ulGrant->coresetCfg.interleaverSize;
+ ulDciReqPdu->pdcchPduConfig.shiftIndex = dlInfo->ulGrant->coresetCfg.shiftIndex;
+ ulDciReqPdu->pdcchPduConfig.precoderGranularity = dlInfo->ulGrant->coresetCfg.precoderGranularity;
+ ulDciReqPdu->pdcchPduConfig.numDlDci = 1;
+ ulDciReqPdu->pdcchPduConfig.coreSetType = coreSetType;
+
+ /* Calculating PDU length. Considering only one Ul dci pdu for now */
+ ulDciReqPdu->pduSize = sizeof(fapi_dl_pdcch_pdu_t);
+ }
+ return ROK;
+}
+#endif
+/*******************************************************************
+ *
+ * @brief Sends UL DCI Request to PHY
+ *
+ * @details
+ *
+ * Function : fillUlDciReq
+ *
+ * Functionality:
+ * -Sends FAPI Ul Dci req to PHY
+ *
+ * @params[in] Pointer to CmLteTimingInfo
+ * @return ROK - success
+ * RFAILED - failure
+ *
+ ******************************************************************/
+uint16_t fillUlDciReq(SlotIndInfo currTimingInfo)
+{
+#ifdef INTEL_FAPI
+ uint8_t cellIdx =0;
+ uint8_t numPduEncoded = 0;
+ SlotIndInfo ulDciReqTimingInfo ={0};
+ MacDlSlot *currDlSlot = NULLP;
+ fapi_ul_dci_req_t *ulDciReq =NULLP;
+ fapi_msg_header_t *msgHeader =NULLP;
+ p_fapi_api_queue_elem_t ulDciElem;
+ p_fapi_api_queue_elem_t headerElem;
+
+ if(lwrMacCb.phyState == PHY_STATE_RUNNING)
+ {
+ GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
+ memcpy(&ulDciReqTimingInfo, &currTimingInfo, sizeof(SlotIndInfo));
+ currDlSlot = &macCb.macCell[cellIdx]->dlSlot[ulDciReqTimingInfo.slot % MAX_SLOT_SUPPORTED];
+
+ if(currDlSlot->dlInfo.ulGrant != NULLP)
+ {
+ LWR_MAC_ALLOC(ulDciElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_ul_dci_req_t)));
+ if(ulDciElem)
+ {
+ FILL_FAPI_LIST_ELEM(ulDciElem, NULLP, FAPI_UL_DCI_REQUEST, 1, \
+ sizeof(fapi_ul_dci_req_t));
+ ulDciReq = (fapi_ul_dci_req_t *)(ulDciElem +1);
+ memset(ulDciReq, 0, sizeof(fapi_ul_dci_req_t));
+ fillMsgHeader(&ulDciReq->header, FAPI_UL_DCI_REQUEST, sizeof(fapi_ul_dci_req_t));
+
+ ulDciReq->sfn = ulDciReqTimingInfo.sfn;
+ ulDciReq->slot = ulDciReqTimingInfo.slot;
+ ulDciReq->numPdus = 1; // No. of PDCCH PDUs
+ if(ulDciReq->numPdus > 0)
+ {
+ /* Fill PDCCH configuration Pdu */
+ fillUlDciPdcchPdu(&ulDciReq->pdus[numPduEncoded], &currDlSlot->dlInfo, CORESET_TYPE1);
+ numPduEncoded++;
+ /* free UL GRANT at SCH */
+ MAC_FREE(currDlSlot->dlInfo.ulGrant, sizeof(DciInfo));
+ currDlSlot->dlInfo.ulGrant = NULLP;
+
+ /* Fill message header */
+ LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
+ if(!headerElem)
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for UL DCI req header");
+ LWR_MAC_FREE(ulDciElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_ul_dci_req_t)));
+ return RFAILED;
+ }
+ FILL_FAPI_LIST_ELEM(headerElem, ulDciElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
+ sizeof(fapi_msg_header_t));
+ msgHeader = (fapi_msg_header_t *)(headerElem + 1);
+ msgHeader->num_msg = 1;
+ msgHeader->handle = 0;
+#ifdef ODU_SLOT_IND_DEBUG_LOG
+ DU_LOG("\nDEBUG --> LWR_MAC: Sending UL DCI Request");
+#endif
+ LwrMacSendToL1(headerElem);
+ }
+ }
+ else
+ {
+ DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for UL DCI Request");
+ memset(currDlSlot, 0, sizeof(MacDlSlot));
+ return RFAILED;
+ }
+ }
+ }
+ else
+ {
+ lwr_mac_procInvalidEvt(&currTimingInfo);
+ }
+#endif
+ return ROK;
+}
+
+lwrMacFsmHdlr fapiEvtHdlr[MAX_STATE][MAX_EVENT] =
+{
+ {
+ /* PHY_STATE_IDLE */
+#ifdef INTEL_TIMER_MODE
+ lwr_mac_procIqSamplesReqEvt,
+#endif
+ lwr_mac_procParamReqEvt,
+ lwr_mac_procParamRspEvt,
+ lwr_mac_procConfigReqEvt,
+ lwr_mac_procConfigRspEvt,
+ lwr_mac_procInvalidEvt,
+ lwr_mac_procInvalidEvt,
+ },
+ {
+ /* PHY_STATE_CONFIGURED */
+#ifdef INTEL_TIMER_MODE
+ lwr_mac_procInvalidEvt,
+#endif
+ lwr_mac_procParamReqEvt,
+ lwr_mac_procParamRspEvt,
+ lwr_mac_procConfigReqEvt,
+ lwr_mac_procConfigRspEvt,
+ lwr_mac_procStartReqEvt,
+ lwr_mac_procInvalidEvt,
+ },
+ {
+ /* PHY_STATE_RUNNING */
+#ifdef INTEL_TIMER_MODE
+ lwr_mac_procInvalidEvt,
+#endif
+ lwr_mac_procInvalidEvt,
+ lwr_mac_procInvalidEvt,
+ lwr_mac_procConfigReqEvt,
+ lwr_mac_procConfigRspEvt,
+ lwr_mac_procInvalidEvt,
+ lwr_mac_procStopReqEvt,
+ }
+};
+
+/*******************************************************************
+ *
+ * @brief Sends message to LWR_MAC Fsm Event Handler
+ *
+ * @details
+ *
+ * Function : sendToLowerMac
+ *
+ * Functionality:
+ * -Sends message to LowerMac
+ *
+ * @params[in] Message Type
+ * Message Length
+ * Messaga Pointer
+ *
+ * @return void
+ *
+ ******************************************************************/
+void sendToLowerMac(uint16_t msgType, uint32_t msgLen, void *msg)
+{
+ lwrMacCb.event = msgType;
+ fapiEvtHdlr[lwrMacCb.phyState][lwrMacCb.event](msg);
+}