+} /* fillSib1DlDciPdu */
+
+/*******************************************************************
+ *
+ * @brief fills Dl DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillRarDlDciPdu
+ *
+ * Functionality:
+ * -Fills the Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+
+void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes;
+ uint8_t bytePos;
+ uint8_t bitPos;
+
+ uint16_t coreset0Size;
+ uint16_t rbStart;
+ uint16_t rbLen;
+ uint32_t freqDomResAssign;
+ uint8_t timeDomResAssign;
+ uint8_t VRB2PRBMap;
+ uint8_t modNCodScheme;
+ uint8_t tbScaling;
+ uint32_t reserved;
+
+ /* Size(in bits) of each field in DCI format 1_0 */
+ uint8_t freqDomResAssignSize;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t tbScalingSize = 2;
+ uint8_t reservedSize = 16;
+
+ dlDciPtr->rnti = rarPdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = rarPdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = rarPdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = rarPdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = rarPdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->powerControlOfssetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+
+ /* TODO: Fill values of coreset0Size, rbStart and rbLen */
+ coreset0Size= rarPdcchInfo->coreset0Cfg.coreSet0Size;
+ rbStart = 0; /* For SIB1 */
+ //rbStart = rarPdcchInfo->dci.pdschCfg->freqAlloc.rbStart;
+ rbLen = rarPdcchInfo->dci.pdschCfg->freqAlloc.rbSize;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ timeDomResAssign = rarPdcchInfo->dci.pdschCfg->timeAlloc.rowIndex -1;
+ VRB2PRBMap = rarPdcchInfo->dci.pdschCfg->freqAlloc.vrbPrbMapping;
+ modNCodScheme = rarPdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
+ tbScaling = 0; /* configured to 0 scaling */
+ reserved = 0;
+
+ /* Reversing bits in each DCI field */
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ tbScaling = reverseBits(tbScaling, tbScalingSize);
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
+ + VRB2PRBMapSize + modNCodSchemeSize + tbScalingSize + reservedSize;
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nLWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ tbScaling, tbScalingSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ reserved, reservedSize);
+ }
+} /* fillRarDlDciPdu */
+
+/*******************************************************************
+ *
+ * @brief fills msg4 Dl DCI PDU required for DL TTI info in MAC
+ *
+ * @details
+ *
+ * Function : fillMsg4DlDciPdu
+ *
+ * Functionality:
+ * -Fills the Msg4 Dl DCI PDU
+ *
+ * @params[in] Pointer to fapi_dl_dci_t
+ * Pointer to PdcchCfg
+ * @return ROK
+ *
+ ******************************************************************/
+void fillMsg4DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *msg4PdcchInfo,\
+Msg4Info *msg4Info)
+{
+ if(dlDciPtr != NULLP)
+ {
+ uint8_t numBytes;
+ uint8_t bytePos;
+ uint8_t bitPos;
+
+ uint16_t coreset0Size = 0;
+ uint16_t rbStart = 0;
+ uint16_t rbLen = 0;
+ uint8_t dciFormatId;
+ uint32_t freqDomResAssign;
+ uint8_t timeDomResAssign;
+ uint8_t VRB2PRBMap;
+ uint8_t modNCodScheme;
+ uint8_t ndi = 0;
+ uint8_t redundancyVer = 0;
+ uint8_t harqProcessNum = 0;
+ uint8_t dlAssignmentIdx = 0;
+ uint8_t pucchTpc = 0;
+ uint8_t pucchResoInd = 0;
+ uint8_t harqFeedbackInd = 0;
+
+ /* Size(in bits) of each field in DCI format 1_0 */
+ uint8_t dciFormatIdSize = 1;
+ uint8_t freqDomResAssignSize;
+ uint8_t timeDomResAssignSize = 4;
+ uint8_t VRB2PRBMapSize = 1;
+ uint8_t modNCodSchemeSize = 5;
+ uint8_t ndiSize = 1;
+ uint8_t redundancyVerSize = 2;
+ uint8_t harqProcessNumSize = 4;
+ uint8_t dlAssignmentIdxSize = 2;
+ uint8_t pucchTpcSize = 2;
+ uint8_t pucchResoIndSize = 3;
+ uint8_t harqFeedbackIndSize = 3;
+
+ dlDciPtr->rnti = msg4PdcchInfo->dci.rnti;
+ dlDciPtr->scramblingId = msg4PdcchInfo->dci.scramblingId;
+ dlDciPtr->scramblingRnti = msg4PdcchInfo->dci.scramblingRnti;
+ dlDciPtr->cceIndex = msg4PdcchInfo->dci.cceIndex;
+ dlDciPtr->aggregationLevel = msg4PdcchInfo->dci.aggregLevel;
+ dlDciPtr->pc_and_bform.numPrgs = msg4PdcchInfo->dci.beamPdcchInfo.numPrgs;
+ dlDciPtr->pc_and_bform.prgSize = msg4PdcchInfo->dci.beamPdcchInfo.prgSize;
+ dlDciPtr->pc_and_bform.digBfInterfaces = msg4PdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = msg4PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
+ dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = msg4PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
+ dlDciPtr->beta_pdcch_1_0 = msg4PdcchInfo->dci.txPdcchPower.powerValue;
+ dlDciPtr->powerControlOfssetSS = msg4PdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
+
+ /* Calculating freq domain resource allocation field value and size
+ * coreset0Size = Size of coreset 0
+ * RBStart = Starting Virtual Rsource block
+ * RBLen = length of contiguously allocted RBs
+ * Spec 38.214 Sec 5.1.2.2.2
+ */
+
+ /* TODO: Fill values of coreset0Size, rbStart and rbLen */
+ coreset0Size = msg4PdcchInfo->coreset0Cfg.coreSet0Size;
+ //rbStart = msg4PdcchInfo->dci.pdschCfg->freqAlloc.rbStart;
+ rbLen = msg4PdcchInfo->dci.pdschCfg->freqAlloc.rbSize;
+
+ if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
+ {
+ if((rbLen - 1) <= floor(coreset0Size / 2))
+ freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
+ else
+ freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
+ + (coreset0Size - 1 - rbStart);
+
+ freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
+ }
+
+ /* Fetching DCI field values */
+ dciFormatId = msg4Info->dciFormatId; /* DCI indentifier for DL */
+ timeDomResAssign = msg4PdcchInfo->dci.pdschCfg->timeAlloc.rowIndex -1;
+ VRB2PRBMap = msg4PdcchInfo->dci.pdschCfg->freqAlloc.vrbPrbMapping;
+ modNCodScheme = msg4PdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
+ ndi = msg4Info->ndi;
+ redundancyVer = msg4PdcchInfo->dci.pdschCfg->codeword[0].rvIndex;
+ harqProcessNum = msg4Info->harqProcNum;
+ dlAssignmentIdx = msg4Info->dlAssignIdx;
+ pucchTpc = msg4Info->pucchTpc;
+ pucchResoInd = msg4Info->pucchResInd;
+ harqFeedbackInd = msg4Info->harqFeedbackInd;
+
+ /* Reversing bits in each DCI field */
+ dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
+ freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
+ timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
+ VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
+ modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
+ ndi = reverseBits(ndi, ndiSize);
+ redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
+ harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
+ dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize);
+ pucchTpc = reverseBits(pucchTpc, pucchTpcSize);
+ pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize);
+ harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize);
+
+
+ /* Calulating total number of bytes in buffer */
+ dlDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
+ + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
+ + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\
+ + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize);
+
+ numBytes = dlDciPtr->payloadSizeBits / 8;
+ if(dlDciPtr->payloadSizeBits % 8)
+ numBytes += 1;
+
+ if(numBytes > DCI_PAYLOAD_BYTE_LEN)
+ {
+ DU_LOG("\nLWR_MAC : Total bytes for DCI is more than expected");
+ return;
+ }
+
+ /* Initialize buffer */
+ for(bytePos = 0; bytePos < numBytes; bytePos++)
+ dlDciPtr->payload[bytePos] = 0;
+
+ bytePos = numBytes - 1;
+ bitPos = 0;
+
+ /* Packing DCI format fields */
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ dciFormatId, dciFormatIdSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ freqDomResAssign, freqDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ timeDomResAssign, timeDomResAssignSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ VRB2PRBMap, VRB2PRBMapSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ modNCodScheme, modNCodSchemeSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ ndi, ndiSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ redundancyVer, redundancyVerSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ harqProcessNum, harqProcessNumSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ dlAssignmentIdx, dlAssignmentIdxSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ pucchTpc, pucchTpcSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ pucchResoInd, pucchResoIndSize);
+ fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
+ harqFeedbackInd, harqFeedbackIndSize);
+ }
+} /* fillMsg4DlDciPdu */