#define NR_PCI 1
#define NR_CELL_ID 1
-#define DU_NAME "ORAN_OAM_DU"
+#define DU_NAME "ORAN OAM DU"
#define CELL_TYPE SMALL
//TODO: while testing for TDD, Mu1 and 100 MHz, this flag must be enabled
#define CORESET1_NUM_PRB 24
/* MACRO defines for PRACH Configuration */
+#ifndef NR_TDD
+#define PRACH_CONFIG_IDX 16
+#else
#define PRACH_CONFIG_IDX 88
+#endif
#define PRACH_MAX_PRB 24 /* As per (spec 38.211-Table 6.3.3.2-1), max allocated PRBs can go upto 24 */
#define PRACH_FREQ_START (MAX_NUM_RB - PRACH_MAX_PRB) /* In order to allocate PRACH from end of the resource grid */
#define PRACH_SEQ_LEN SHORT_SEQUENCE
#define SPARE 0
#define SSB_SC_OFFSET 0
#define DU_RANAC 1
-#define CELL_IDENTITY 16
+#define CELL_IDENTITY 1
/* Macro definitions for DUtoCuRrcContainer */
#define CELL_GRP_ID 0
#define DEDICATED_RATIO 10
#define NUM_OF_SUPPORTED_SLICE 2
+#ifdef NR_DRX
+/* Macros for Drx configuration */
+#define DRX_ONDURATION_TIMER_VALUE_PRESENT_IN_MS true
+#define DRX_ONDURATION_TIMER_VALUE_IN_SUBMS 32
+#define DRX_ONDURATION_TIMER_VALUE_IN_MS 10
+#define DRX_INACTIVITY_TIMER 2
+#define DRX_HARQ_RTT_TIMER_DL 56
+#define DRX_HARQ_RTT_TIMER_UL 56
+#define DRX_RETRANSMISSION_TIMER_DL 4
+#define DRX_RETRANSMISSION_TIMER_UL 4
+#define DRX_LONG_CYCLE_START_OFFSET_CHOICE 40
+#define DRX_LONG_CYCLE_START_OFFSET_VAL 8
+#define DRX_SHORT_CYCLE_PRESENT true
+#define DRX_SHORT_CYCLE 2
+#define DRX_SHORT_CYCLE_TIMER 2
+#define DRX_SLOT_OFFSET 0
+#endif
+
typedef enum
{
GNBDU,