#define SCH_MU3_NUM_SLOTS 40
#define SCH_MU4_NUM_SLOTS 50
#define SCH_MAX_SFN 1024
-#define MAX_NUM_RB 106 /* value for numerology 0 15Khz */
+#ifdef NR_TDD
+#define MAX_NUM_RB 275 /* value for numerology 1, 100 MHz */
+#else
+#define MAX_NUM_RB 106 /* value for numerology 0, 20 MHz */
+#endif
#define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
#define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
#define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
#define BO_DELTA 1
#define RAR_DELAY 2
#define MSG4_DELAY 1
+#define PDSCH_START_RB 10
#define PUSCH_START_RB 15
#define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
#define SI_RNTI 0xFFFF
#define P_RNTI 0xFFFE
#define DMRS_MAP_TYPE_A 1
-#define NUM_DMRS_SYMBOLS 12
-#define DMRS_ADDITIONAL_POS 2
+#define NUM_DMRS_SYMBOLS 1
+#define DMRS_ADDITIONAL_POS 0
#define SCH_DEFAULT_K1 1
#define SCH_TQ_SIZE 10
SchDlCb dlInfo;
}SchUeCb;
+/**
+ * @brief
+ * RA Request Info
+ */
+typedef struct schRaReq
+{
+ uint32_t raRnti;
+ RachIndInfo *rachInd;
+ SlotTimingInfo winStartTime;
+ SlotTimingInfo winEndTime;
+}SchRaReq;
+
/**
* @brief
* Cell Control block per cell.
Inst instIdx; /*!< Index of the scheduler instance */
Inst macInst; /*!< Index of the MAC instance */
uint8_t numSlots; /*!< Number of slots in current frame */
- SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/
+ SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
SchCellCfg cellCfg; /*!< Cell ocnfiguration */
bool firstSsbTransmitted;
bool firstSib1Transmitted;
uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
- SchRaCb raCb[MAX_NUM_UE]; /*!< Rach Cb */
+ SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
+ SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
uint16_t numActvUe; /*!<Number of active UEs */
uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
SchCb schCb[SCH_MAX_INST];
/* function declarations */
+SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
+void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
+void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
+uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
short int schActvTmr(Ent ent,Inst inst);
uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,uint16_t slot);
-uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst inst);
+uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
-uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot);
+uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot, bool ssbPresent, bool sib1Present);
uint16_t schCalcTbSize(uint32_t payLoadSize);
uint16_t schCalcNumPrb(uint16_t tbSize, uint16_t mcs, uint8_t numSymbols);
uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
uint32_t *accumalatedSize, uint16_t slot);
uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
-
+uint8_t schFillRar(RarAlloc *rarAlloc, uint16_t raRnti, uint16_t pci, uint8_t offsetPointA, bool ssbPresent, bool sib1Present);
+void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, SchPdschCfgCmn pdschCmnCfg,\
+SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
+void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
/**********************************************************************
End of file
**********************************************************************/