# See the License for the specific language governing permissions and #
# limitations under the License. #
################################################################################
-*******************************************************************************/
+ *******************************************************************************/
/* macros */
#define SCH_INST_START 1
-#define SCH_MAX_CELLS 1
#define SCH_MAX_INST 1
-#define SCH_NUM_SLOTS 10 /*forcing this to 10 */
+#define SCH_MU0_NUM_SLOTS 10
+#define SCH_MU1_NUM_SLOTS 20
+#define SCH_MU2_NUM_SLOTS 30
+#define SCH_MU3_NUM_SLOTS 40
+#define SCH_MU4_NUM_SLOTS 50
#define SCH_MAX_SFN 1024
-#define MAX_NUM_RB 106 /* value for numerology 0 15Khz */
-#define SCH_MIB_TRANS 80
+#define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
+#define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
#define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
-#define SCH_SCS_15KHZ 0 /* numerology 0 and 15Khz */
-#define SCH_SYMBOL_PER_SLOT 14
+#define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
#define SCH_SSB_NUM_SYMB 4
-#define SCH_SSB_NUM_PRB 20
-#define SCH_MAX_SSB_BEAM 4 /* since we are supporting only SCS=15KHz */
-#define SCH_MEM_REGION 4
-#define SCH_POOL 1
+#define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
#define SCHED_DELTA 1
#define BO_DELTA 1
#define RAR_DELAY 2
#define MSG4_DELAY 1
-#define SCH_MAX_UE 1
+#define PDSCH_START_RB 10
+/* Considering pdsch region from 3 to 13, DMRS exclued.
+ * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
+#define NUM_PDSCH_SYMBOL 11
#define PUSCH_START_RB 15
+#define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
#define SI_RNTI 0xFFFF
#define P_RNTI 0xFFFE
+#define DMRS_MAP_TYPE_A 1
+#define NUM_DMRS_SYMBOLS 1
+#define DMRS_ADDITIONAL_POS 0
+#define SCH_DEFAULT_K1 1
+#define SCH_TQ_SIZE 10
+#define SSB_IDX_SUPPORTED 1
#define CRC_FAILED 0
#define CRC_PASSED 1
-/* allocate and zero out a static buffer */
-#define SCH_ALLOC(_datPtr, _size) \
-{ \
- S16 _ret; \
- _ret = SGetSBuf(SCH_MEM_REGION, SCH_POOL, \
- (Data **)&_datPtr, _size); \
- if(_ret == ROK) \
- cmMemset((U8*)_datPtr, 0, _size); \
- else \
- _datPtr = NULLP; \
-}
-
-/* free a static buffer */
-#define SCH_FREE(_datPtr, _size) \
- if(_datPtr) \
- SPutSBuf(SCH_MEM_REGION, SCH_POOL, \
- (Data *)_datPtr, _size);
-
-#define SCH_FILL_RSP_PST(_rspPst, _inst)\
-{ \
- _rspPst.srcProcId = SFndProcId(); \
- _rspPst.dstProcId = SFndProcId();\
- _rspPst.srcEnt = ENTRG;\
- _rspPst.dstEnt = ENTRG;\
- _rspPst.srcInst = 1;\
- _rspPst.dstInst = 0;\
- _rspPst.selector = MAC_SELECTOR_TC;\
-}
-extern uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
+#define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
+#define UL_GRANT_SIZE 224
+
+#define PRB_BITMAP_IDX_LEN 64
+#define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
+
+typedef struct schCellCb SchCellCb;
+typedef struct schUeCb SchUeCb;
+
+typedef enum
+{
+ SCH_NUMEROLOGY_0,
+ SCH_NUMEROLOGY_1,
+ SCH_NUMEROLOGY_2,
+ SCH_NUMEROLOGY_3,
+ SCH_NUMEROLOGY_4
+}SchNumerology;
+
+typedef enum
+{
+ SCH_UE_STATE_INACTIVE,
+ SCH_UE_STATE_ACTIVE
+}SchUeState;
+
+typedef enum
+{
+ SCH_LC_STATE_INACTIVE,
+ SCH_LC_STATE_ACTIVE
+}SchLcState;
+
+typedef enum
+{
+ WINDOW_YET_TO_START,
+ WITHIN_WINDOW,
+ WINDOW_EXPIRED
+}RaRspWindowStatus;
+
/**
- * @brief
- * Structure holding LTE MAC's General Configuration information.
- */
+ * @brief
+ * Structure holding LTE MAC's General Configuration information.
+ */
typedef struct schGenCb
{
uint8_t tmrRes; /*!< Timer resolution */
uint8_t startCellId; /*!< Starting Cell Id */
#ifdef LTE_ADV
bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
- of RLC control BO and SRB BO on
- PCell. val 0 means don't force*/
+ of RLC control BO and SRB BO on
+ PCell. val 0 means don't force*/
bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
#endif
}SchGenCb;
+typedef struct freePrbBlock
+{
+ uint16_t numFreePrb;
+ uint16_t startPrb;
+ uint16_t endPrb;
+}FreePrbBlock;
+
+/**
+ * @brief
+ * PRB allocations for a symbol within a slot
+ */
+typedef struct schPrbAlloc
+{
+ CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
+ uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
+}SchPrbAlloc;
+
/**
- * @brief
- * scheduler allocationsfor DL per cell.
- */
+ * @brief
+ * scheduler allocationsfor DL per cell.
+ */
typedef struct schDlSlotInfo
{
- uint16_t totalPrb; /*!< Number of RBs in the cell */
- uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
- bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
- uint8_t ssbIdxSupported; /*!< Max SSB index */
- SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
- bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
- RarInfo *rarInfo; /*!< RAR info */
- Msg4Info *msg4Info; /*!< msg4 info */
+ SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
+ bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
+ uint8_t ssbIdxSupported; /*!< Max SSB index */
+ SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
+ bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
+ RarAlloc *rarAlloc; /*!< RAR allocation */
+ DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
}SchDlSlotInfo;
typedef struct schRaCb
}SchRaCb;
/**
- * @brief
- * scheduler allocationsfor UL per cell.
- */
+ * @brief
+ * scheduler allocationsfor UL per cell.
+ */
typedef struct schUlSlotInfo
{
- uint16_t totalPrb; /*!< Number of RBs in the cell */
- uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
- bool puschPres; /*!< PUSCH presence field */
- SchPuschInfo *schPuschInfo; /*!< PUSCH info */
+ SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
+ uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
+ bool puschPres; /*!< PUSCH presence field */
+ SchPuschInfo *schPuschInfo; /*!< PUSCH info */
+ bool pucchPres; /*!< PUCCH presence field */
+ SchPucchInfo schPucchInfo; /*!< PUCCH info */
}SchUlSlotInfo;
/**
- * @brief
- * Cell Control block per cell.
- */
+@brief
+* BSR info per slot per UE.
+*/
+typedef struct bsrInfo
+{
+ uint8_t priority; /* CG priority */
+ uint32_t dataVol; /* Data volume requested in bytes */
+}BsrInfo;
+
+typedef struct schLcCtxt
+{
+ uint8_t lcId; // logical Channel ID
+ uint8_t lcp; // logical Channel Prioritization
+ SchLcState lcState;
+ uint32_t bo;
+ uint16_t pduSessionId; /*Pdu Session Id*/
+ Snssai *snssai; /*S-NSSAI assoc with LCID*/
+}SchDlLcCtxt;
+
+typedef struct schDlCb
+{
+ uint8_t numDlLc;
+ SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
+}SchDlCb;
+
+typedef struct schUlLcCtxt
+{
+ SchLcState lcState;
+ uint8_t lcId;
+ uint8_t priority;
+ uint8_t lcGroup;
+ uint8_t schReqId;
+ uint8_t pbr; // prioritisedBitRate
+ uint8_t bsd; // bucketSizeDuration
+ uint16_t pduSessionId; /*Pdu Session Id*/
+ Snssai *snssai; /*S-NSSAI assoc with LCID*/
+}SchUlLcCtxt;
+
+typedef struct schUlCb
+{
+ uint8_t numUlLc;
+ SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
+}SchUlCb;
+
+typedef struct schUeCfgCb
+{
+ uint16_t cellId;
+ uint16_t crnti;
+ bool macCellGrpCfgPres;
+ SchMacCellGrpCfg macCellGrpCfg;
+ bool phyCellGrpCfgPres;
+ SchPhyCellGrpCfg phyCellGrpCfg;
+ bool spCellCfgPres;
+ SchSpCellCfg spCellCfg;
+ SchAmbrCfg *ambrCfg;
+ SchModulationInfo dlModInfo;
+ SchModulationInfo ulModInfo;
+}SchUeCfgCb;
+
+/**
+ * @brief
+ * UE control block
+ */
+typedef struct schUeCb
+{
+ uint16_t ueIdx;
+ uint16_t crnti;
+ SchUeCfgCb ueCfg;
+ SchUeState state;
+ SchCellCb *cellCb;
+ bool srRcvd;
+ BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
+ SchUlCb ulInfo;
+ SchDlCb dlInfo;
+}SchUeCb;
+
+/**
+ * @brief
+ * RA Request Info
+ */
+typedef struct schRaReq
+{
+ uint32_t raRnti;
+ RachIndInfo *rachInd;
+ SlotTimingInfo winStartTime;
+ SlotTimingInfo winEndTime;
+}SchRaReq;
+
+/**
+ * @brief
+ * Cell Control block per cell.
+ */
typedef struct schCellCb
{
uint16_t cellId; /*!< Cell ID */
Inst instIdx; /*!< Index of the scheduler instance */
Inst macInst; /*!< Index of the MAC instance */
- uint8_t numSlots; /*!< Number of slots in current frame */
- SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/
- SchDlSlotInfo *schDlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in DL */
- SchUlSlotInfo *schUlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in UL */
- SchCellCfg cellCfg; /*!< Cell ocnfiguration */
- uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
- SchRaCb raCb[SCH_MAX_UE]; /*!< Rach Cb */
+ uint8_t numSlots; /*!< Number of slots in current frame */
+ SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
+ SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
+ SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
+ SchCellCfg cellCfg; /*!< Cell ocnfiguration */
+ bool firstSsbTransmitted;
+ bool firstSib1Transmitted;
+ uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
+ SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
+ SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
+ uint16_t numActvUe; /*!<Number of active UEs */
+ uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
+ uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
+ SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
+#ifdef NR_TDD
+ uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
+ uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
+ uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
+#endif
}SchCellCb;
/**
- * @brief
- * Control block for sch
- */
+ * @brief
+ * Control block for sch
+ */
typedef struct schCb
{
- TskInit schInit; /*!< Task Init info */
- SchGenCb genCfg; /*!< General Config info */
- SchCellCb *cells[SCH_MAX_CELLS]; /* Array to store cellCb ptr */
+ TskInit schInit; /*!< Task Init info */
+ SchGenCb genCfg; /*!< General Config info */
+ CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
+ CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
+ SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
}SchCb;
/* Declaration for scheduler control blocks */
SchCb schCb[SCH_MAX_INST];
/* function declarations */
-uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,uint16_t slot);
-uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst inst);
-uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
-uint8_t schDlRsrcAllocMsg4(Msg4Alloc *msg4Alloc, SchCellCb *cell, uint16_t slot);
+short int schActvTmr(Ent ent,Inst inst);
+
+/* Configuration related function declarations */
+void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
+void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
+void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
+ SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
+void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
+ uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
+uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
+SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
+
+/* Incoming message handler function declarations */
+uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
+uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
+/* DL scheduling related function declarations */
+PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
+PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
+uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
+uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
+void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
+uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueIdx, RarAlloc *rarAlloc, uint8_t k0Index);
+uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo slotTime, DlMsgAlloc *msg4Alloc);
+uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
+ uint32_t *accumalatedSize, DlMsgAlloc *dlMsgAlloc);
+uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
+uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
+ uint16_t *startPrb, uint16_t numPrb);
+
+/* UL scheduling related function declarations */
+uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
+bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
+uint8_t schCalcPrachNumRb(SchCellCb *cell);
+void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
+uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
+uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
+uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo pdcchSlotTime, uint32_t dataVol, SchPuschInfo *puschInfo);
+uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
+ uint16_t *startPrb, uint16_t numPrb);
/**********************************************************************
- End of file
-**********************************************************************/
+ End of file
+ **********************************************************************/