/*******************************************************************************
################################################################################
# Copyright (c) [2017-2019] [Radisys] #
# #
# Licensed under the Apache License, Version 2.0 (the "License"); #
# you may not use this file except in compliance with the License. #
# You may obtain a copy of the License at #
# #
# http://www.apache.org/licenses/LICENSE-2.0 #
# #
# Unless required by applicable law or agreed to in writing, software #
# distributed under the License is distributed on an "AS IS" BASIS, #
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
# See the License for the specific language governing permissions and #
# limitations under the License. #
################################################################################
*******************************************************************************/
/**********************************************************************
Name: LTE MAC layer
Type: C include file
Desc: Defines required by LTE MAC
File: rg_sch.x
**********************************************************************/
/** @file rg_sch.x
@brief This file contains basic data structures for the scheuler.
*/
#ifdef TENB_STATS
#include "pj_tenb_stats.x"
#endif
#ifndef __SCH__
#define __SCH__
#ifdef TENB_STATS
#include "l2_tenb_stats.x"
#endif
#ifdef EMTC_ENABLE
#include "rg_sch_emtc.x"
#endif
typedef struct rgSchHistNode
{
uint32_t line;
S8* file;
const S8* func;
Void * dbgVal; /* This is specific to the data struct being debug
for example if the debugging is done fo list
then this should contain the node address */
uint32_t action;
}RgSchHistNode;
#define MAX_HIST_NODES 50
#define RGSCH_ACTION_ADD 11
#define RGSCH_ACTION_DEL 12
typedef struct rgSchHistInfo
{
uint32_t histCount;
RgSchHistNode hist[MAX_HIST_NODES];
}RgSchHistInfo;
#define RG_SCH_RECORD(_histInfo,_action,_dbgVal)\
{\
(_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].file = __FILE__;\
(_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].func = __FUNCTION__;\
(_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].line = __LINE__;\
(_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].action = _action;\
(_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].dbgVal = _dbgVal;\
(_histInfo)->histCount++;\
}
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
typedef TfuDciFormat1aInfo RgDciFmt1AInfo;
typedef TfuRaReqInfo RgTfuRaReqInfo;
typedef TfuSubbandCqiInfo RgSchSubbandCqiInfo;
typedef TfuHqIndInfo RgTfuHqIndInfo;
typedef TfuHqInfo RgTfuHqInfo;
typedef TfuCntrlReqInfo RgTfuCntrlReqInfo;
/* Forward declarations for some structures */
#ifdef LTE_L2_MEAS
typedef struct rgSchL2MeasCb RgSchL2MeasCb;
#endif /* LTE_L2_MEAS */
typedef struct rgSchQciCb RgSchQciCb;
typedef struct rgSchUeCb RgSchUeCb;
typedef struct rgSchCellCb RgSchCellCb;
typedef struct rgSchErrInfo RgSchErrInfo;
typedef struct rgSchUlAlloc RgSchUlAlloc;
typedef struct rgSchUlRetxAlloc RgSchUlRetxAlloc;
typedef struct rgSchUlHqProcCb RgSchUlHqProcCb;
typedef struct rgSchDlHqProcCb RgSchDlHqProcCb;
/* Changes for MIMO feature addition */
/* Removed dependency on MIMO compile-time flag */
typedef struct rgSchDlHqTbCb RgSchDlHqTbCb;
typedef struct rgSchLcgCb RgSchLcgCb;
typedef struct rgSchDlHqEnt RgSchDlHqEnt;
typedef struct rgSchRaCb RgSchRaCb;
typedef struct _rgSchCb RgSchCb;
typedef struct rgSchUlLcCb RgSchUlLcCb;
typedef struct rgSchDlLcCb RgSchDlLcCb;
typedef struct _rgSchdApis RgSchdApis;
#ifdef LTE_TDD
typedef struct rgSchTddPhichOffInfo RgSchTddPhichOffInfo;
typedef uint8_t RgSchTddNpValTbl[RGSCH_TDD_MAX_P_PLUS_ONE_VAL];
#endif
/* Added support for SPS*/
#ifdef LTEMAC_SPS
typedef struct rgSchDlSfAllocInfo RgSchDlSfAllocInfo;
#endif
typedef struct rgSchUeCellInfo RgSchUeCellInfo;
/**
* @brief
* Scheduler APIs
*/
struct _rgSchdApis
{
S16 (*rgSCHRgrUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeCfg *cfg,
RgSchErrInfo *err));
S16 (*rgSCHRgrUeRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg *recfg,
RgSchErrInfo *err));
Void (*rgSCHFreeUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
S16 (*rgSCHRgrCellCfg) ARGS((RgSchCellCb *cell, RgrCellCfg *cfg,
RgSchErrInfo *err));
S16 (*rgSCHRgrCellRecfg) ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
RgSchErrInfo *err));
Void (*rgSCHFreeCell) ARGS((RgSchCellCb *cell));
S16 (*rgSCHRgrLchCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchDlLcCb *dl, RgrLchCfg *cfg, RgSchErrInfo *errInfo));
S16 (*rgSCHRgrLcgCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchLcgCb *lcg, RgrLcgCfg *cfg, RgSchErrInfo *errInfo));
S16 (*rgSCHRgrLchRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchDlLcCb *dl, RgrLchRecfg *recfg,
RgSchErrInfo *errInfo));
S16 (*rgSCHRgrLcgRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchLcgCb *lcg, RgrLcgRecfg *recfg, RgSchErrInfo *errInfo));
Void (*rgSCHFreeDlLc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *dlLc));
Void (*rgSCHFreeLcg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *lcg));
S16 (*rgSCHRgrLchDel) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,CmLteLcId lcId, \
uint8_t lcgId));
Void (*rgSCHActvtUlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
Void (*rgSCHActvtDlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
Void (*rgSCHHdlUlTransInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
CmLteTimingInfo timingInfo));
Void (*rgSCHUeReset) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
S16 (*rgSCHUpdBsrShort) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, uint8_t bsr, RgSchErrInfo *err));
S16 (*rgSCHUpdBsrTrunc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, uint8_t bsr, RgSchErrInfo *err));
S16 (*rgSCHUpdBsrLong) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t bsArr[], RgSchErrInfo *err));
S16 (*rgSCHUpdPhr) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t phr, RgSchErrInfo *err));
S16 (*rgSCHUpdExtPhr) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgInfExtPhrCEInfo * extPhr, RgSchErrInfo *err));
#ifdef RG_UNUSED
S16 (*rgSCHUpdUlHqProc) ARGS((RgSchCellCb *cell, RgSchUlHqProcCb *curProc,
RgSchUlHqProcCb *oldProc));
#endif
S16 (*rgSCHContResUlGrant) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchErrInfo *err));
S16 (*rgSCHSrRcvd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, CmLteTimingInfo, RgSchErrInfo *err));
S16 (*rgSCHTti) ARGS((RgSchCellCb *cell, RgSchErrInfo *err));
Void (*rgSCHUlCqiInd) ARGS(( RgSchCellCb *cell, RgSchUeCb *ue, TfuUlCqiRpt *ulCqiInfo));
Void (*rgSCHPucchDeltaPwrInd) ARGS(( RgSchCellCb *cell,
RgSchUeCb *ue, S8 delta));
S16 (*rgSCHlUeReset) ARGS(( RgSchCellCb *cell, RgSchUeCb *ue));
Void (*rgSCHDlDedBoUpd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *svc));
/* ccpu00105914: PHR handling for MSG3 */
Void (*rgSCHUlRecMsg3Alloc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchRaCb *raCb));
Void (*rgSCHUlHqProcForUe) ARGS((RgSchCellCb *cell, CmLteTimingInfo frm,
RgSchUeCb *ue, RgSchUlHqProcCb **procRef));
RgSchUlAlloc *(*rgSCHFirstRcptnReq) ARGS((RgSchCellCb *cell));
RgSchUlAlloc *(*rgSCHNextRcptnReq) ARGS((RgSchCellCb *cell,
RgSchUlAlloc *alloc));
RgSchUlAlloc *(*rgSCHFirstHqFdbkAlloc) ARGS((RgSchCellCb *cell, uint8_t idx));
RgSchUlAlloc *(*rgSCHNextHqFdbkAlloc) ARGS((RgSchCellCb *cell,
RgSchUlAlloc *alloc,uint8_t idx));
Void (*rgSCHDlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchDlHqProcCb *hqP));
Void (*rgSCHDlCqiInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
Bool isPucchInfo, Void *dlCqi, CmLteTimingInfo timingInfo));
/* Added changes of TFU_UPGRADE */
#ifdef TFU_UPGRADE
Void (*rgSCHSrsInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
TfuSrsRpt* srsInd, CmLteTimingInfo timingInfo));
#endif
Void (*rgSCHDlTARpt) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
/* Changes for MIMO feature addition */
/* Removed dependency on MIMO compile-time flag */
Void (*rgSCHDlRlsSubFrm) ARGS((RgSchCellCb *cell, CmLteTimingInfo subFrm));
/* Added support for SPS*/
#ifdef LTEMAC_SPS
Void (*rgSCHHdlCrntiCE) ARGS((RgSchCellCb *cell, RgSchUeCb * ue));
Void (*rgSCHDlProcAck) ARGS((RgSchCellCb *cell, RgSchDlHqProcCb *hqP));
Void (*rgSCHDlProcDtx) ARGS((RgSchCellCb *cell, RgSchDlHqProcCb *hqP));
Void (*rgSCHDlRelPdcchFbk) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
uint8_t isAck));
Void (*rgSCHUlSpsRelInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
Bool isExplRel));
Void (*rgSCHUlSpsActInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
uint16_t sduSuze));
Void (*rgSCHUlCrcFailInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
CmLteTimingInfo crcTime));
Void (*rgSCHUlCrcInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
CmLteTimingInfo crcTime));
#endif /* LTEMAC_SPS */
Void (*rgSCHDrxStrtInActvTmrInUl) ARGS((RgSchCellCb *cell));
Void (*rgSCHUpdUeDataIndLcg) ARGS((RgSchCellCb *cell, RgSchUeCb * ue, RgInfUeDatInd *datInd));
#ifdef LTE_ADV
S16 (*rgSCHRgrSCellUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue ,RgrUeSecCellCfg *sCellInfoCfg,
RgSchErrInfo *err));
S16 (*rgSCHRgrSCellUeDel) ARGS((RgSchUeCellInfo *sCellInfo, RgSchUeCb *ue));
#endif
#ifdef EMTC_ENABLE
Void (*rgSCHUlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchUlHqProcCb *hqP));
#endif
};
/* Added changes of TFU_UPGRADE */
#ifdef TFU_UPGRADE
/**
* @brief Periodic CQI/PMI/RI configuration parameters information
*/
typedef RgrUePrdDlCqiCfg RgSchUeDlPCqiCfg;
/**
* @brief Periodic CQI Setup configuration parameters information
*/
/* Reference: 36.313: CQI-ReportPeriodic */
typedef RgrUeDlPCqiSetup RgSchUeDlPCqiSetup;
/**
* @brief SRS configuration parameters information
*/
/* Reference 36.313 SoundingRS-UL-Config */
typedef RgrUeUlSrsCfg RgSchUeUlSrsCfg;
/**
* @brief SRS configuration setup parameters information
*/
/* Reference 36.313 SoundingRS-UL-Config */
typedef RgrUeUlSrsSetupCfg RgSchUeSrsUlSetupCfg;
/**
* @brief SR configuration parameters information
*/
typedef RgrUeSrCfg RgSchUeSrCfg;
/**
* @brief SR Setup configuration parameters information
*/
typedef RgrUeSrSetupCfg RgSchUeSrSetupCfg;
#define IOT_INVALID_FREQSTART 0xffffffff
#define IOT_INFINITE_SIZE 0xffffffff
#define RGSCH_IOT_PDCCH_POOLSZ 100
#define RGSCH_IOT_PDSCH_POOLSZ 100
#define RGSCH_IOT_PUSCH_POOLSZ 100
#define RGSCH_IOT_PUCCH_POOLSZ 100
#define RGSCH_IOT_SCHED_POOLSZ 100
/* TODO: Minimum Delta between CRNT Time and TX time */
#define RGSCH_IOT_PDCCH_DELTA RG_SCH_CMN_DL_DELTA
#define RGSCH_IOT_PDSCH_DELTA RG_SCH_CMN_DL_DELTA - 1 /* UL_CNTRL_DELTA value is 2*/
#define RGSCH_IOT_PUCCH_DELTA 6
#define RGSCH_IOT_PUSCH_DELTA 6
#define RGSCH_IOT_PDCCH_MAXFREQSZ 24 /* MAX num of eCCEs per SF */
#define RGSCH_IOT_PDSCH_MAXFREQSZ 100 /* MAX num of PDSCH RB per SF */
#define RGSCH_IOT_PUCCH_MAXFREQSZ 2048 /* MAx num of PUCCH resource per SF */
#define RGSCH_IOT_PUSCH_MAXFREQSZ 100 /* MAx num of PUSCh RB per SF */
#define RGSCH_IOT_SCHED_MAXFREQSZ 1 /*Resource only in Time domain */
#define RGSCH_IOT_PUCCH_INVALID_FREQ 2049
/**
* @brief
* IoT PDCCH/PDSCH/PUSCH/PUCCH resource definition.
* For Iot Devices resource can span multiple subframes
* Hence resource is defined as a set of freq resources
* over a set of consecutive valid subframes
*/
typedef struct rgSchIotRes
{
uint32_t resType;
PTR allctdBy;
CmLteTimingInfo timeStart;
CmLteTimingInfo timeEnd;
uint32_t tSize;
uint8_t freqStart;
uint8_t freqEnd;
uint32_t fSize;
CmLList lnk; /*!< Link to other Fragments or Allocs in resMngmt */
CmLList cbLnk; /*!< Link to other allocs in a given control block (ueCb) */
CmLList resLnk;/*! 1*/
uint32_t aCqiTrigWt; /* Metric to track Aperiodic CQI Trigger occassion */
RgSchCqiReqField cqiReqField; /* Cqi Request field. This Value can be 00 01 10 11, based upon
the cell present in which trigger list form App */
}RgSchUeACqiCb;
typedef enum
{
RG_SCH_FDD_PCQI_TBL = 0,
RG_SCH_TDD_PCQI_TBL,
RG_SCH_RI_TBL,
RG_SCH_FDD_SRS_TBL,
RG_SCH_TDD_SRS_TBL,
RG_SCH_SR_TBL
} RgSchPerTbl;
/*ccpu00116923 - ADD - SRS present support*/
#ifdef LTE_TDD
typedef uint8_t RgSchTddCellSpSrsSubfrmTbl[RGSCH_CELLSP_SRS_SF_CONFIGS][RGSCH_NUM_SUB_FRAMES];
#else
typedef uint8_t RgSchFddCellSpSrsSubfrmTbl[RGSCH_CELLSP_SRS_SF_CONFIGS][RGSCH_NUM_SUB_FRAMES];
#endif
#endif
#ifdef LTE_TDD
/**
* @brief
* Enum to define the type of Downlink subframe.
*/
typedef enum
{
RG_SCH_SPL_SF_NO_DATA = 0,
RG_SCH_SPL_SF_DATA,
RG_SCH_DL_SF_0,
RG_SCH_DL_SF
}RgSchTddSfType;
/**
* @brief
* TDD UE specific PUCCH recpetion information.
*/
typedef struct rgSchUePucchRecpInfo
{
CmHashListEnt hashLstEnt; /*!< List of PUCCH for receiving
ACK/NACK feedback information */
TfuUeRecpReqInfo *pucchRecpInfo; /*!< UE PUCCH Reception information */
} RgSchUePucchRecpInfo;
/**
* @brief
* TDD switch point information.
*/
typedef struct rgSchTddSubfrmInfo
{
uint8_t switchPoints; /*!< Number of DL-UL switch points */
uint8_t numFrmHf1; /*!< Number of subframes for half frame 1
Present for both 5ms and 10ms periodicity */
uint8_t numFrmHf2; /*!< Number of subframes for half frame 2
Present only for 5ms periodicity */
} RgSchTddSubfrmInfo;
/**
* @brief
* TDD DL Association Set information.
*/
typedef struct rgSchTddDlAscSetIdxK
{
uint8_t numFdbkSubfrms; /*!< Number of Feedbacks for DL Subframes */
uint8_t subfrmNum[RGSCH_NUM_SUB_FRAMES-1]; /*!< List of Subframe Number */
} RgSchTddDlAscSetIdxK;
/** @brief PRACH Information for a frequency resource. */
typedef struct rgrSchTddPrachInfo
{
uint8_t freqIdx; /*!< Frequency Index */
uint8_t sfn; /*!< Even/Odd/All Radio Frames */
uint8_t halfFrm; /*!< First/Second Half Frame */
uint8_t ulStartSfIdx; /*!< Uplink Start Subframe Index*/
} RgSchTddPrachInfo;
/** @brief PRACH resource Information for each of the
* frequency resources. */
typedef struct rgrSchTddPrachRscInfo
{
uint8_t numRsc; /*!< Number of frequency resources*/
RgSchTddPrachInfo prachInfo[RGSCH_TDD_MAX_FREQ_RSRC]; /*!< PRACH Information */
} RgSchTddPrachRscInfo;
/**
* @brief
* TDD Special subframe configuration information.
*/
struct rgSchTddSplSubfrmInfo
{
uint8_t norDlDwPts; /*!< DL Normal CP: DwPTS in Ts */
uint8_t norDlNorUpPts; /*!< DL Normal CP: UL Normal CP:UpPTS in Ts */
uint8_t norDlExtUpPts; /*!< DL Normal CP: UL Extended CP: UpPTS in Ts */
uint8_t extDlDwPts; /*!< DL Extended CP: DwPTS in Ts */
uint8_t extDlNorUpPts; /*!< DL Extended CP: UL Normal CP:UpPTS in Ts */
uint8_t extDlExtUpPts; /*!< DL Extended CP: UL Extended CP: UpPTS in Ts */
};
/**
* @brief
* RACH response awaiting scheduling from the current time is
* identified with sfn offset and subframe.
*/
typedef struct rgSchTddRachRspInfo
{
uint8_t sfnOffset; /*!< SFN offset with respect to
expected RACH available for
scheduling */
uint8_t numSubfrms; /* Number of subframes present */
uint8_t subframe[RGSCH_NUM_SUB_FRAMES]; /*!< List of Subframe numbers */
} RgSchTddRachRspInfo;
typedef RgSchTddRachRspInfo RgSchTddRachDelInfo;
/**
* @brief
* List of awaiting RACH responses for scheduling across radio frames.
*
*/
typedef struct rgSchTddRachRspLst
{
uint8_t numRadiofrms; /*!< Number of radio frames */
RgSchTddRachRspInfo rachRsp[2]; /*!< RACH Occasions for which response
can be sent */
RgSchTddRachDelInfo delInfo; /*!< Previous RACH responses for
which the scheduling deadline
has expired. So those responses
can be deleted */
} RgSchTddRachRspLst;
/**
* @brief
* Uplink association index information indicates the SFN offset and
* subframe in which DL HARQ ACK/NACK is expected.
*/
typedef struct rgSchTddUlAscInfo
{
uint8_t subframe; /*!< Subframe number */
uint8_t sfnOffset; /*!< SFN offset with respect to expected
UL data reception time */
} RgSchTddUlAscInfo;
/**
* @brief
* PUSCH information indicates the SFN offset and
* subframe in which UL data is scheduled.
*/
typedef struct rgSchTddPuschOffInfo
{
uint8_t subframe; /*!< Subframe number */
uint8_t sfnOffset; /*!< SFN offset with respect to expected
UL data reception time */
} RgSchTddPuschOffInfo;
/**
* @brief
* PHICH information indicates the SFN offset and
* subframe for which PHICH should be sent.
*/
struct rgSchTddPhichOffInfo
{
uint8_t numSubfrms; /*!< Number of subframes */
/* ACC-TDD */
uint8_t subframe; /*!< The Uplink Subframe number corresponding
to the phich */
uint8_t sfnOffset; /*!< SFN offset with respect to expected
UL data reception time */
};
/**
* @brief
* DL feedback reception information indicates the SFN offset
* and subframe at which feedback is expected.
*/
typedef struct rgSchTddDlFdbkInfo
{
uint8_t subframe; /*!< Subframe number */
uint8_t sfnOffset; /*!< SFN offset with respect to current
scheduled time */
uint8_t m; /*!< m factor used in Downlink Association
Set Index */
#ifdef LTE_ADV /*Naw:: This is not correct */
CmLListCp n1PucchResLst; /*!< List for storing the used N1 resource */
#endif
} RgSchTddDlFdbkInfo;
/**
* @brief
* Special subframe configuration index.
*/
typedef struct rgSchTddSplSubfrmCfg
{
uint16_t dwPts; /*!< DwPTS in OFDM Symbol Duration */
uint16_t upPts; /*!< UpPTS in OFDM Symbol Duration */
Bool isDlDataAllowed; /*!< To allow scheduling of DL data on
special subframe */
} RgSchTddSplSubfrmCfg;
/**
* @brief
* ACK/NACK information to be used for ACK/NACK bundling mode.
*/
typedef struct rgSchTddANInfo
{
uint16_t sfn; /*!< ACK/NACK is sent for PDU in this SFN */
uint8_t subframe; /*!< ACK/NACK is sent for PDU in this subframe */
uint8_t dlDai; /*!< Downlink Assignment Index for
UL-DL Configuration 1-6 */
uint8_t ulDai; /*!< DAI for uplink */
uint8_t latestMIdx; /*!< Last transmitted DL subframe 'm' index */
uint8_t n1ResTpcIdx; /*!< N1 Res idx for scell assigned in TPC command */
Bool isSpsOccasion; /*!< To indicate the presence of SPS occasion */
#ifdef LTE_ADV
uint8_t wUlDai; /*!< Max Ul dai in all the cells */
#endif
} RgSchTddANInfo;
#endif
/**
* @brief
* Information about one MCS entry.
*/
typedef struct rgSchUlIMcsInfo
{
uint8_t qm;
uint8_t iTbs;
} RgSchUlIMcsTbl[29];
RgSchUlIMcsTbl rgUlIMcsTbl;
typedef struct rgSchUeCatTbl
{
uint32_t maxUlBits;/*Maximum number of
bits of an UL-SCH
transport block
transmitted within a
TTI*/
uint32_t maxDlBits[4];/*Maximum number of
bits of a DLSCH
transport block
received within a TTI*/
/* correcting DL harq softbuffer limitation logic */
uint32_t maxSftChBits;/*Total number of soft channel bits*/
Bool ul64qamSup;/*Support for 64QAM in UL*/
/* Changes for MIMO feature addition */
/* Removed dependency on MIMO compile-time flag */
uint32_t maxDlTbBits;/*Maximum number of DL-SCH
transport block bits
received within a TTI*/
uint8_t maxTxLyrs;/*Maximum number of supported
layers for spatial multiplexing
in DL*/
} RgSchUeCatTbl[CM_MAX_UE_CAT_SUPP + 1];
RgSchUeCatTbl rgUeCatTbl;
/* Changes for MIMO feature addition */
/* Removed dependency on MIMO compile-time flag */
typedef uint32_t RgSchTbSzTbl[RGSCH_MAX_NUM_LYR_PERCW][RGSCH_NUM_ITBS][RGSCH_MAX_NUM_RB];
#ifdef LTE_TDD
typedef uint8_t RgSchRaPrmblToRaFrmTbl[RGSCH_MAX_TDD_RA_PREAMBLE_FMT+1];
#else
/* Added matrix 'rgRaPrmblToRaFrmTbl' for computation of RA
sub-frames from preamble format */
typedef uint8_t RgSchRaPrmblToRaFrmTbl[RGSCH_MAX_RA_PREAMBLE_FMT+1];
#endif
RgSchRaPrmblToRaFrmTbl rgRaPrmblToRaFrmTbl;
uint8_t rgRvTable[4];
typedef struct rgDciFmt
{
uint8_t dciType;
union
{
RgDciFmt1AInfo dci1a;
} dci;
} RgDciFmt;
typedef enum rgSchPdcchSearchSpace
{
RG_SCH_UE_SPECIFIC_SEARCH_SPACE,
RG_SCH_CMN_SEARCH_SPACE,
}RgSchPdcchSearchSpace;
/**
* @brief
* Information about one PDCCH.
*/
typedef struct rgSchPdcch {
uint8_t nCce; /*!< CCE index */
CmLteAggrLvl aggrLvl; /*!< Aggregation level */
TfuDciInfo dci; /*!< PDCCH format */
uint16_t rnti; /*!< RNTI to who the PDCCH is allocated */
#if (defined (LTE_TDD))
uint8_t dlDai; /*!< DAI associated with this PDCCH.
THis is used for F1BCS resource calulcation */
#endif
/* Added support for SPS*/
#ifdef LTEMAC_SPS
CmLteTimingInfo relFbkTiming; /*!< Feebback timing information for release
PDCCH */
Bool isSpsRnti; /*!< TRUE if rnti is SPS RNTI */
uint16_t crnti; /*!< CRNTI to who the PDCCH is allocated */
#endif
CmLList lnk; /*!< To link PDCCHs in a subframe */
#ifdef EMTC_ENABLE
Void *emtcPdcch;
#endif
RgSchUeCb *ue; /*!< Pointer to the UE Control Block */
RgSchPdcchSearchSpace pdcchSearchSpace; /*!< Search Space from this PDCCH allocated */
uint8_t dciNumOfBits; /*!< Size of DCI in bits */
} RgSchPdcch;
/**
* @brief
* PDCCH information for cell.
*/
typedef struct rgSchPdcchInfo {
uint8_t *map; /*!< Bit map of PDCCHs */
uint8_t currCfi; /*!< Number of CCEs */
uint16_t nCce; /*!< Total CCEs */
CmLListCp pdcchs; /*!< List of RgSchPdcch */
} RgSchPdcchInfo;
typedef struct rgSchPhich
{
CmLList lnk; /*!< To link PHICHs in a subframe */
uint8_t hqFeedBack; /*!< Harq Feed Back */
uint8_t rbStart; /*!< Starting RB */
uint8_t nDmrs; /*!< 3 bits for DMRS cyclic shift */
/* changes for passing iphich at TFU;*/
Bool isForMsg3; /*! < Phich Ack/Nack conveyed for MSG 3 */
#ifdef LTE_TDD
uint8_t iPhich; /*!< For determining phich group */
#endif
} RgSchPhich;
typedef struct rgSchPhichInfo
{
CmLListCp phichs; /*!< List of RgSchPhich */
} RgSchPhichInfo;
typedef struct rgSchBcchTb
{
RgSchPdcch *pdcch;
Buffer *tb;
uint16_t tbSize;
} RgSchBcchTb;
typedef struct rgSchPcchTb
{
RgSchPdcch *pdcch;
Buffer *tb;
uint16_t tbSize;
} RgSchPcchTb;
typedef struct rgSchRaRspAlloc
{
uint16_t raRnti;
uint32_t tbSz;
TknUInt8 backOffInd; /*!< Backoff index value */
CmLListCp raRspLst; /*!< List of RaCbs */
CmLListCp contFreeUeLst; /*! List of HandOver or PdcchOrder UEs */
RgSchPdcch *pdcch; /*!< NULLP if no Rsp allocation done for raRnti*/
}RgSchRaRspAlloc;
typedef struct rgSchBchTb
{
Buffer *tb; /*!< BCH data for this frame */
uint16_t tbSize; /*!< Non-Zero if bch data is scheduled for this SF */
}RgSchBchTb;
/* Added support for SPS*/
#ifdef LTEMAC_SPS
/**
* TODO: check compilation
@brief Downlink Resource allocation type information. */
struct rgSchDlSfAllocInfo
{
uint32_t raType0Mask; /*!< RBG allocation mask for type 0*/
uint32_t raType1Mask[RG_SCH_NUM_RATYPE1_32BIT_MASK]; /*!< RA Type 1
allocation mask */
uint32_t raType1UsedRbs[RG_SCH_NUM_RATYPE1_32BIT_MASK];/*!< RA Type 1 Used RBs
per subset */
uint32_t nxtRbgSubset; /*!< Next RBG subset to be used for allocation */
uint32_t raType2Mask[RG_SCH_NUM_RATYPE2_32BIT_MASK];
/*!< Mask for resource allocation type 2 */
};
#endif /* LTEMAC_SPS */
/* LTE_ADV_FLAG_REMOVED_START */
/**
@brief RGR RB range for SFR */
typedef struct rgrPwrHiCCRange
{
uint8_t startRb; /*ueLst */
Void * laaCb;
CmLListCp hqPLst; /*!< This is a list of hq proc per DL
SF which are scheduled in that SF.
The number of harq procs awaiting
feedback for the same subframe depends on
mode TDD or FDD and max number of Carriers
that can be aggregated */
#ifdef LTE_ADV
RgSchN3PucchRes n3ScellPucch;
#endif
}RgSchDlHqInfo;
/*CA Dev End*/
/** @brief This structure contains the Measurement gap configuration for an UE.
*/
typedef struct rgUeMeasGapCfg
{
Bool isMesGapEnabled; /*!< Is Measuremnet gap enabled or disabled */
uint8_t gapPrd; /*!< Gap period 40ms/80ms */
uint8_t gapOffst; /*!< Gap offset - Vaue is 0 to 1*/
} RgUeMeasGapCfg;
/**
@brief Measurement Gap related information per UE. */
typedef struct rgSchUeMeasGapCb
{
Bool isMesGapEnabled;/*!< TRUE if Measurement gap is enabled for this UE */
uint8_t isMeasuring; /*!< Set to TRUE during measurement gap */
uint8_t gapPrd; /*!< Measurement gap period configuration for the UE */
uint8_t gapOffst; /*!< Measurement gap offset for the UE */
CmLList measQLnk; /*!< To Link to the measurement gap list */
CmLList ackNakQLnk; /*!< To Link to the ACK NACK Rep list */
CmTimer measGapTmr; /*!< Timer for Measurement Gap */
CmTimer measGapUlInactvTmr; /*!< UL Inactive timer for measurement gap */
CmTimer measGapDlInactvTmr; /*!< DL Inactive timer for measurement gap */
} RgSchUeMeasGapCb;
/**
@brief ACK-NACK repetition related information per UE. */
typedef struct rgSchUeAckNakRepCb
{
Bool isAckNackEnabled; /*!< Is ACK/NACK Enabled*/
uint8_t isAckNakRep; /*!< Set to TRUE during ACK-NACK repetition prd */
uint8_t cfgRepCnt; /*!< Configured value for the repetition counter */
uint8_t repCntr; /*!< Actual repetition counter */
uint16_t pucchRes; /*!< PUCCH resource for repetition */
CmTimer ackNakRepUlInactvTmr; /*!< UL Inactive timer for ack-nack repetition */
CmTimer ackNakRepDlInactvTmr; /*!< DL Inactive timer for ack-nack repetition */
CmTimer ackNakRepTmr; /*!< Timer for ack-nack repetition */
CmLList ackNakRepLnk; /*!< ACK NACK repetition queue link */
CmLListCp *prsntQ; /*!< Pointer to the Queue that this UE is current
present in. */
} RgSchUeAckNakRepCb;
/**
* @brief
* UE's MIMO specific information.
*/
typedef struct rgSchUeMimoInfo
{
RgrTxMode oldTMode; /*!< UE's Previous Transmission Mode */
RgrTxMode txMode; /*!< UE's Transmission Mode */
TknUInt32 doa; /*!< DOA indicator for this UE */
Bool puschFdbkVld; /*!< True if Precoding Info in PDCCH has to be
in-accordance with the latest PUSCH report */
TfuDlCqiPuschInfo puschPmiInfo; /*!< PUSCH report details for explicit PMI
* information to PHY during a PDSCH */
RgrCodeBookRstCfg cdbkSbstRstrctn; /*!< Codebook subset restriction defined as per
* 36.331 section 6.3.2. As of now, this info
* is not processed by MAC. SCH shall use the
* PMI reported by UE unconditionally.*/
#ifdef DL_LA
S32 txModUpChgFactor; /*!< tx mode chnage factor for step up*/
S32 txModDownChgFactor; /*!< tx mode chnage factor for step
Down*/
#endif
}RgSchUeMimoInfo;
/* Added changes of TFU_UPGRADE */
#ifdef TFU_UPGRADE
/** @brief This structure that stores the length of Bits that
* will be received over PUSCH for Aperiodic Mode 3-1.
*/
typedef struct rgSchCqiRawPuschMode31
{
uint8_t wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
uint8_t totLenSbDiffCqiCw0; /*!< Length of SubBand Differential CQI Codeword 0 */
uint8_t r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1*/
uint8_t r1TotLenSbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank = 1*/
uint8_t rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank > 1*/
uint8_t rg1TotLenSbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank > 1*/
uint8_t r1PmiBitLen; /*!< Length of PMI Bits for Rank = 1*/
uint8_t rg1PmiBitLen; /*!< Length of PMI Bits for Rank > 1*/
} RgSchCqiRawPuschMode31;
/** @brief This structure that stores the length of Bits that
* will be received over PUSCH for Aperiodic Mode 3-0.
*/
typedef struct rgSchCqiRawPuschMode30
{
uint8_t wideBCqiCw; /*!< Length of Wideband CQI */
uint8_t totLenSbDiffCqi; /*!< Length of SubBand Differential CQI */
} RgSchCqiRawPuschMode30;
/** @brief This structure that stores the length of Bits that
* will be received over PUSCH for Aperiodic Mode 2-2.
*/
typedef struct rgSchCqiRawPuschMode22
{
uint8_t wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
uint8_t sBDiffCqiCw0; /*!< Length of SubBand Differential CQI Codeword 0 */
uint8_t r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1 */
uint8_t r1SbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank =1*/
uint8_t rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank > 1*/
uint8_t rg1SbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank >1*/
uint8_t posOfM; /*!< Position of M selected SubBands */
uint8_t r1PmiBitLen; /*!< Length of PMI Bits for Rank =1*/
uint8_t rg1PmiBitLen; /*!< Length of PMI Bits for Rank >1*/
} RgSchCqiRawPuschMode22;
/** @brief This structure that stores the length of Bits that
* will be received over PUSCH for Aperiodic Mode 2-0.
*/
typedef struct rgSchCqiRawPuschMode20
{
uint8_t wideBCqiCw; /*!< Length of Wideband CQI */
uint8_t subBandDiffCqi; /*!< Length of SubBand Differential CQI */
uint8_t posOfM; /*!< Position of M selected SubBands */
} RgSchCqiRawPuschMode20;
/** @brief This structure that stores the length of Bits that
* will be received over PUSCH for Aperiodic Mode 1-2.
*/
typedef struct rgSchCqiRawPuschMode12
{
uint8_t wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
uint8_t r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1*/
uint8_t rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword for Rank > 1 */
uint8_t r1TotalPmiBitLen; /*!< Aggregate length of PMI Bits for Rank =1 */
uint8_t rg1TotalPmiBitLen; /*!< Aggregate length of PMI Bits for Rank > 1 */
} RgSchCqiRawPuschMode12;
/** @brief This structure that stores the length of Bits that
* will be received over PUSCH.
*/
typedef struct rgSchDlCqiRawPusch
{
TfuDlCqiPuschMode mode; /*!< PUSCH CQI mode */
TknUInt8 ri; /*!< Rank Indicator for TM 3,4 */
union
{
RgSchCqiRawPuschMode12 mode12Info; /*!< Mode 1-2 information */
RgSchCqiRawPuschMode20 mode20Info; /*!< Mode 2-0 information */
RgSchCqiRawPuschMode22 mode22Info; /*!< Mode 2-2 information */
RgSchCqiRawPuschMode30 mode30Info; /*!< Mode 3-0 information */
RgSchCqiRawPuschMode31 mode31Info; /*!< Mode 3-1 information */
}u;
} RgSchDlCqiRawPusch;
typedef struct rgSchPuschRawCqiInfoPerCell
{
uint8_t sCellIdx; /*!< Serving cell idx of the cell for
this cqi info*/
RgSchDlCqiRawPusch puschRawCqiInfo; /*!< Raw CQI Bit Width for PUSCH */
} RgSchPuschRawCqiInfoPerCell;
typedef struct rgSchPuschRawCqiInfoForSCells
{
uint8_t numOfCells; /* Num of cells for which Apcqi is comming*/
RgSchPuschRawCqiInfoPerCell cqiBitWidth[CM_LTE_MAX_CELLS];
} RgSchPuschRawCqiInfoForSCells;
typedef struct rgSchPucchRawCqiInfoPerCell
{
uint8_t sCellIdx; /*!< Serving cell idx of the cell for
this cqi info*/
TfuDlCqiPucch pucchRawCqiInfo; /*!< Raw CQI Bit Width for PUCCH */
} RgSchPucchRawCqiInfoPerCell;
typedef struct rgSchUeRawCqiBitWidthInfo
{
TfuRecpReqType type; /*!< Type indicating PUCCH or PUSCH */
CmLteTimingInfo recvTime;
union
{
RgSchPucchRawCqiInfoPerCell pucch;
RgSchPuschRawCqiInfoForSCells pusch;
}u;
} RgSchUeRawCqiBitWidthInfo;
#endif
/* CaDev start */
#ifdef LTE_ADV
/**
* @brief
* Enum for storing the different states of a Scell
* RG_SCH_SCELL_INACTIVE : SCell is added but not activate
* RG_SCH_SCELL_TOBE_ACTIVATED : SCell Activation trigger condition is met
Need to be scheduled.
* RG_SCH_SCELL_ACTVTN_IN_PROG : Waiting for Harq feedback for the scell activation
* RG_SCH_SCELL_ACTIVE : SCell is activated succesfully
*/
typedef enum
{
RG_SCH_SCELL_INACTIVE = 0, /*!sfInfo[(_sfi)].sfType = _state;\
}
/* Mark sfi as UL Subframe */
#define RG_SCH_DYN_TDD_MARKTYPE_UL(_dynTdd, _sfi)\
{\
RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, RG_SCH_DYNTDD_DLC_ULD);\
}
/* Mark sfi as DL Subframe */
#define RG_SCH_DYN_TDD_MARKTYPE_DL(_dynTdd, _sfi)\
{\
RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, RG_SCH_DYNTDD_DLC_DLD);\
}
/* Get SFI and SFN from given time and subframe offset */
#define RG_SCH_DYN_TDD_GET_SFIDX(_sfi, _crntSfIdx, _offset)\
(_sfi) = (_crntSfIdx + _offset)% RG_SCH_DYNTDD_MAX_SFINFO
/**
@brief Dynamic TDD subframe type. */
typedef struct rgSchDynTddSfType
{
uint8_t sfType; /*!< 0= NOT Defined
1= DL Cntrl + DL Data
2= DL Cntrl + DL Data + UL Cntrl
3= DL Cntrl + UL Data
4= DL Cntrl + UL Data + UL Cntrl
*/
}RgSchDynTddSfType;
/**
@brief Dynamic TDD control Block */
typedef struct rgSchDynTddCb
{
Bool isDynTddEnbld; /*!< Is dynamic TDD enabled */
uint8_t crntDTddSfIdx; /*!< Pivot Index corresponding
cell's current subframe */
RgSchDynTddSfType sfInfo[RG_SCH_DYNTDD_MAX_SFINFO];
}RgSchDynTddCb;
#endif
/**
* @brief
* Global Control block for LTE-MAC.
*/
struct _rgSchCb
{
TskInit rgSchInit; /*!< Task Init info */
RgSchGenCb genCfg; /*!< General Config info */
uint8_t numSaps; /*!< Num RGR Saps = Num TFU Saps */
RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
RgSchLowSapCb *tfuSap; /*!< TFU SAP Control Block */
RgSchUpSapCb *rgmSap; /*!< TFU SAP Control Block */
CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
CmTqType tmrTq[RGSCH_TQ_SIZE]; /*!< Timer Task Queue */
uint8_t rgSchDlDelta; /* 4UE_TTI_DELTA */
uint8_t rgSchCmnDlDelta;
uint8_t rgSchUlDelta;
RgSchCellCb *cells[CM_LTE_MAX_CELLS]; /* Array to store cellCb ptr */
RgrSchedEnbCfg rgrSchedEnbCfg; /*!< eNB level RR/PFS Config */
Void *rgSchEnbPfsDl; /*!< eNB level PFS DL Block */
Void * laaCb;
#ifdef RG_5GTF
RgSchDynTddCb rgSchDynTdd; /*!< Dynamic TDD Control Block */
#endif
};
/* Declaration for scheduler control blocks */
RgSchCb rgSchCb[RGSCH_MAX_INST];
/*
* Data structures for RAM
*/
/**
* @brief
* Random Access Req Info to be stored in cellCb.
*/
typedef struct rgSchRaReqInfo
{
CmLList raReqLstEnt; /*!< Linked list entity for RaReq List */
CmLteTimingInfo timingInfo; /*!< RACHO: Time of RaReq Reception */
RgTfuRaReqInfo raReq; /*!< Random Access Request Information */
RgSchUeCb *ue; /*!< UECB if RAP ID is a dedicated one */
} RgSchRaReqInfo;
/**
* @enum rgSchRaState
* Enumeration of random access states.
*/
typedef enum rgSchRaState
{
RGSCH_RA_MSG3_PENDING, /*!< Msg3 reception pending */
RGSCH_RA_MSG4_PENDING, /*!< Msg4 transmission pending */
RGSCH_RA_MSG4_DONE /*!< Msg4 transmission successful */
} RgSchRaState;
/**
* @brief
* Control block for Random Access.
*/
struct rgSchRaCb
{
CmLList raCbLnk; /*!< To link to the raCb list */
CmLList schdLnk; /*!< To link raCb to the "to be scheduled"
list */
CmLteRnti tmpCrnti; /*!< Temporary C-RNTI */
CmLteTimingInfo timingInfo; /*!< Timing information */
RgSchRntiLnk *rntiLnk; /*!< Link to RNTI for raCb */
RgSchRaState raState; /*!< Random access state */
struct
{
uint32_t bo; /*!< Buffer occupancy for CCCH */
} dlCcchInfo; /*!< Params for DL CCCH */
uint8_t msg3HqProcId; /*!< Msg3 Harq Process ID */
/*ccpu00128820 - DEL - msg3HqProcRef is delete for Msg3 alloc double delete issue*/
RgSchUlHqProcCb msg3HqProc; /*!< msg3HqProcRef points to this initially */
RgSchUeCb *ue; /*!< NULL initially */
Bool toDel; /*!< To delete this RaCb after msg4 reject */
TknUInt8 phr; /*!< To store the PHR, if received along with
Msg3 */
CmLList rspLnk; /*!< Used to link RACB to a frame for resp */
uint8_t rapId; /*!< RAP ID */
TknUInt16 ta; /*!< Timing Adjustment */
RgSchUlGrnt msg3Grnt; /*!< Msg3 grant as given by the UL Sched */
uint32_t y[RGSCH_NUM_SUB_FRAMES]; /*!< y values using tmpCrnti by DLSCHED */
RgSchDlHqEnt *dlHqE; /*!< DL HARQ module */
uint8_t ccchCqi; /*!< DL Cqi obtained from RaReq and Used for CCCH */
RgSchDlRbAlloc rbAllocInfo; /*!< RB Allocation Info for MSG4 Trans/Retrans */
/* PHR handling for MSG3 */
CmLteTimingInfo msg3AllocTime; /*!< Allocation time for msg3 grant */
#ifdef RGR_V1
/* CR timer changes*/
CmLList contResTmrLnk; /*!< To link raCb to the
Guard Timer/Contention Resolution timer list*/
CmLteTimingInfo expiryTime; /*!< Expiry time for Guard/Contention
Resolution timers */
uint32_t ccchSduBo; /*!rntiLnk */
Void rgSCHUtlIndRntiRls2Mac ARGS(( RgSchCellCb *cell, CmLteRnti rnti,
Bool ueIdChng, CmLteRnti newRnti));
/*rg008.201 - Added support for SPS*/
#ifdef LTEMAC_SPS
S16 rgSCHDbmDeInitSpsUeCbLst ARGS((RgSchCellCb *cellCb));
S16 rgSCHDbmInsSpsUeCb ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
RgSchUeCb* rgSCHDbmGetSpsUeCb ARGS((RgSchCellCb *cellCb, CmLteRnti ueId));
RgSchUeCb* rgSCHDbmGetNextSpsUeCb ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
S16 rgSCHDbmDelSpsUeCb ARGS((RgSchCellCb *cellCb,RgSchUeCb *ueCb));
#endif /* LTEMAC_SPS */
#ifdef LTE_L2_MEAS
/*
* L2M APIs
*/
S16 rgSchL2mMeasReq ARGS ((
RgSchCellCb *cell,
LrgSchMeasReqInfo *measInfo,
RgSchErrInfo err));
S16 RgSchMacL2MeasSend ARGS
((
Pst* pst,
RgInfL2MeasSndReq *measInfo
));
S16 RgSchMacL2MeasStop ARGS
((
Pst* pst,
RgInfL2MeasStopReq *measInfo
));
#endif /* LTE_L2_MEAS */
/*
* DHM APIs
*/
/* LTE_ADV_FLAG_REMOVED_START */
S16 rgSchSFRTotalPoolInit ARGS((RgSchCellCb *cell, RgSchDlSf *sf));
/* LTE_ADV_FLAG_REMOVED_END */
Void rgSCHDhmHqPAdd2FreeLst ARGS (( RgSchDlHqProcCb *hqP));
Void rgSCHDhmHqPAdd2InUseLst ARGS (( RgSchDlHqProcCb *hqP));
Void rgSCHDhmHqPDelFrmFreeLst ARGS (( RgSchDlHqProcCb *hqP));
Void rgSCHDhmHqPDelFrmInUseLst ARGS (( RgSchDlHqProcCb *hqP));
RgSchDlHqEnt *rgSCHDhmHqEntInit ARGS((RgSchCellCb *cell));
S16 rgSCHDhmGetAvlHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue, CmLteTimingInfo timingInfo,
RgSchDlHqProcCb **hqP));
Void rgSCHDhmHqRetx ARGS((RgSchDlHqEnt *hqE, CmLteTimingInfo timeInfo,
RgSchDlHqProcCb *hqP));
RgSchDlHqProcCb * rgSCHDhmLastSchedHqProc ARGS((RgSchDlHqEnt *hqE));
/* CR timer changes*/
S16 rgSCHDhmGetCcchSduHqProc ARGS((RgSchUeCb *ueCb, CmLteTimingInfo timeInfo,
RgSchDlHqProcCb **hqP));
S16 rgSCHDhmGetMsg4HqProc ARGS((RgSchRaCb *raCb, CmLteTimingInfo timeInfo));
Void rgSCHDhmRlsHqProc ARGS((RgSchDlHqProcCb *hqP));
/* ccpu00118350 : Correcting NDI manipulation of Harq */
Void rgSCHDhmRlsHqpTb ARGS((RgSchDlHqProcCb *hqP, uint8_t tbIdx, Bool togNdi));
Void rgSCHUtlDlHqPTbAddToTx ARGS((RgSchDlSf *subFrm,
RgSchDlHqProcCb *hqP, uint8_t tbIdx ));
Void rgSCHDhmHqTbRetx ARGS(( RgSchDlHqEnt *hqE,
CmLteTimingInfo timingInfo, RgSchDlHqProcCb *hqP, uint8_t tbIdx));
Void rgSCHUtlDlHqPTbAddToTx ARGS((RgSchDlSf *subFrm,
RgSchDlHqProcCb *hqP, uint8_t tbIdx ));
Void rgSCHDhmHqTbRetx ARGS(( RgSchDlHqEnt *hqE,
CmLteTimingInfo timingInfo, RgSchDlHqProcCb *hqP, uint8_t tbIdx));
#ifdef RG_UNUSED
S16 rgSCHDhmGetHqProcFrmId ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t idx,
RgSchDlHqProcCb **hqP));
#endif
/* Changes for MIMO feature addition */
Void rgSCHDhmSchdTa ARGS((RgSchUeCb *ueCb, RgSchDlHqTbCb *tbInfo));
S16 rgSCHDhmHqFdbkInd ARGS((Void *cb, uint8_t cbType, RgSchCellCb *cellCb,
CmLteTimingInfo timingInfo, RgTfuHqInfo *fdbk, RgInfRlsHqInfo
*rlsHqBufs,RgSchErrInfo *err));
#ifdef EMTC_ENABLE
S16 rgSCHDhmEmtcHqFdbkInd ARGS((Void *cb, uint8_t cbType, RgSchCellCb *cellCb,
CmLteTimingInfo timingInfo, RgTfuHqInfo *fdbk, RgInfRlsHqInfo
*rlsHqBufs,RgSchErrInfo *err));
S16 rgSCHUtlAddToResLst
(
CmLListCp *cp,
RgSchIotRes *iotRes
);
#endif
/*CA Dev Start */
S16 rgSCHDhmPrcFdbkForTb(RgSchCellCb *cell,RgSchUeCb *ue,
RgSchDlHqProcCb *hqP,RgSchDlSf *sf,Bool isMsg4,
uint16_t rnti,uint8_t tbCnt,CmLteTimingInfo timingInfo, uint8_t isAck,
RgInfRlsHqInfo *rlsHqBufs,RgSchErrInfo *err
);
/*CA Dev End */
Void rgSCHDhmRgrUeCfg ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb,
RgrUeCfg *ueCfg, RgSchErrInfo *err));
Void rgSCHDhmRgrUeRecfg ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb,
RgrUeRecfg *ueCfg, RgSchErrInfo *err));
Void rgSCHDhmRgrCellCfg ARGS((RgSchCellCb *cellCb, RgrCellCfg *cellCfg,
RgSchErrInfo *err));
Void rgSCHDhmRgrCellRecfg ARGS((RgSchCellCb *cellCb, RgrCellRecfg
*cellRecfg, RgSchErrInfo *err));
Void rgSCHDhmFreeUe ARGS((RgSchUeCb *ueCb));
Void rgSCHDhmUpdTa ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb, uint8_t ta));
Void rgSCHDhmProcTAExp ARGS((RgSchUeCb *ue));
/* Changes for MIMO feature addition */
S16 rgSCHDhmAddLcData ARGS((Inst inst, RgSchLchAllocInfo *lchData,
RgSchDlHqTbCb *tbInfo));
S16 rgSCHDhmRlsDlsfHqProc ARGS((RgSchCellCb *cellCb, CmLteTimingInfo
timingInfo));
#ifdef LTE_TDD
S16 rgSCHDhmTddRlsSubFrm ARGS((RgSchCellCb *cell, CmLteTimingInfo uciTimingInfo));
S16 rgSCHCfgVldtTddDrxCycCfg ARGS((RgSchCellCb *cell, uint16_t drxCycle,
uint8_t onDurTmr, uint16_t offSet));
#endif
/* Added support for SPS*/
#ifdef LTEMAC_SPS
S16 rgSCHDhmGetHqProcFrmId ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
uint8_t idx,
RgSchDlHqProcCb **hqP
));
#endif /* LTEMAC_SPS */
/* Freeing up the HARQ proc blocked for
* indefinite time in case of Retx */
S16 rgSCHDhmDlRetxAllocFail ARGS((
RgSchUeCb *ue,
RgSchDlHqProcCb *proc
));
/* MS_WORKAROUND for ccpu00122893 temp fix Incorrect HqProc release was done instead of
* a Harq Entity reset. Fixing the same */
Void rgSCHDhmHqEntReset ARGS((
RgSchDlHqEnt *hqE
));
/* Measurement GAP and ACK NACK */
S16 rgSCHMeasGapANRepUeCfg ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
RgrUeCfg *ueCfg
));
S16 rgSCHMeasGapANRepUeRecfg ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
RgrUeRecfg *ueRecfg
));
/* ccpu00133470- Added extra argument to identify UE DEL*/
Void rgSCHMeasGapANRepUeDel ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
Bool isUeDel
));
S16 rgSCHMeasGapANRepTtiHndl ARGS((
RgSchCellCb *cell
));
S16 rgSCHMeasGapANRepGetDlInactvUe ARGS((
RgSchCellCb *cell,
CmLListCp *dlInactvUeLst
));
S16 rgSCHMeasGapANRepGetUlInactvUe ARGS((
RgSchCellCb *cell,
CmLListCp *ulInactvUeLst
));
Void rgSCHMeasGapANRepDlInactvTmrExpry ARGS((
RgSchUeCb *ue,
uint8_t tmrEvnt
));
Void rgSCHMeasGapANRepUlInactvTmrExpry ARGS((
RgSchUeCb *ue,
uint8_t tmrEvnt
));
Void rgSCHMeasGapANRepTmrExpry ARGS((
RgSchUeCb *ue
));
Void rgSCHAckNakRepTmrExpry ARGS((
RgSchUeCb *ue
));
Void rgSCHAckNakRepSndHqFbkRcpReq ARGS((
RgSchCellCb *cell,
RgSchDlSf *dlSf,
CmLteTimingInfo timingInfo));
Void rgSCHAckNakRepAddToQ ARGS((
RgSchCellCb *cell,
RgSchDlSf *crntDlSf));
/*
* SCH Util APIs
*/
#ifdef LTEMAC_SPS
Void rgSCHUtlHdlCrcInd ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
CmLteTimingInfo timingInfo
));
#endif
#ifdef LTE_L2_MEAS
S16 rgSCHUtlValidateMeasReq ARGS ((RgSchCellCb *cellCb,
LrgSchMeasReqInfo *schL2MeasInfo,
RgSchErrInfo *err
));
S16 rgSchL2mSndCfm ARGS((Pst *pst,
RgSchL2MeasCb *measCb,
LrgSchMeasReqInfo *measInfo,
Bool isErr
));
S16 rgSchFillL2MeasCfm ARGS((
RgSchCellCb *cell,
RgSchL2MeasCb *measCb,
LrgSchMeasCfmInfo *cfm,
uint32_t measTime
));
Void rgSchL2mFillCfmPst ARGS((
Pst *pst,
Pst *cfmPst,
LrgSchMeasReqInfo *measInfo
));
S16 rgSCHL2Meas ARGS((
RgSchCellCb *cell,
uint8_t isCalrCrcInd
));
#endif /* LTE_L2_MEAS */
/* Added changes of TFU_UPGRADE */
#ifdef TFU_UPGRADE
F64 rgSCHUtlPower ARGS
((
F64 x,
F64 n
));
uint32_t rgSCHUtlParse ARGS
((
uint8_t *buff,
uint8_t startPos,
uint8_t endPos,
uint8_t buffSize
));
uint8_t rgSCHUtlFindDist ARGS
((
uint16_t crntTime,
uint16_t tempIdx
));
#endif
Bool rgSCHUtlPdcchAvail ARGS((RgSchCellCb *cell, RgSchPdcchInfo
*pdcchInfo, CmLteAggrLvl aggrLvl, RgSchPdcch **pdcch));
Void rgSCHUtlPdcchPut ARGS((RgSchCellCb *cell, RgSchPdcchInfo *pdcchInfo,
RgSchPdcch *pdcch));
#ifdef LTE_TDD
/* Changes for passing iPhich at TFU interface*/
S16 rgSCHUtlAddPhich ARGS((RgSchCellCb *cellCb, CmLteTimingInfo frm,
uint8_t hqFeedBack, uint8_t nDmrs, uint8_t rbStart, uint8_t iPhich));
#else
S16 rgSCHUtlAddPhich ARGS((RgSchCellCb *cellCb, CmLteTimingInfo frm,
uint8_t hqFeedBack, uint8_t nDmrs, uint8_t rbStart,Bool isForMsg3));
#endif
RgSchDlSf* rgSCHUtlSubFrmGet ARGS((RgSchCellCb *cell,
CmLteTimingInfo frm));
Void rgSCHUtlSubFrmPut ARGS((RgSchCellCb *cell, RgSchDlSf *sf));
uint8_t rgSCHUtlLog32bitNbase2 ARGS((uint32_t n));
/* Added support for SPS*/
#ifdef LTEMAC_SPS
RgSchDlHqProcCb * rgSCHDhmSpsDlGetHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
CmLteTimingInfo timingInfo));
#endif
#ifdef LTE_TDD
uint8_t rgSCHUtlCalcNCce ARGS((uint8_t bw, RgrPhichNg ng, uint8_t cfi, uint8_t mPhich,
uint8_t numAntna, Bool isEcp));
#else
uint8_t rgSCHUtlCalcNCce ARGS((uint8_t bw, RgrPhichNg ng, uint8_t cfi, uint8_t numAntna, Bool
isEcp));
#endif
#ifdef LTE_TDD
/* Changes for passing iPhich at TFU interface*/
S16 rgSCHUtlGetPhichInfo ARGS((RgSchUlHqProcCb *hqProc, uint8_t *rbStartRef,
uint8_t *nDmrsRef, uint8_t *iPhich));
#else
S16 rgSCHUtlGetPhichInfo ARGS((RgSchUlHqProcCb *hqProc, uint8_t *rbStartRef,
uint8_t *nDmrsRef));
#endif
/* Added changes of TFU_UPGRADE */
#ifndef TFU_UPGRADE
/* To include the length and ModOrder in DataRecp Req. */
/* Updating NDI and HARQ proc Id */
S16 rgSCHUtlAllocRcptInfo ARGS((RgSchUlAlloc *alloc, CmLteRnti *rnti,
uint8_t *iMcsRef, uint8_t *rbStartRef, uint8_t *numRbRef, uint8_t *rvRef, uint16_t *size,
TfuModScheme *modType,Bool *isRtx,
uint8_t *nDmrs,
Bool *ndi,
uint8_t *hqPId));
#else
S16 rgSCHUtlAllocRcptInfo ARGS((
RgSchCellCb *cell,
RgSchUlAlloc *alloc,
CmLteTimingInfo *timeInfo,
TfuUeUlSchRecpInfo *recpReq
));
#endif /* TFU_UPGRADE */
S16 rgSCHUtlRgrCellCfg ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg,
RgSchErrInfo *errInfo));
S16 rgSCHUtlRgrCellRecfg ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
RgSchErrInfo *errInfo));
S16 rgSCHUtlFreeCell ARGS((RgSchCellCb *cell));
S16 rgSCHUtlRgrUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgrUeCfg *cfg, RgSchErrInfo *err));
S16 rgSCHUtlRgrLcCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchDlLcCb *dl, RgrLchCfg *cfg,RgSchErrInfo *errInfo));
S16 rgSCHUtlRgrLcDel ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
CmLteLcId lcId, uint8_t lcgId));
S16 rgSCHUtlRgrLcRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
RgSchDlLcCb *dlLc,RgrLchRecfg *recfg,RgSchErrInfo *err));
S16 rgSCHUtlRgrLcgCfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
RgrLcgCfg *cfg,RgSchErrInfo *errInfo));
S16 rgSCHUtlRgrLcgRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
RgrLcgRecfg *recfg,RgSchErrInfo *err));
Void rgSCHUtlRgrLcgDel ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
uint8_t lcgId));
Void rgSCHUtlDlCqiInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
TfuDlCqiRpt *dlCqiInd, CmLteTimingInfo timingInfo));
/* Added changes of TFU_UPGRADE */
#ifdef TFU_UPGRADE
Void rgSCHUtlRawCqiInd ARGS
((
RgSchCellCb *cell,
RgSchUeCb *ue,
TfuRawCqiRpt* rawCqiRpt,
CmLteTimingInfo timingInfo
));
Void rgSCHUtlSrsInd ARGS
((
RgSchCellCb *cell,
RgSchUeCb *ue,
TfuSrsRpt* srsRpt,
CmLteTimingInfo timingInfo
));
S16 rgSCHUtlGetCfgPerOff ARGS
((
RgSchPerTbl tbl,
uint16_t cfgIdx,
uint16_t *peri,
uint16_t *offset
));
#endif
Void rgSCHUtlDoaInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
TfuDoaRpt *doaInd));
Void rgSCHUtlDlTARpt ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
/* Changes for MIMO feature addition */
Void rgSCHUtlDlRlsSubFrm ARGS((RgSchCellCb *cell, CmLteTimingInfo subFrm));
Void rgSCHUtlDlProcAddToRetx ARGS((RgSchCellCb *cell,
RgSchDlHqProcCb *hqP));
S16 rgSCHUtlRegSch ARGS((uint8_t schIdx, RgSchdApis *apis));
Void rgSCHUtlDlHqProcAddToTx ARGS((RgSchDlSf *subFrm, RgSchDlHqProcCb *hqP));
/* Changes for MIMO feature addition */
Void rgSCHUtlDlHqPTbRmvFrmTx ARGS((RgSchDlSf *subFrm,
RgSchDlHqProcCb *hqP, uint8_t tbIdx, Bool isRepeating));
S16 rgSCHUtlRgrUeRecfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgrUeRecfg *recfg, RgSchErrInfo *err));
Void rgSCHUtlFreeDlLc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchDlLcCb *dlLc));
Void rgSCHUtlFreeUlLc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchUlLcCb *ulLc));
Void rgSCHUtlFreeUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
Void rgSCHUtlDlDedBoUpd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchDlLcCb *svc));
#ifdef RG_UNUSED
S16 rgSCHUtlUpdUlHqProc ARGS((RgSchCellCb *cell, RgSchUlHqProcCb *curProc,
RgSchUlHqProcCb *oldProc));
#endif
/* PHR handling for MSG3 */
Void rgSCHUtlRecMsg3Alloc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchRaCb *raCb));
S16 rgSCHUtlContResUlGrant ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgSchErrInfo *err));
S16 rgSCHUtlSrRcvd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
CmLteTimingInfo, RgSchErrInfo *err));
Void rgSCHUtlUpdBsrShort ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t lcgId,
uint8_t bsr, RgSchErrInfo *err));
Void rgSCHUtlUpdBsrTrunc ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t lcgId,
uint8_t bsr, RgSchErrInfo *err));
Void rgSCHUtlUpdBsrLong ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
uint8_t bsr1,uint8_t bsr2,uint8_t bsr3,uint8_t bsr4, RgSchErrInfo *err));
S16 rgSCHUtlUpdPhr ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
uint8_t phr, RgSchErrInfo *err));
S16 rgSCHUtlUpdExtPhr ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
RgInfExtPhrCEInfo * extPhr, RgSchErrInfo *err));
S16 rgSCHUtlDataRcvd ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t numLc,
RgSchUlLcCb *lcArr[], uint16_t bytesArr[], RgSchErrInfo *err));
Void rgSCHUtlUlCqiInd ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
TfuUlCqiRpt *ulCqiInfo));
Void rgSCHUtlPucchDeltaPwrInd ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
S8 delta));
Void rgSCHUtlUeReset ARGS(( RgSchCellCb *cell, RgSchUeCb *ue));
Void rgSCHUtlUlHqProcForUe ARGS((RgSchCellCb *cell, CmLteTimingInfo frm,
RgSchUeCb *ue, RgSchUlHqProcCb **procRef));
RgSchUlAlloc *rgSCHUtlFirstRcptnReq ARGS((RgSchCellCb *cell));
RgSchUlAlloc *rgSCHUtlNextRcptnReq ARGS((RgSchCellCb *cell,
RgSchUlAlloc *alloc));
RgSchUlAlloc *rgSCHUtlFirstHqFdbkAlloc ARGS((RgSchCellCb *cell, uint8_t idx));
RgSchUlAlloc *rgSCHUtlNextHqFdbkAlloc ARGS((RgSchCellCb *cell,
RgSchUlAlloc *alloc, uint8_t idx));
S16 rgSCHUtlTfuBndReq ARGS((Inst inst, SuId suId, SpId spId));
S16 rgSCHUtlTfuUBndReq ARGS((Inst inst, RgSchLowSapCfgInfo sapCfg, Reason reason));
#ifdef EMTC_ENABLE
S16 rgSCHEmtcUtlResetSfAlloc ARGS((RgInfSfAlloc *sfAlloc,
Bool resetCmnLcInfo, Bool restAlloc));
#endif
S16 rgSCHUtlResetSfAlloc ARGS((RgInfSfAlloc *sfAlloc,
Bool resetCmnLcInfo, Bool restAlloc));
S16 rgSCHUtlGetSfAlloc ARGS((RgSchCellCb *cell));
S16 rgSCHUtlPutSfAlloc ARGS((RgSchCellCb *cell));
S16 rgSCHUtlAllocSBuf ARGS((Inst inst, Data **pData, Size size));
/* ccpu00117052 - MOD - Passing double pointer
for proper NULLP assignment*/
Void rgSCHUtlFreeSBuf ARGS((Inst inst, Data **data, Size size));
Void rgSCHUtlFillDgnParams ARGS((Inst inst, RgUstaDgn *dgn,uint8_t dgnType));
Void rgSCHUtlGetPstToLyr ARGS((Pst *pst,RgSchCb *schCb,Inst macInst));
S16 rgSCHUtlFillRgInfCmnLcInfo ARGS((RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,
CmLteLcId lcId, Bool sendInd));
S16 rgSCHUtlFillRgInfRarInfo ARGS((RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,RgSchCellCb *cell));
S16 rgSCHUtlFillPdschDciInfo ARGS((TfuPdschDciInfo *pdschDci,TfuDciInfo
*pdcchDci));
/* CA dev Start */
Void rgSCHUtlFillRgInfUeInfo ARGS((RgSchDlSf*, RgSchCellCb *cell, CmLListCp *dlDrxInactvTmrLst,
CmLListCp *dlInActvLst, CmLListCp *ulInActvLst));
/* CA dev End */
S16 rgSCHUtlUpdSch ARGS((RgInfSfDatInd *subfrmInfo, RgSchCellCb *cellCb,
RgSchUeCb *ueCb, RgInfUeDatInd *pdu,RgSchErrInfo *err));
S16 rgSCHUtlHndlCcchBoUpdt ARGS((RgSchCellCb *cell,RgInfCmnBoRpt *boRpt));
S16 rgSCHUtlHndlBcchPcchBoUpdt ARGS((RgSchCellCb *cell,RgInfCmnBoRpt
*boUpdt));
S16 rgSCHUtlRgrBndCfm ARGS ((Inst inst, SuId suId,uint8_t status));
/* Added for sending TTI tick to RRM */
#ifdef RGR_RRM_TICK
S16 rgSCHUtlRgrTtiInd ARGS ((RgSchCellCb *cell, RgrTtiIndInfo *ttiInd));
#endif
S16 schSendCfgCfm ARGS ((Region reg, Pool pool, \
RgrCfgTransId transId, uint8_t status));
S16 rgSCHUtlProcMsg3 ARGS((RgInfSfDatInd *subfrmInfo, RgSchCellCb *cellCb,
RgSchUeCb *ueCb, CmLteRnti rnti,RgInfUeDatInd *pdu,
RgSchErrInfo *err ));
#ifdef RG_PHASE_2
S16 rgSCHUtlTfuGrpPwrCntrlReq ARGS((Inst inst,S16 sapId,
TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq));
#endif
S16 rgSCHUtlTfuCntrlReq ARGS((Inst inst, S16 sapId,
TfuCntrlReqInfo *cntrlReq));
S16 rgSCHUtlTfuRecpReq ARGS((Inst inst, S16 sapId,
TfuRecpReqInfo *recpReq));
S16 rgSCHUtlValidateTfuSap ARGS((Inst inst,SuId suId));
S16 rgSCHUtlAllocEventMem ARGS((Inst inst,Ptr *memPtr,Size memSize));
S16 rgSCHUtlGetEventMem ARGS((Ptr *ptr,Size len,Ptr memCpa));
S16 rgSCHUtlGetRlsHqAlloc ARGS((RgSchCellCb *cell));
S16 rgSCHUtlPutRlsHqAlloc ARGS((RgSchCellCb *cell));
S16 rgSCHUtlDlActvtUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
S16 rgSCHUtlUlActvtUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
Void rgSCHUtlHdlUlTransInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
CmLteTimingInfo timingInfo));
#ifdef TFU_UPGRADE
Void rgSCHUtlUpdACqiTrigWt ARGS((RgSchUeCb *ue,RgSchUeCellInfo *sCellInfo, uint8_t isAck));
#endif
/* Nprb indication at PHY for common Ch */
/* Corrected allocation for common channels */
S32 rgSCHUtlGetAllwdCchTbSz ARGS((uint32_t bo, uint8_t *nPrb, uint8_t *mcs
));
/* CR timer changes*/
S16 rgSCHUtlUpdtBo ARGS((RgSchCellCb *cell,
RgInfCmnBoRpt *staRsp));
S16 rgSCHUtlAddUeToCcchSduLst ARGS(
(RgSchCellCb *cell,
RgSchUeCb *ueCb));
#ifdef EMTC_ENABLE
S16 rgSCHUtlAddUeToEmtcCcchSduLst ARGS(
(RgSchCellCb *cell,
RgSchUeCb *ueCb));
S16 rgSCHRamRmvFrmEmtcRaInfoSchdLst ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
Void rgSCHRamEmtcDelRaCb ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
S16 rgSCHRamEmtcUpdtBo ARGS((RgSchCellCb *cell, RgSchRaCb *raCb,
RgInfCmnBoRpt *staRsp));
#endif
/* Added for SI Enhancement*/
#ifdef RGR_SI_SCH
Void rgSCHUtlPutSiInfo ARGS((RgSchCellCb *cell));
Void rgSCHUtlFreeWarningSiSeg ARGS((Region reg,Pool pool,
CmLListCp *siPduLst));
Void rgSCHUtlFreeWarningSiPdu ARGS((RgSchCellCb *cell));
Buffer *rgSCHUtlGetWarningSiPdu ARGS((RgSchCellCb *cell));
S16 rgSCHUtlGetMcsAndNPrb ARGS((RgSchCellCb *cell, uint8_t *nPrb, uint8_t *mcs, MsgLen *msgLen));
S16 rgSCHUtlCalMcsAndNPrb ARGS((RgSchCellCb *cell, uint8_t cfgType, MsgLen msgLen, uint8_t siId));
#endif/*RGR_SI_SCH*/
#ifdef LTE_TDD
S16 rgSCHUtlAllocUeANFdbkInfo ARGS((RgSchUeCb *ue,uint8_t servCellIdx));
Void rgSCHUtlDelUeANFdbkInfo ARGS((RgSchUeCb *ue,uint8_t servCellIdx));
S16 rgSCHUtlInitUeANFdbkInfo ARGS((RgSchTddANInfo *anInfo));
RgSchTddANInfo* rgSCHUtlGetUeANFdbkInfo ARGS((RgSchUeCb *ueCb, CmLteTimingInfo *timeInfo,uint8_t servCellIdx));
uint8_t rgSCHUtlGetDlSfIdx ARGS((RgSchCellCb *cell, CmLteTimingInfo *timeInfo));
Void rgSCHUtlPrachCfgInit ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg ));
Void rgSCHUtlGetNxtDlSfInfo ARGS((CmLteTimingInfo curDlTime, RgSchCellCb *cell, RgSchDlSf *dlSf, RgSchDlSf **nxtDlsf, CmLteTimingInfo *nxtDlTime));
Void rgSCHUtlGetPrevDlSfInfo ARGS((RgSchCellCb * cell, CmLteTimingInfo curDlTime, CmLteTimingInfo *prevDlTime, uint8_t *numSubfrm));
#endif
Void rgSCHCmnDlSch ARGS
((
RgSchCellCb *cell
));
Void rgSCHCmnSndCnsldtInfo ARGS
((
RgSchCellCb *cell
));
Void rgSCHCmnCnsldtSfAlloc ARGS
((
RgSchCellCb *cell
));
/* Added support for SPS*/
Void rgSCHCmnDlAllocFnlz ARGS
((
RgSchCellCb *cell
));
#ifdef LTEMAC_SPS
Void rgSCHUtlDlRelPdcchFbk ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
Bool isAck
));
Void rgSCHUtlDlProcAck ARGS((
RgSchCellCb *cell,
RgSchDlHqProcCb *hqP
));
S16 rgSCHUtlSpsRelInd ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb,
Bool isExplRel
));
Void rgSCHCmnDlSch ARGS
((
RgSchCellCb *cell
));
S16 rgSCHUtlSpsActInd ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb,
uint16_t spsSduSize
));
Void rgSCHUtlHdlCrcFailInd ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
CmLteTimingInfo timingInfo
));
Void rgSCHUtlHdlCrntiCE ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue
));
#endif /* LTEMAC_SPS*/
/******* : START *****/
S16 rgSCHUtlUlSfInit ARGS((
RgSchCellCb *cell,
RgSchUlSf *sf,
uint8_t idx,
uint8_t maxUePerSf
));
Void rgSCHUtlUlSfDeinit ARGS((
RgSchCellCb *cell,
RgSchUlSf *sf
));
RgSchUlAlloc *rgSCHUtlUlAllocGetHole ARGS((
RgSchUlSf *sf,
uint8_t numRb,
RgSchUlHole *hole
));
RgSchUlAlloc *rgSCHUtlUlAllocGetCompHole ARGS((
RgSchUlSf *sf,
RgSchUlHole *hole
));
RgSchUlAlloc *rgSCHUtlUlAllocGetPartHole ARGS((
RgSchUlSf *sf,
uint8_t numRb,
RgSchUlHole *hole
));
Void rgSCHUtlUlAllocRls ARGS((
RgSchUlSf *sf,
RgSchUlAlloc *alloc
));
/* UL_ALLOC_ENHANCEMENT */
Void rgSCHUtlUlAllocRelease ARGS((
RgSchUlAlloc *alloc
));
RgSchUlAlloc *rgSCHUtlUlAllocFirst ARGS((
RgSchUlSf *sf
));
RgSchUlAlloc *rgSCHUtlUlAllocNxt ARGS((
RgSchUlSf *sf,
RgSchUlAlloc *alloc
));
RgSchUlHole *rgSCHUtlUlHoleFirst ARGS((
RgSchUlSf *sf
));
RgSchUlHole *rgSCHUtlUlHoleNxt ARGS((
RgSchUlSf *sf,
RgSchUlHole *hole
));
RgSchUlAlloc *rgSCHUtlUlAllocGetAdjNxt ARGS((
RgSchUlAllocDb *db,
RgSchUlAlloc *prv
));
RgSchUlAlloc *rgSCHUtlUlAllocGetFirst ARGS((
RgSchUlAllocDb *db
));
Void rgSCHUtlUlHoleAddAlloc ARGS((
RgSchUlSf *sf,
RgSchUlAlloc *alloc
));
/* UL_ALLOC_ENHANCEMENT */
Void rgSCHUtlUlHoleAddAllocation ARGS((
RgSchUlAlloc *alloc
));
Void rgSCHUtlUlHoleJoin ARGS((
RgSchUlHoleDb *db,
RgSchUlHole *prv,
RgSchUlHole *nxt,
RgSchUlAlloc *alloc
));
Void rgSCHUtlUlHoleExtndRight ARGS((
RgSchUlHoleDb *db,
RgSchUlHole *prv,
RgSchUlAlloc *alloc
));
Void rgSCHUtlUlHoleExtndLeft ARGS((
RgSchUlHoleDb *db,
RgSchUlHole *nxt,
RgSchUlAlloc *alloc
));
Void rgSCHUtlUlHoleNew ARGS((
RgSchUlHoleDb *db,
RgSchUlAlloc *alloc
));
Void rgSCHUtlUlHoleUpdAllocLnks ARGS((
RgSchUlHole *hole,
RgSchUlAlloc *prvAlloc,
RgSchUlAlloc *nxtAlloc
));
Void rgSCHUtlUlHoleIns ARGS((
RgSchUlHoleDb *db,
RgSchUlHole *hole
));
Void rgSCHUtlUlHoleIncr ARGS((
RgSchUlHoleDb *db,
RgSchUlHole *hole
));
Void rgSCHUtlUlHoleDecr ARGS((
RgSchUlHoleDb *db,
RgSchUlHole *hole
));
Void rgSCHUtlUlHoleRls ARGS((
RgSchUlHoleDb *db,
RgSchUlHole *hole
));
S16 rgSCHUtlUlAllocMemInit ARGS((
RgSchCellCb *cell,
RgSchUlAllocMem *mem,
uint8_t maxAllocs
));
Void rgSCHUtlUlAllocMemDeinit ARGS((
RgSchCellCb *cell,
RgSchUlAllocMem *mem
));
S16 rgSCHUtlUlHoleMemInit ARGS((
RgSchCellCb *cell,
RgSchUlHoleMem *mem,
uint8_t maxHoles,
RgSchUlHole **holeRef
));
Void rgSCHUtlUlHoleMemDeinit ARGS((
RgSchCellCb *cell,
RgSchUlHoleMem *mem
));
RgSchUlAlloc *rgSCHUtlUlAllocMemGet ARGS((
RgSchUlAllocMem *mem
));
Void rgSCHUtlUlAllocMemRls ARGS((
RgSchUlAllocMem *mem,
RgSchUlAlloc *alloc
));
RgSchUlHole *rgSCHUtlUlHoleMemGet ARGS((
RgSchUlHoleMem *mem
));
Void rgSCHUtlUlHoleMemRls ARGS((
RgSchUlHoleMem *mem,
RgSchUlHole *hole
));
RgSchUlAlloc *rgSCHUtlUlGetSpfcAlloc ARGS((
RgSchUlSf *sf,
uint8_t startSb,
uint8_t numSb
));
/******* : END *****/
/* DRX function declarations */
S16 rgSCHDrxCellCfg ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg));
Void rgSCHDrxCellDel ARGS((RgSchCellCb *cell));
S16 rgSCHDrxUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgrUeCfg *ueCfg));
#ifdef RGR_V2
S16 rgSCHDrxUeReCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
RgrUeRecfg *ueCfg));
#endif
S16 rgSCHDrxUeDel ARGS((RgSchCellCb *cell,RgSchUeCb *ue));
Void rgSCHDrxTtiInd ARGS ((RgSchCellCb *cell));
S16 rgSCHDrxSfAlloc ARGS ((RgSchCellCb *cellCb, RgSchDlSf
*dlSf));
S16 rgSCHDrxDlTrnsFail ARGS((RgSchCellCb *cell, RgSchDlHqProcCb
*dlHq));
Void rgSCHDrxDedRa ARGS((RgSchCellCb *cellCb, RgSchUeCb* ueCb));
S16 rgSCHDrxSrInd ARGS((RgSchCellCb *cell,RgSchUeCb *ue));
Void rgSCHDrxStrtInActvTmr ARGS((RgSchCellCb *cell,
CmLListCp *ueLst,
uint8_t direction));
S16 rgSCHUtlGetDrxSchdUesInDl ARGS((RgSchCellCb *cellCb,
RgSchUeCb *ueCb,
RgSchDlHqProcCb *dlHq,
RgInfUeAlloc *allocInfo,
CmLListCp *dlDrxInactvTmrLst,
CmLListCp *dlInActvLst,
CmLListCp *ulInActvLst));
Void rgSCHDrxStartHarqRTTTmr ARGS((RgSchCellCb *cell,
RgSchDlHqProcCb *hqP,
uint8_t tbCnt));
Void rgSCHDrxUeHqReset ARGS((RgSchCellCb *cell,
RgSchUeCb *ue,
RgSchDlHqEnt *hqE,
uint8_t cellIdx));
#ifdef TFU_UPGRADE
#ifdef LTE_TDD
const RgSchTddCellSpSrsSubfrmTbl rgSchTddCellSpSrsSubfrmTbl;
#else
const RgSchFddCellSpSrsSubfrmTbl rgSchFddCellSpSrsSubfrmTbl;
#endif
#endif
#ifdef LTEMAC_HDFDD
S16 rgSCHHdFddUeCfg ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb,
Bool hdFdd));
S16 rgSCHHdFddUeDel ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb));
Void rgSCHCmnHdFddPtUlMrk ARGS((
RgSchCellCb *cellCb));
Void rgSCHCmnHdFddChkUlAllow ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb,
uint8_t *flag));
Void rgSCHCmnHdFddChkDlAllow ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb,
Bool *flag));
Void rgSCHCmnHdFddChkNackAllow ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb,
CmLteTimingInfo timInfo,
Bool *flag));
Void rgSCHCmnHdFddUpdULMark ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb));
Void rgSCHCmnHdFddUpdDLMark ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb));
Void rgSCHHdFddGetSfn ARGS((
uint16_t *sfn,
CmLteTimingInfo timeInfo,
S16 offset));
#endif /* ifdef LTEMAC_HDFDD */
/* ccpu00117452 - MOD - Changed macro name from
RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
#ifdef RGR_CQI_REPT
S16 rgSCHUtlRgrStaInd ARGS((
RgSchCellCb *cell,
RgrStaIndInfo *rgrSta
));
S16 rgSCHUtlFillSndStaInd ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
RgrStaIndInfo *staInfo,
uint8_t numCqiRept
));
#endif /* End of RGR_CQI_REPT */
S16 rgSCHUtlRgrUeStaInd ARGS((
RgSchCellCb *cell,
RgrUeStaIndInfo *rgrUeSta
));
S16 rgSCHUtlFillSndUeStaInd ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
RgrUeStaIndInfo *ueStaInfo
));
/* LTE_ADV_FLAG_REMOVED_START */
S16 rgSCHUtlRgrLoadInfInd ARGS((
RgSchCellCb *cell,
RgrLoadInfIndInfo *rgrLoadInf
));
/* LTE_ADV_FLAG_REMOVED_END */
#ifdef LTE_ADV
#ifdef TFU_UPGRADE
TfuAckNackMode rgSchUtlGetFdbkMode ARGS((
RgrSchFrmt1b3TypEnum fdbkType
));
TfuAckNackMode rgSchUtlGetFdbkMode ARGS((
RgrSchFrmt1b3TypEnum fdbkType
));
#endif /*TFU_UPGRADE */
#endif /* LTE_ADV */
/* FIX */
Void rgSCHUtlRlsRnti ARGS((
RgSchCellCb *cellCb,
RgSchRntiLnk *rntiLnk,
Bool ueIdChngd,
CmLteRnti newRnti
));
S16 rgSCHUtlRgmBndCfm ARGS((
Inst instId,
SuId suId,
uint8_t status
));
Void rgSCHDhmDelHqEnt ARGS((
RgSchCellCb *cell,
RgSchDlHqEnt **hqE
));
Void rgSCHDhmAssgnUeHqEntFrmRaCb ARGS((
RgSchUeCb *ue,
RgSchRaCb *raCb
));
Void rgSCHUtlReTxTa ARGS((
RgSchCellCb *cellCb,
RgSchUeCb *ueCb));
/* LTE_ADV_FLAG_REMOVED_START */
Void rgSchSFRTotalPoolFree ARGS((
RgSchSFRTotalPoolInfo *sfrTotalPoolInfo,
RgSchCellCb *cell));
Void rgSchDSFRPwrCheck ARGS((
RgSchDlSf *sf,
Bool *isAllUePwrHigh));
/* LTE_ADV_FLAG_REMOVED_END */
S16 rgSCHUtlUpdAvgPrbUsage ARGS((
RgSchCellCb *cell
));
uint8_t rgSchUtlCfg0ReTxIdx ARGS((
RgSchCellCb *cell,
CmLteTimingInfo phichTime,
uint8_t hqFdbkIdx
));
S16 rgSCHUtlBuildNSendLcgReg ARGS((
RgSchCellCb *cell,
CmLteRnti crnti,
uint8_t lcgId,
Bool isGbr
));
Void rgSCHUtlPdcchInit ARGS((
RgSchCellCb *cell,
RgSchDlSf *subFrm,
uint16_t nCce));
Void rgSCHDynCfiReCfg ARGS((
RgSchCellCb *cell,
Bool isDynCfiEnb
));
Void rgSchUtlCalcTotalPrbReq ARGS((RgSchCellCb *cell,
RgSchUeCb *ue,
uint32_t bo,
uint32_t *prbReqrd));
uint8_t rgSchUtlGetNumSbs ARGS((
RgSchCellCb *cell,
RgSchUeCb *ue,
uint32_t *numSbs
));
uint8_t rgSchUtlSortInsUeLst ARGS((
RgSchCellCb *cell,
CmLListCp *ueLst,
CmLList *node,
uint8_t subbandRequired
));
S16 rgSCHUtlResetCpuOvrLdState ARGS((
RgSchCellCb *cell,
uint8_t cnrtCpuOvrLdIns
));
Void rgSCHUtlCpuOvrLdAdjItbsCap ARGS((
RgSchCellCb *cell
));
#ifdef TFU_UPGRADE
S16 rgSCHTomUtlPcqiSbCalcBpIdx ARGS((
CmLteTimingInfo crntTimInfo,
RgSchUeCb *ueCb,
RgSchUePCqiCb *cqiCb
));
#ifdef LTE_ADV
S16 rgSCHUtlSCellHndlCqiCollsn ARGS((
RgSchUePCqiCb *cqiCb
));
S16 rgSCHUtlSCellHndlRiCollsn ARGS((
RgSchUePCqiCb *cqiCb
));
#endif/*LTE_ADV*/
#endif/*TFU_UPGRADE*/
Void rgSCHTomUtlGetTrigSet ARGS((
RgSchCellCb *cell,
RgSchUeCb *ueCb,
uint8_t cqiReq,
uint8_t *triggerSet
));
Void rgSCHUtlUpdUeDciSize ARGS((
RgSchCellCb *cell,
RgSchUeCb *ueCb,
Bool isCsi2Bit
));
Void rgSCHUtlCalcDciSizes ARGS((
RgSchCellCb *cell
));
Void rgSchCmnPreDlSch ARGS ((
RgSchCellCb **cell,
uint8_t nCell,
RgSchCellCb **cellLst
));
Void rgSchCmnPstDlSch ARGS ((
RgSchCellCb *cell
));
uint8_t rgSCHCmnGetBiIndex ARGS ((
RgSchCellCb *cell,
uint32_t ueCount
));
uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __SCH__ */
/**********************************************************************
End of file
**********************************************************************/