1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /********************************************************************20**
25 Desc: This file Contains the Data structures for Common LTE
29 *********************************************************************21*/
36 #endif /*__cplusplus*/
39 @brief CM_LTE Interface File (cm_lte.h)
42 #define CM_LTE_MAX_LOGCH_PER_RB 2 /*!< Maximum Logical Channel per RB */
44 /* Mode of RLC entity */
45 #define CM_LTE_MODE_TM 1 /*!< TM mode */
46 #define CM_LTE_MODE_UM 2 /*!< UM mode */
47 #define CM_LTE_MODE_AM 3 /*!< AM mode */
49 /* Logical Channel Type */
50 #define CM_LTE_LCH_BCCH 1 /*!< BCCH Logical Channel */
51 #define CM_LTE_LCH_PCCH 2 /*!< PCCH Logical Channel */
52 #define CM_LTE_LCH_CCCH 3 /*!< CCCH Logical Channel */
53 #define CM_LTE_LCH_DTCH 4 /*!< DTCH Logical Channel */
54 #define CM_LTE_LCH_DCCH 5 /*!< DCCH Logical Channel */
56 /* Transport Channel Type */
57 #define CM_LTE_TRCH_BCH 1 /*!< BCH Transport Channel */
58 #define CM_LTE_TRCH_PCH 2 /*!< PCH Transport Channel */
59 #define CM_LTE_TRCH_DL_SCH 3 /*!< DL-SCH Transport Channel */
60 #define CM_LTE_TRCH_RACH 4 /*!< RACH Transport Channel */
61 #define CM_LTE_TRCH_UL_SCH 5 /*!< UL-SCH Transport Channel */
63 #define CM_LTE_DIR_UL 1 /*!< Uplink Direction */
64 #define CM_LTE_DIR_DL 2 /*!< Downlink Direction */
65 #define CM_LTE_DIR_DL_UL 3 /*!< Bi-Directional */
68 #define CM_LTE_SRB 0 /*!< Signalling Radio Bearer */
69 #define CM_LTE_DRB 1 /*!< Data Radio Bearer */
70 #define CM_MAX_UE_CAT_SUPP 8 /*!< CA dev changes*/
71 #define CM_LTE_MAX_CELLS 8 /*!< Max Number of Cells. One primary
72 seven secondary cells */
74 #define CM_MAX_CPU_CORES 10 /*!< Maximum number of cores */
75 #define CM_L2_CPU_UTIL 0 /*!< Get L2 CPU Utilization */
76 #define CM_L3_CPU_UTIL 1 /*!< Get L3 CPU Utilization */
77 #define CM_L2_MEM_UTIL_AREAIDX 0 /*!< Get L2 MEM utilization */
78 #define CM_L3_MEM_UTIL_AREAIDX 1 /*!< Get L3 MEM utilization */
79 #define CM_MEM_CPU_UITL_INFO_TMR_VAL 1000 /*!< timer value */
80 #ifdef TENB_T2K3K_SPECIFIC_CHANGES
81 #define CM_NUM_L2_CORES 1 /*!< number of L2 cores */
82 #define CM_NUM_L3_CORES 1 /*!< number of L3 cores */
84 #define CM_NUM_L2_CORES 4 /*!< number of L2 cores */
85 #define CM_NUM_L3_CORES 1 /*!< number of L3 cores */
88 /*#define TTI_THRESHOLD_VALUE 800*/
90 #define displayTtiCounters(cellId) \
91 RLOG_ARG4(L_ALWAYS,DBG_CELLID, (cellId),"avgTtiProcessingTime = [%d] maxTtiProcessingTime = [%d] ttiThresholdExceedCount = [%d] ttiStretchCount = [%d]",(ttiProc.totTtiProcessingTime/ttiProc.numOfTti),ttiProc.maxTtiProcessingTime,ttiProc.ttiThresholdExceedCount,ttiProc.ttiStretchCount)
96 #endif /* __cplusplus */
97 #endif /* __CM_LTE_H__ */
99 /********************************************************************30**
102 **********************************************************************/