1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for rach handling functions
29 **********************************************************************/
32 @brief This file implements the rach handling.
34 #include "common_def.h"
40 #include "du_app_mac_inf.h"
41 #include "mac_sch_interface.h"
43 #include "sch_utils.h"
45 SchCb schCb[SCH_MAX_INST];
46 uint8_t puschDeltaTable[MAX_MU_PUSCH];
49 * @brief calculate ra-rnti function.
53 * Function : calculateRaRnti
55 * This function calculates ra-rnti
57 * @param[in] symbol index
58 * @param[in] slot index
59 * @param[in] frequency index
62 uint16_t calculateRaRnti(uint8_t symbolIdx, uint8_t slotIdx, uint8_t freqIdx)
65 uint8_t ulCarrierIdx = 0; /* Uplink carrier used for MSG1 transmission. 0:NUL carrier; 1:SUL carrier */
67 /* Refer to spec 38.321, section 5.1.3 */
68 raRnti = (1 + symbolIdx + (14*slotIdx) + (14*80*freqIdx) + (14*80*8*ulCarrierIdx));
73 * @brief create raCb function.
77 * Function : createSchRaCb
79 * This function create raCb
82 * @param[in] shed instance
85 void createSchRaCb(uint16_t tcrnti, Inst schInst)
89 GET_UE_IDX(tcrnti, ueIdx);
90 schCb[schInst].cells[schInst]->raCb[ueIdx -1].tcrnti = tcrnti;
94 * @brief resource allocation for msg3 PUSCH
98 * Function : schAllocMsg3Pusch
100 * This function handles msg3 PUSCH allocation
102 * @param[in] Inst schInst, SCH instance
103 * @param[in] slot, current slot
104 * @param[out] msg3StartRb
105 * @param[out] msg3NumRb
108 SchPuschInfo* schAllocMsg3Pusch(Inst schInst, uint16_t slot, uint16_t crnti, uint16_t msg3SlotAlloc)
110 SchCellCb *cell = NULLP;
111 SchUlSlotInfo *schUlSlotInfo = NULLP;
112 uint8_t startSymb = 0;
118 uint8_t numPdschSymbols= 14;
121 cell = schCb[schInst].cells[schInst];
122 startSymb = cell->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[0].startSymbol;
123 symbLen = cell->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[0].symbolLength;
125 startRb = cell->schUlSlotInfo[msg3SlotAlloc]->puschCurrentPrb;
126 tbSize = schCalcTbSize(8); /* 6 bytes msg3 and 2 bytes header */
127 numRb = schCalcNumPrb(tbSize, mcs, numPdschSymbols);
129 /* allocating 1 extra RB for now */
131 /* increment PUSCH PRB */
132 cell->schUlSlotInfo[msg3SlotAlloc]->puschCurrentPrb += numRb;
134 for(idx=startSymb; idx<symbLen; idx++)
136 cell->schUlSlotInfo[msg3SlotAlloc]->assignedPrb[idx] = startRb + numRb;
138 schUlSlotInfo = cell->schUlSlotInfo[msg3SlotAlloc];
140 SCH_ALLOC(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
141 if(!schUlSlotInfo->schPuschInfo)
143 DU_LOG("\nERROR --> SCH : Memory allocation failed in schAllocMsg3Pusch");
146 tbSize = 0; /* since nPrb has been incremented, recalculating tbSize */
147 tbSize = schCalcTbSizeFromNPrb(numRb, mcs, numPdschSymbols);
148 tbSize = tbSize/8;/*bits to byte conversion*/
149 schUlSlotInfo->schPuschInfo->crnti = crnti;
150 schUlSlotInfo->schPuschInfo->harqProcId = SCH_HARQ_PROC_ID;
151 schUlSlotInfo->schPuschInfo->resAllocType = SCH_ALLOC_TYPE_1;
152 schUlSlotInfo->schPuschInfo->fdAlloc.startPrb = startRb;
153 schUlSlotInfo->schPuschInfo->fdAlloc.numPrb = numRb;
154 schUlSlotInfo->schPuschInfo->tdAlloc.startSymb = startSymb;
155 schUlSlotInfo->schPuschInfo->tdAlloc.numSymb = symbLen;
156 schUlSlotInfo->schPuschInfo->tbInfo.qamOrder = 2; /* QPSK modulation */
157 schUlSlotInfo->schPuschInfo->tbInfo.mcs = mcs;
158 schUlSlotInfo->schPuschInfo->tbInfo.mcsTable = SCH_MCS_TABLE_QAM_64;
159 schUlSlotInfo->schPuschInfo->tbInfo.ndi = 1; /* new transmission */
160 schUlSlotInfo->schPuschInfo->tbInfo.rv = 0;
161 schUlSlotInfo->schPuschInfo->tbInfo.tbSize = tbSize; /*Considering 2 PRBs */
162 schUlSlotInfo->schPuschInfo->dmrsMappingType = DMRS_MAP_TYPE_A; /* Setting Type-A */
163 schUlSlotInfo->schPuschInfo->nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
164 schUlSlotInfo->schPuschInfo->dmrsAddPos = DMRS_ADDITIONAL_POS;
166 return schUlSlotInfo->schPuschInfo;
170 * @brief Processes any pending RA request
174 * Function : schProcessRaReq
176 * This function process pending RA request
178 * @param[in] Current timing of the cell
181 void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cell)
184 SchPuschInfo *msg3PuschInfo;
185 RarInfo *rarInfo = NULLP;
187 uint8_t k2Index = 0, k2 = 0;
189 uint16_t rarSlot = 0;
190 uint16_t msg3Slot = 0;
192 uint16_t slotIdx = 0;
195 while(ueIdx < MAX_NUM_UE)
197 if(cell->raReq[ueIdx] == NULLP)
203 //puschMu = cell->cellCfg.puschMu;
204 delta = puschDeltaTable[puschMu];
205 k2 = cell->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].k2;
207 /* RAR will sent with a delay of RAR_DELAY */
208 rarSlot = (currTime.slot + RAR_DELAY + PHY_DELTA_DL) % cell->numSlots;
210 for(slotIdx=0; slotIdx<cell->numSlots;slotIdx++)
212 /* Slot allocation for msg3 based on 38.214 section 6.1.2.1 */
213 msg3Slot = (rarSlot+delta+k2)%cell->numSlots;
215 if((schGetSlotSymbFrmt(rarSlot, cell->slotFrmtBitMap) != DL_SLOT) &&\
216 (schGetSlotSymbFrmt(msg3Slot, cell->slotFrmtBitMap) != UL_SLOT))
218 rarSlot = (rarSlot + 1) % cell->numSlots;
223 if(slotIdx>=cell->numSlots)
225 DU_LOG("\nERROR --> SCH : NO Slot for Msg2 with Msg3 Grant\n");
229 /* Slot allocation for msg3 based on 38.214 section 6.1.2.1 */
230 msg3Slot = rarSlot + k2 + delta;
231 msg3Slot = msg3Slot % cell->numSlots;
234 SchDlSlotInfo *schDlSlotInfo = cell->schDlSlotInfo[rarSlot]; /* RAR will sent in the next slot */
236 /* Allocate the rarInfo, this pointer will be checked at schProcessSlotInd function */
237 SCH_ALLOC(rarInfo, sizeof(RarInfo));
240 DU_LOG("\nERROR --> SCH : Memory Allocation failed for rarInfo");
244 schDlSlotInfo->rarInfo = rarInfo;
246 /* create raCb at SCH */
247 createSchRaCb(cell->raReq[ueIdx]->rachInd->crnti, cell->instIdx);
249 /* allocate resources for msg3 */
250 msg3PuschInfo = schAllocMsg3Pusch(cell->instIdx, rarSlot, cell->raReq[ueIdx]->rachInd->crnti, msg3Slot);
254 rarInfo->raRnti = cell->raReq[ueIdx]->raRnti;
255 rarInfo->tcrnti = cell->raReq[ueIdx]->rachInd->crnti;
256 rarInfo->RAPID = cell->raReq[ueIdx]->rachInd->preambleIdx;
257 rarInfo->ta = cell->raReq[ueIdx]->rachInd->timingAdv;
258 rarInfo->ulGrant.bwpSize = cell->cellCfg.schInitialUlBwp.bwp.freqAlloc.numPrb;
259 /* Spec 38.213, section 8.2, 0 : MSG3 PUSCH will be transmitted without frequency hopping */
260 rarInfo->ulGrant.freqHopFlag = 0;
261 rarInfo->ulGrant.msg3FreqAlloc.startPrb = msg3PuschInfo->fdAlloc.startPrb;
262 rarInfo->ulGrant.msg3FreqAlloc.numPrb = msg3PuschInfo->fdAlloc.numPrb;
263 rarInfo->ulGrant.k2Index = k2Index;
264 rarInfo->ulGrant.mcs = msg3PuschInfo->tbInfo.mcs;
265 rarInfo->ulGrant.tpc = 3; /* TODO : Check appropriate value to be filled */
266 /* Spec 38.213, section 8.2 : In a contention based random access
267 * procedure, the CSI request field is reserved. */
268 rarInfo->ulGrant.csiReq = 0;
271 SCH_FREE(cell->raReq[ueIdx]->rachInd, sizeof(RachIndInfo));
272 SCH_FREE(cell->raReq[ueIdx], sizeof(SchRaReq));
275 } /* End of while(ueIdx < MAX_NUM_UE) */
279 * @brief process rach indication function.
283 * Function : schProcessRachInd
285 * This function process rach indication
287 * @param[in] rachInd parameters
288 * @param[in] shed instance
291 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst)
293 SchCellCb *cell = schCb[schInst].cells[schInst];
294 SchRaReq *raReq = NULLP;
299 SCH_ALLOC(raReq, sizeof(SchRaReq));
302 DU_LOG("\nERROR --> SCH : Memory allocation failure in schProcessRachInd");
303 SCH_FREE(rachInd, sizeof(RachIndInfo));
307 /* calculate the ra-rnti value */
308 raReq->raRnti = calculateRaRnti(rachInd->symbolIdx, rachInd->slotIdx, rachInd->freqIdx);
309 raReq->rachInd = rachInd;
310 raReq->winStartTime.sfn = rachInd->timingInfo.sfn;
311 raReq->winStartTime.slot = rachInd->timingInfo.slot;
313 /* Converting window size from ms to number of slots */
314 slotDuration = (1 / pow(2, cell->cellCfg.numerology));
315 winNumSlots = (float)cell->cellCfg.schRachCfg.raRspWindow / slotDuration;
317 /* Adding window size to window start time to get window end time */
318 ADD_DELTA_TO_TIME(raReq->winStartTime, raReq->winEndTime, winNumSlots);
320 /* Storing RA request in cellCb */
321 GET_UE_IDX(rachInd->crnti, ueIdx);
322 cell->raReq[ueIdx] = raReq;
328 * @brief fill RAR info function.
332 * Function : calculateRaRnti
334 * This function fills pdcch and pdsch info for RAR
336 * @param[in] rar Allocation info
339 * @param[in] offset to pointA to determine freq alloc
342 uint8_t schFillRar(RarAlloc *rarAlloc, uint16_t raRnti, uint16_t pci, uint8_t offsetPointA, \
343 bool ssbPresent, bool sib1Present)
346 uint8_t coreset0Idx = 0;
348 uint8_t firstSymbol = 0;
349 uint8_t numSymbols = 0;
351 uint8_t FreqDomainResource[6] = {0};
353 uint8_t mcs = 4; /* MCS fixed to 4 */
355 SchBwpDlCfg *initialBwp = &schCb[inst].cells[inst]->cellCfg.schInitialDlBwp;
356 PdcchCfg *pdcch = &rarAlloc->rarPdcchCfg;
357 PdschCfg *pdsch = &rarAlloc->rarPdschCfg;
358 BwpCfg *bwp = &rarAlloc->bwp;
359 FreqDomainAlloc *sib1PdschFreqAlloc = NULL;
361 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
363 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
364 numRbs = coresetIdxTable[coreset0Idx][1];
365 numSymbols = coresetIdxTable[coreset0Idx][2];
366 offset = coresetIdxTable[coreset0Idx][3];
368 /* calculate time domain parameters */
369 // note: since slot value is made sl1, RAR can be sent at all slots
370 uint16_t mask = 0x2000;
371 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
373 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
379 /* calculate the PRBs */
380 freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
383 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
384 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
385 bwp->subcarrierSpacing = initialBwp->bwp.scs;
386 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
388 /* fill the PDCCH PDU */
389 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
390 pdcch->coresetCfg.durationSymbols = numSymbols;
391 memcpy(pdcch->coresetCfg.freqDomainResource, FreqDomainResource, FREQ_DOM_RSRC_SIZE);
392 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
393 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
394 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
395 pdcch->coresetCfg.coreSetType = 0;
396 pdcch->coresetCfg.shiftIndex = pci;
397 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
399 pdcch->dci.rnti = raRnti; /* RA-RNTI */
400 pdcch->dci.scramblingId = pci;
401 pdcch->dci.scramblingRnti = 0;
402 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
403 pdcch->dci.aggregLevel = 4;
404 pdcch->dci.beamPdcchInfo.numPrgs = 1;
405 pdcch->dci.beamPdcchInfo.prgSize = 1;
406 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
407 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
408 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
409 pdcch->dci.txPdcchPower.powerValue = 0;
410 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
411 pdcch->dci.pdschCfg = pdsch;
413 /* fill the PDSCH PDU */
415 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
416 pdsch->rnti = raRnti; /* RA-RNTI */
418 pdsch->numCodewords = 1;
419 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
421 pdsch->codeword[cwCount].targetCodeRate = 308;
422 pdsch->codeword[cwCount].qamModOrder = 2;
423 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
424 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
425 pdsch->codeword[cwCount].rvIndex = 0;
426 /* RAR PDU length and FAPI payload header length */
427 tbSize = schCalcTbSize(RAR_PAYLOAD_SIZE + TX_PAYLOAD_HDR_LEN);
428 pdsch->codeword[cwCount].tbSize = tbSize;
430 pdsch->dataScramblingId = pci;
431 pdsch->numLayers = 1;
432 pdsch->transmissionScheme = 0;
434 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
435 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
436 pdsch->dmrs.dlDmrsScramblingId = pci;
437 pdsch->dmrs.scid = 0;
438 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
439 pdsch->dmrs.dmrsPorts = 0;
440 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
441 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
442 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
443 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
444 /* The RB numbering starts from coreset0 */
445 pdsch->pdschFreqAlloc.freqAlloc.startPrb = PDSCH_START_RB;
448 /* PDSCH is always above SSB */
449 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1;
453 /* Must not overlap with SIB1 */
454 sib1PdschFreqAlloc = &schCb[inst].cells[inst]->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc;
455 pdsch->pdschFreqAlloc.freqAlloc.startPrb = sib1PdschFreqAlloc->startPrb + sib1PdschFreqAlloc->numPrb + 1;
457 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, \
458 initialBwp->pdschCommon.timeDomRsrcAllocList[0].lengthSymbol);
459 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
460 pdsch->pdschTimeAlloc.timeAlloc.startSymb = initialBwp->pdschCommon.timeDomRsrcAllocList[0].startSymbol;
461 pdsch->pdschTimeAlloc.timeAlloc.numSymb = initialBwp->pdschCommon.timeDomRsrcAllocList[0].lengthSymbol;
462 pdsch->beamPdschInfo.numPrgs = 1;
463 pdsch->beamPdschInfo.prgSize = 1;
464 pdsch->beamPdschInfo.digBfInterfaces = 0;
465 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
466 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
467 pdsch->txPdschPower.powerControlOffset = 0;
468 pdsch->txPdschPower.powerControlOffsetSS = 0;
473 /**********************************************************************
475 **********************************************************************/