src/5gnrsch/sch_common.c

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17  *******************************************************************************/
  18
  19 /************************************************************************
  20
  21 Name:     5G NR SCH layer
  22
  23 Type:     C source file
  24
  25 Desc:     C source code for Entry point fucntions
  26
  27 File:     sch_common.c
  28
  29  **********************************************************************/
  30
  31 /** @file sch_common.c
  32   @brief This module performs common scheduling
  33  */
  34 #include "common_def.h"
  35 #include "tfu.h"
  36 #include "lrg.h"
  37
  38 #include "tfu.x"
  39 #include "lrg.x"
  40 #include "du_log.h"
  41 #include "du_app_mac_inf.h"
  42 #include "mac_sch_interface.h"
  43 #include "sch.h"
  44 #include "sch_utils.h"
  45
  46 SchCb schCb[SCH_MAX_INST];
  47 uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
  48 uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
  49 uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
  50
  51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
  52 {
  53    packSchMacUlSchInfo,
  54    MacProcUlSchInfo,
  55    packSchMacUlSchInfo
  56 };
  57
  58 /**
  59  * @brief common resource allocation for SSB
  60  *
  61  * @details
  62  *
  63  *     Function : schBroadcastAlloc
  64  *
  65  *     This function handles common scheduling for DL
  66  *
  67  *  @param[in]  SchCellCb *cell, cell cb
  68  *  @param[in]  DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
  69  *  @return  void
  70  **/
  71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
  72       uint16_t slot)
  73 {
  74    /* schedule SSB */
  75    uint8_t ssbStartPrb, ssbStartSymb, idx;
  76    SchDlSlotInfo *schDlSlotInfo;
  77    SsbInfo ssbInfo;
  78
  79    schDlSlotInfo = cell->schDlSlotInfo[slot];
  80
  81    if(dlBrdcstAlloc->ssbTrans)
  82    {
  83       ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; //+Kssb
  84       ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
  85                                                                                 supporting only 1 ssb beam */
  86
  87       /* Assign interface structure */
  88       for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
  89       {
  90          ssbInfo.ssbIdx              = idx;
  91          ssbInfo.fdAlloc.startPrb    = ssbStartPrb;
  92          ssbInfo.fdAlloc.numPrb      = SCH_SSB_NUM_PRB;
  93          ssbInfo.tdAlloc.startSymb   = ssbStartSymb;
  94          ssbInfo.tdAlloc.numSymb     = SCH_SSB_NUM_SYMB;
  95          dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
  96          schDlSlotInfo->ssbInfo[idx] = ssbInfo;
  97       }
  98
  99       schDlSlotInfo->ssbPres = true;
 100       schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
 101       for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
 102       {
 103          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
 104       }
 105    }
 106
 107    /* SIB1 allocation */
 108    if(dlBrdcstAlloc->sib1Trans)
 109    {
 110       uint16_t tbSize         = 0;
 111       uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 112       uint8_t mcs             = 4;  /* MCS fixed to 4 */
 113       uint8_t numSib1Prb      = 0;
 114       schDlSlotInfo->sib1Pres = true;
 115
 116       tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
 117       numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
 118       for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
 119       {
 120          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
 121       }
 122       memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
 123       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
 124       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
 125       dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
 126    }
 127    return ROK;
 128 }
 129
 130 /*******************************************************************
 131  *
 132  * @brief Handles sending UL scheduler info to MAC
 133  *
 134  * @details
 135  *
 136  *    Function : sendUlSchInfoToMac
 137  *
 138  *    Functionality:
 139  *     Sends UL Sch info to MAC from SCH
 140  *
 141  * @params[in]
 142  * @return ROK     - success
 143  *         RFAILED - failure
 144  *
 145  * ****************************************************************/
 146 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
 147 {
 148    Pst pst;
 149
 150    memset(&pst, 0, sizeof(Pst));
 151    FILL_PST_SCH_TO_MAC(pst, inst);
 152    pst.event = EVENT_UL_SCH_INFO;
 153
 154    return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
 155 }
 156 /**
 157  * @brief resource allocation for PRACH
 158  *
 159  * @details
 160  *
 161  *     Function : schPrachResAlloc
 162  *
 163  *     This function handles PRACH allocation
 164  *
 165  *  @param[in]  SchCellCb *cell, cell cb
 166  *  @param[in]  UlSchedInfo *ulSchedInfo, UL scheduling info
 167  *  @return  void
 168  **/
 169 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
 170 {
 171    uint8_t  puschScs;
 172    uint8_t  numPrachRb = 0;
 173    uint8_t  numRa = 0;
 174    uint8_t  freqStart = 0;
 175    uint8_t  prachCfgIdx = 0;
 176    uint8_t  prachFormat = 0;
 177    uint8_t  x = 0;
 178    uint8_t  y = 0;
 179    uint16_t prachSubframe = 0;
 180    uint8_t  prachStartSymbol = 0;
 181    uint8_t  prachOcas = 0;
 182    uint8_t  dataType = 0;
 183    uint8_t  idx = 0;
 184    uint8_t  subFrame = 0;
 185    SchUlSlotInfo *schUlSlotInfo = NULLP;
 186
 187    puschScs      = cell->cellCfg.schInitialUlBwp.bwp.scs;
 188    schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
 189    prachCfgIdx   = cell->cellCfg.schRachCfg.prachCfgIdx;
 190
 191    /* derive the prachCfgIdx table paramters */
 192    x                = prachCfgIdxTable[prachCfgIdx][1];
 193    y                = prachCfgIdxTable[prachCfgIdx][2];
 194    prachSubframe    = prachCfgIdxTable[prachCfgIdx][3];
 195
 196    if((prachOccasionTimingInfo.sfn%x) == y)
 197    {
 198 #ifdef NR_TDD
 199       subFrame = prachOccasionTimingInfo.slot/2;
 200 #else
 201       subFrame = prachOccasionTimingInfo.slot;
 202 #endif
 203       /* check for subFrame number */
 204       if ((1 << subFrame) & prachSubframe)
 205       {
 206          /* prach ocassion present in this subframe */
 207 #ifdef NR_TDD
 208          if(UL_SLOT != schGetSlotSymbFrmt(prachOccasionTimingInfo.slot, cell->slotFrmtBitMap))
 209          {
 210             DU_LOG("\nERROR  --> SCH : PrachCfgIdx %d doesn't support UL slot", prachCfgIdx);
 211          }
 212          else
 213 #endif
 214          {
 215             prachFormat      = prachCfgIdxTable[prachCfgIdx][0];
 216             prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
 217             prachOcas        = prachCfgIdxTable[prachCfgIdx][6];
 218
 219             /* freq domain resource determination for RACH*/
 220             freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
 221             /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
 222              * where M is given by msg1Fdm */
 223             numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
 224             for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
 225             {
 226                if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
 227                {
 228                   if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
 229                   {
 230                      if(numRbForPrachTable[idx][2] == puschScs)
 231                      {
 232                         break;
 233                      }
 234                   }
 235                }
 236             }
 237             numPrachRb = numRbForPrachTable[idx][3];
 238             dataType |= SCH_DATATYPE_PRACH;
 239             /* Considering first slot in the frame for PRACH */
 240             idx = 0;
 241             schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
 242          }
 243          ulSchedInfo->dataType = dataType;
 244          /* prach info */
 245          ulSchedInfo->prachSchInfo.numPrachOcas   = prachOcas;
 246          ulSchedInfo->prachSchInfo.prachFormat    = prachFormat;
 247          ulSchedInfo->prachSchInfo.numRa          = numRa;
 248          ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
 249          DU_LOG("\nINFO  --> SCH : RACH occassion set for slot %d", prachOccasionTimingInfo.slot);
 250       }
 251    }
 252 }
 253
 254
 255 /**
 256  * @brief Function to fill Pucch Format 0
 257  *
 258  * @details
 259  *
 260  *     Function : fillPucchFormat0
 261  *
 262  *     Function to fill Pucch format 0
 263  *
 264  *  @param[in]  SchPucchInfo pointer, SchPucchResrcInfo pointer
 265  *  @return  void
 266  **/
 267
 268 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
 269 {
 270    if(resrcInfo->SchPucchFormat.format0)
 271    {
 272       ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 273       ulSchedPucch->pucchFormat  = PUCCH_FORMAT_0;
 274       ulSchedPucch->initialCyclicShift =  resrcInfo->SchPucchFormat.format0->initialCyclicShift;
 275       ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
 276       ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
 277    }
 278 }
 279
 280 /**
 281  * @brief Function to fill Pucch Format 1
 282  *
 283  * @details
 284  *
 285  *     Function : fillPucchFormat1
 286  *
 287  *     Function to fill Pucch format 1
 288  *
 289  *  @param[in]  SchPucchInfo pointer, SchPucchResrcInfo pointer
 290  *  @return  void
 291  **/
 292
 293 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
 294 {
 295    if(resrcInfo->SchPucchFormat.format1)
 296    {
 297       ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 298       ulSchedPucch->pucchFormat  = PUCCH_FORMAT_1;
 299       ulSchedPucch->initialCyclicShift =  resrcInfo->SchPucchFormat.format1->initialCyclicShift;
 300       ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
 301       ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
 302       ulSchedPucch->timeDomOCC =  resrcInfo->SchPucchFormat.format1->timeDomOCC;
 303   }
 304 }
 305
 306 /**
 307  * @brief Function to fill Pucch format for UL Sched Info
 308  *
 309  * @details
 310  *
 311  *     Function : fillUlSchedPucchFormat
 312  *
 313  *     Function to fill Pucch format for UL Sched Info
 314  *
 315  *  @param[in]  pucchFormat , SchPucchInfo pointer,
 316  *  @param[in]  SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
 317  *  @return  void
 318  **/
 319
 320 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
 321    SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
 322 {
 323    uint8_t ret = ROK;
 324
 325    switch(pucchFormat)
 326    {
 327       case PUCCH_FORMAT_0:
 328          {
 329             if(resrcInfo)
 330                fillPucchFormat0(ulSchedPucch, resrcInfo);
 331             return ret;
 332          }
 333       case PUCCH_FORMAT_1:
 334          {
 335             if(resrcInfo)
 336             {
 337                fillPucchFormat1(ulSchedPucch, resrcInfo);
 338             }
 339             if(formatCfg)
 340             {
 341                memcpy(&ulSchedPucch->cmnFormatCfg, formatCfg, sizeof(SchPucchFormatCfg));
 342             }
 343             return ret;
 344          }/* To Add support for more Pucch Format */
 345
 346       default:
 347          DU_LOG("\nERROR  --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
 348          ret = RFAILED;
 349          return ret;
 350    }
 351    return ret;
 352 }
 353
 354 /**
 355  * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
 356  *
 357  * @details
 358  *
 359  *     Function : fillUlSchedPucchDedicatedCfg
 360  *
 361  *     Function to fill Pucch Dedicated Cfg for UL Sched Info
 362  *
 363  *  @param[in]  pucchFormat to be filled
 364  *  @param[in]  SchPucchFormatCfg pointer, SchPucchCfg pointer
 365  *  @return  void
 366  **/
 367
 368 uint8_t fillUlSchedPucchDedicatedCfg(uint16_t numSlots, SchPucchCfg *pucchDedCfg,\
 369    SlotIndInfo *slotInfo, SchPucchInfo *ulSchedPucch)
 370 {
 371    uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
 372    uint16_t srOffset = 0;
 373
 374    ret = ROK;
 375    if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
 376    {
 377       //Assuming one entry in the list
 378       for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
 379       {
 380          for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
 381          {
 382             if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
 383                pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
 384             {
 385                ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
 386                ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
 387                ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
 388                ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
 389                ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
 390                         &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
 391                if(ret == RFAILED)
 392                   return ret;
 393             }
 394          }
 395       }
 396    }
 397    if(pucchDedCfg->format1)
 398    {
 399       memset(&ulSchedPucch->cmnFormatCfg, 0, sizeof(SchPucchFormatCfg));
 400       ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
 401       if(ret == RFAILED)
 402          return ret;
 403    }
 404
 405    /* setting SR and UCI flag */
 406    if(pucchDedCfg->schedReq)
 407    {
 408       for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
 409       {
 410          srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
 411          srOffset      = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
 412          break;
 413       }
 414       if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
 415       {
 416          ulSchedPucch->srFlag  = true;
 417          ulSchedPucch->uciFlag = true;
 418       }
 419    }
 420    return ret;
 421 }
 422
 423 /**
 424  * @brief Function to fill Pucch Resource Info
 425  *
 426  * @details
 427  *
 428  *     Function : fillPucchResourceInfo
 429  *
 430  *     Function to fill Pucch Resource Info
 431  *
 432  *  @param[in]  SchPucchInfo *schPucchInfo, Inst inst
 433  *  @return  ROK/RFAILED
 434  **/
 435
 436 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
 437 {
 438    uint8_t ret = ROK, ueIdx = 0, pucchIdx = 0;
 439    SchCellCb  *cell = schCb[inst].cells[inst];
 440    SchPucchCfgCmn *pucchCfg = NULLP;
 441    SchBwpParams *ulBwp = NULLP;
 442
 443    GET_UE_IDX(schPucchInfo->rnti, ueIdx);
 444    if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
 445    {
 446       /* fill pucch dedicated cfg */
 447       ret = fillUlSchedPucchDedicatedCfg(cell->numSlots,\
 448        &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg, &cell->slotInfo, schPucchInfo);
 449       if(ret == RFAILED)
 450       {
 451          memset(schPucchInfo, 0, sizeof(SchPucchInfo));
 452          DU_LOG("\nERROR  --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
 453          return ret;
 454       }
 455    }
 456    else
 457    {
 458       /* fill pucch common cfg */
 459       /* derive pucchResourceSet from schCellCfg */
 460       pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
 461       pucchIdx = pucchCfg->pucchResourceCommon;
 462       ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
 463       schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
 464       schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 465       schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
 466       schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
 467       schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
 468
 469       /* set SR and UCI flag to false */
 470       schPucchInfo->srFlag  = true;
 471       schPucchInfo->uciFlag = true;
 472    }
 473    /* set HARQ flag to true */
 474    schPucchInfo->harqFlag = true;
 475    schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
 476
 477    return ROK;
 478 }
 479
 480 /**
 481  * @brief resource allocation for UL
 482  *
 483  * @details
 484  *
 485  *     Function : schUlResAlloc
 486  *
 487  *     This function handles UL Resource allocation
 488  *
 489  *  @param[in]  SchCellCb *cell, cellCb
 490  *  @return  void
 491  **/
 492 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
 493 {
 494    int ret = ROK;
 495    UlSchedInfo ulSchedInfo;
 496    SchUlSlotInfo  *schUlSlotInfo = NULLP;
 497    SlotIndInfo ulTimingInfo;
 498    memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
 499
 500    /* add PHY delta */
 501    ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA_UL+SCHED_DELTA);
 502
 503    ulSchedInfo.cellId = cell->cellId;
 504    ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
 505    ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
 506    ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
 507
 508    /* Schedule resources for PRACH */
 509    if(cell->firstSib1Transmitted)
 510     schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
 511
 512    schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
 513    if(schUlSlotInfo->schPuschInfo)
 514    {
 515       ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
 516       ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
 517       memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
 518             sizeof(SchPuschInfo));
 519       SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
 520       schUlSlotInfo->schPuschInfo = NULL;
 521    }
 522
 523    if(schUlSlotInfo->pucchPres)
 524    {
 525       ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
 526       fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
 527       memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
 528             sizeof(SchPucchInfo));
 529       memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 530    }
 531
 532    //send msg to MAC
 533    ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
 534    if(ret != ROK)
 535    {
 536       DU_LOG("\nERROR  -->  SCH : Sending UL Sch info from SCH to MAC failed");
 537    }
 538
 539    schInitUlSlot(schUlSlotInfo);
 540    return ret;
 541 }
 542
 543 /*******************************************************************
 544  *
 545  * @brief Fills pdcch and pdsch info for msg4
 546  *
 547  * @details
 548  *
 549  *    Function : schDlRsrcAllocMsg4
 550  *
 551  *    Functionality:
 552  *       Fills pdcch and pdsch info for msg4
 553  *
 554  * @params[in]
 555  * @return ROK     - success
 556  *         RFAILED - failure
 557  *
 558  * ****************************************************************/
 559 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
 560 {
 561    uint8_t coreset0Idx = 0;
 562    uint8_t numRbs = 0;
 563    uint8_t firstSymbol = 0;
 564    uint8_t numSymbols = 0;
 565    uint8_t offset = 0;
 566    uint8_t offsetPointA;
 567    uint8_t FreqDomainResource[6] = {0};
 568    uint16_t tbSize = 0;
 569    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 570    uint8_t mcs = 4;  /* MCS fixed to 4 */
 571    SchBwpDlCfg *initialBwp;
 572
 573    PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
 574    PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
 575    BwpCfg *bwp = &msg4Alloc->bwp;
 576
 577    initialBwp   = &cell->cellCfg.schInitialDlBwp;
 578    offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
 579    coreset0Idx  = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
 580
 581    /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
 582    numRbs        = coresetIdxTable[coreset0Idx][1];
 583    numSymbols    = coresetIdxTable[coreset0Idx][2];
 584    offset        = coresetIdxTable[coreset0Idx][3];
 585
 586    /* calculate time domain parameters */
 587    uint16_t mask = 0x2000;
 588    for(firstSymbol=0; firstSymbol<14;firstSymbol++)
 589    {
 590       if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
 591          break;
 592       else
 593          mask = mask>>1;
 594    }
 595
 596    /* calculate the PRBs */
 597    freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
 598
 599    /* fill BWP */
 600    bwp->freqAlloc.numPrb   = initialBwp->bwp.freqAlloc.numPrb;
 601    bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
 602    bwp->subcarrierSpacing  = initialBwp->bwp.scs;
 603    bwp->cyclicPrefix       = initialBwp->bwp.cyclicPrefix;
 604
 605    /* fill the PDCCH PDU */
 606    pdcch->coresetCfg.startSymbolIndex = firstSymbol;
 607    pdcch->coresetCfg.durationSymbols = numSymbols;
 608    memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
 609    pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
 610    pdcch->coresetCfg.regBundleSize = 6;    /* spec-38.211 sec 7.3.2.2 */
 611    pdcch->coresetCfg.interleaverSize = 2;  /* spec-38.211 sec 7.3.2.2 */
 612    pdcch->coresetCfg.coreSetType = 0;
 613    pdcch->coresetCfg.coreSetSize = numRbs;
 614    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
 615    pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
 616    pdcch->numDlDci = 1;
 617    pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
 618    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
 619    pdcch->dci.scramblingRnti = 0;
 620    pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
 621    pdcch->dci.aggregLevel = 4;
 622    pdcch->dci.beamPdcchInfo.numPrgs = 1;
 623    pdcch->dci.beamPdcchInfo.prgSize = 1;
 624    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
 625    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
 626    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
 627    pdcch->dci.txPdcchPower.powerValue = 0;
 628    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
 629
 630    /* fill the PDSCH PDU */
 631    uint8_t cwCount = 0;
 632    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
 633    pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
 634    pdsch->pduIndex = 0;
 635    pdsch->numCodewords = 1;
 636    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
 637    {
 638       pdsch->codeword[cwCount].targetCodeRate = 308;
 639       pdsch->codeword[cwCount].qamModOrder = 2;
 640       pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
 641       pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
 642       pdsch->codeword[cwCount].rvIndex = 0;
 643       /* 38.214: Table 5.1.3.2-1,  divided by 8 to get the value in bytes */
 644       /* TODO : Calculate tbSize based of DL CCCH msg size */
 645       tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
 646       pdsch->codeword[cwCount].tbSize = tbSize;
 647    }
 648    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
 649    pdsch->numLayers = 1;
 650    pdsch->transmissionScheme = 0;
 651    pdsch->refPoint = 0;
 652    pdsch->dmrs.dlDmrsSymbPos = 2;
 653    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
 654    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
 655    pdsch->dmrs.scid = 0;
 656    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
 657    pdsch->dmrs.dmrsPorts = 0;
 658    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
 659    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
 660    pdsch->dmrs.dmrsAddPos       = DMRS_ADDITIONAL_POS;
 661    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
 662    /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
 663    pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
 664    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
 665    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
 666    pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
 667    pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
 668    pdsch->beamPdschInfo.numPrgs = 1;
 669    pdsch->beamPdschInfo.prgSize = 1;
 670    pdsch->beamPdschInfo.digBfInterfaces = 0;
 671    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
 672    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
 673    pdsch->txPdschPower.powerControlOffset = 0;
 674    pdsch->txPdschPower.powerControlOffsetSS = 0;
 675
 676    pdcch->dci.pdschCfg = pdsch;
 677
 678    return ROK;
 679 }
 680
 681 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot)
 682 {
 683    uint8_t k1 = SCH_DEFAULT_K1, ueIdx = 0, dlToUlAckIdx;
 684    uint16_t pucchSlot = 0;
 685    SchUlSlotInfo  *schUlSlotInfo = NULLP;
 686    SchPucchCfg    *schPucchCfg = NULLP;
 687
 688    GET_UE_IDX(crnti, ueIdx);
 689    if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
 690    {
 691       schPucchCfg = &(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg);
 692      if(schPucchCfg->dlDataToUlAck)
 693      {
 694         for(dlToUlAckIdx = 0; dlToUlAckIdx < schPucchCfg->dlDataToUlAck->dlDataToUlAckListCount; dlToUlAckIdx++)
 695         {
 696            //For now considering only the first value in the list
 697            k1 = schPucchCfg->dlDataToUlAck->dlDataToUlAckList[dlToUlAckIdx];
 698            break;
 699         }
 700      }
 701    }
 702
 703    pucchSlot = (slot + k1)  % cell->numSlots;
 704    schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
 705    memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 706
 707    schUlSlotInfo->pucchPres = true;
 708    schUlSlotInfo->schPucchInfo.rnti = crnti;
 709
 710    return ROK;
 711 }
 712
 713 /*******************************************************************
 714  *
 715  * @brief Fills pdcch and pdsch info for dedicated DL msg
 716  *
 717  * @details
 718  *
 719  *    Function : schDlRsrcAllocDlMsg
 720  *
 721  *    Functionality:
 722  *       Fills pdcch and pdsch info for dl msg
 723  *
 724  * @params[in]
 725  * @return ROK     - success
 726  *         RFAILED - failure
 727  *
 728  * ****************************************************************/
 729 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
 730       uint32_t *accumalatedSize, uint16_t slot)
 731 {
 732    uint8_t ueIdx;
 733    uint16_t tbSize = 0;
 734    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 735    PdcchCfg *pdcch = NULLP;
 736    PdschCfg *pdsch = NULLP;
 737    BwpCfg *bwp = NULLP;
 738    SchUeCb ueCb;
 739    SchControlRsrcSet coreset1;
 740    SchPdschConfig pdschCfg;
 741
 742    pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
 743    pdsch = &dlMsgAlloc->dlMsgPdschCfg;
 744    bwp = &dlMsgAlloc->bwp;
 745
 746    GET_UE_IDX(crnti, ueIdx);
 747    ueCb  = cell->ueCb[ueIdx-1];
 748    coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
 749    pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
 750
 751    /* fill BWP */
 752    bwp->freqAlloc.numPrb = MAX_NUM_RB;
 753    bwp->freqAlloc.startPrb = 0;
 754    bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
 755    bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
 756
 757    /* fill the PDCCH PDU */
 758    //Considering coreset1 also starts from same symbol as coreset0
 759    pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
 760    pdcch->coresetCfg.durationSymbols = coreset1.duration;
 761    memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
 762    pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
 763    pdcch->coresetCfg.regBundleSize = 6;   /* must be 6 for non-interleaved */
 764    pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
 765    pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
 766    //Considering number of RBs in coreset1 is same as coreset0
 767    pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
 768    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
 769    pdcch->coresetCfg.precoderGranularity =  coreset1.precoderGranularity;
 770    pdcch->numDlDci = 1;
 771    pdcch->dci.rnti = ueCb.crnti;
 772    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
 773    pdcch->dci.scramblingRnti = 0;
 774    pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
 775    pdcch->dci.aggregLevel = 4;
 776    pdcch->dci.beamPdcchInfo.numPrgs = 1;
 777    pdcch->dci.beamPdcchInfo.prgSize = 1;
 778    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
 779    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
 780    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
 781    pdcch->dci.txPdcchPower.powerValue = 0;
 782    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
 783
 784    /* fill the PDSCH PDU */
 785    uint8_t cwCount = 0;
 786    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
 787    pdsch->rnti = ueCb.crnti;
 788    pdsch->pduIndex = 0;
 789    pdsch->numCodewords = 1;
 790    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
 791    {
 792       pdsch->codeword[cwCount].targetCodeRate = 308;
 793       pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
 794       pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
 795       pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
 796       pdsch->codeword[cwCount].rvIndex = 0;
 797       tbSize = schCalcTbSize(*accumalatedSize);
 798       if(tbSize < *accumalatedSize)
 799          *accumalatedSize = tbSize;
 800       pdsch->codeword[cwCount].tbSize = tbSize;
 801    }
 802    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
 803    pdsch->numLayers = 1;
 804    pdsch->transmissionScheme = 0;
 805    pdsch->refPoint = 0;
 806    pdsch->dmrs.dlDmrsSymbPos = 2;
 807    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
 808    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
 809    pdsch->dmrs.scid = 0;
 810    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
 811    pdsch->dmrs.dmrsPorts = 0;
 812    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
 813    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
 814    pdsch->dmrs.dmrsAddPos       = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
 815    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
 816    pdsch->pdschFreqAlloc.freqAlloc.startPrb = 1;
 817    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, numPdschSymbols);
 818    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
 819    pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
 820    pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
 821    pdsch->beamPdschInfo.numPrgs = 1;
 822    pdsch->beamPdschInfo.prgSize = 1;
 823    pdsch->beamPdschInfo.digBfInterfaces = 0;
 824    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
 825    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
 826    pdsch->txPdschPower.powerControlOffset = 0;
 827    pdsch->txPdschPower.powerControlOffsetSS = 0;
 828
 829    pdcch->dci.pdschCfg = pdsch;
 830    return ROK;
 831 }
 832
 833 /**********************************************************************
 834   End of file
 835  **********************************************************************/
 836