1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
34 #include "common_def.h"
41 #include "du_app_mac_inf.h"
42 #include "mac_sch_interface.h"
44 #include "sch_utils.h"
46 SchCb schCb[SCH_MAX_INST];
47 uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
48 uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
49 uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
50 uint8_t puschDeltaTable[MAX_MU_PUSCH];
52 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
60 * @brief common resource allocation for SSB
64 * Function : schBroadcastAlloc
66 * This function handles common scheduling for DL
68 * @param[in] SchCellCb *cell, cell cb
69 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
72 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
76 uint8_t ssbStartPrb, ssbStartSymb, idx;
77 SchDlSlotInfo *schDlSlotInfo;
80 schDlSlotInfo = cell->schDlSlotInfo[slot];
82 if(dlBrdcstAlloc->ssbTrans)
84 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; //+Kssb
85 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
86 supporting only 1 ssb beam */
88 /* Assign interface structure */
89 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
92 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
93 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
94 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
95 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
96 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
97 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
100 schDlSlotInfo->ssbPres = true;
101 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
102 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
104 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
108 /* SIB1 allocation */
109 if(dlBrdcstAlloc->sib1Trans)
112 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
113 uint8_t mcs = 4; /* MCS fixed to 4 */
114 uint8_t numSib1Prb = 0;
115 schDlSlotInfo->sib1Pres = true;
117 tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
118 numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
119 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
121 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
123 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
124 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
125 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
126 dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
131 /*******************************************************************
133 * @brief Handles sending UL scheduler info to MAC
137 * Function : sendUlSchInfoToMac
140 * Sends UL Sch info to MAC from SCH
143 * @return ROK - success
146 * ****************************************************************/
147 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
151 memset(&pst, 0, sizeof(Pst));
152 FILL_PST_SCH_TO_MAC(pst, inst);
153 pst.event = EVENT_UL_SCH_INFO;
155 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
158 * @brief resource allocation for PRACH
162 * Function : schPrachResAlloc
164 * This function handles PRACH allocation
166 * @param[in] SchCellCb *cell, cell cb
167 * @param[in] UlSchedInfo *ulSchedInfo, UL scheduling info
170 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo)
173 uint8_t numPrachRb = 0;
175 uint8_t freqStart = 0;
176 uint8_t prachCfgIdx = 0;
177 uint8_t prachFormat = 0;
180 uint16_t prachSubframe = 0;
181 uint8_t prachStartSymbol = 0;
182 uint8_t prachOcas = 0;
183 uint8_t dataType = 0;
185 uint8_t subFrame = 0;
186 SchUlSlotInfo *schUlSlotInfo = NULLP;
188 puschScs = cell->cellCfg.schInitialUlBwp.bwp.scs;
189 schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
190 prachCfgIdx = cell->cellCfg.schRachCfg.prachCfgIdx;
192 /* derive the prachCfgIdx table paramters */
193 x = prachCfgIdxTable[prachCfgIdx][1];
194 y = prachCfgIdxTable[prachCfgIdx][2];
195 prachSubframe = prachCfgIdxTable[prachCfgIdx][3];
197 if((prachOccasionTimingInfo.sfn%x) == y)
200 subFrame = prachOccasionTimingInfo.slot/2;
202 subFrame = prachOccasionTimingInfo.slot;
204 /* check for subFrame number */
205 if ((1 << subFrame) & prachSubframe)
207 /* prach ocassion present in this subframe */
209 if(UL_SLOT != schGetSlotSymbFrmt(prachOccasionTimingInfo.slot%cell->numSlotsInPeriodicity,\
210 cell->slotFrmtBitMap))
212 DU_LOG("\nERROR --> SCH : PrachCfgIdx %d doesn't support UL slot", prachCfgIdx);
217 prachFormat = prachCfgIdxTable[prachCfgIdx][0];
218 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
219 prachOcas = prachCfgIdxTable[prachCfgIdx][6];
221 /* freq domain resource determination for RACH*/
222 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
223 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
224 * where M is given by msg1Fdm */
225 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
226 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
228 if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
230 if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
232 if(numRbForPrachTable[idx][2] == puschScs)
239 numPrachRb = numRbForPrachTable[idx][3];
240 dataType |= SCH_DATATYPE_PRACH;
241 /* Considering first slot in the frame for PRACH */
243 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
245 ulSchedInfo->dataType = dataType;
247 ulSchedInfo->prachSchInfo.numPrachOcas = prachOcas;
248 ulSchedInfo->prachSchInfo.prachFormat = prachFormat;
249 ulSchedInfo->prachSchInfo.numRa = numRa;
250 ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
251 DU_LOG("\nINFO --> SCH : RACH occassion set for slot %d", prachOccasionTimingInfo.slot);
258 * @brief Function to fill Pucch Format 0
262 * Function : fillPucchFormat0
264 * Function to fill Pucch format 0
266 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
270 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
272 if(resrcInfo->SchPucchFormat.format0)
274 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
275 ulSchedPucch->pucchFormat = PUCCH_FORMAT_0;
276 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format0->initialCyclicShift;
277 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
278 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
283 * @brief Function to fill Pucch Format 1
287 * Function : fillPucchFormat1
289 * Function to fill Pucch format 1
291 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
295 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
297 if(resrcInfo->SchPucchFormat.format1)
299 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
300 ulSchedPucch->pucchFormat = PUCCH_FORMAT_1;
301 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format1->initialCyclicShift;
302 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
303 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
304 ulSchedPucch->timeDomOCC = resrcInfo->SchPucchFormat.format1->timeDomOCC;
309 * @brief Function to fill Pucch format for UL Sched Info
313 * Function : fillUlSchedPucchFormat
315 * Function to fill Pucch format for UL Sched Info
317 * @param[in] pucchFormat , SchPucchInfo pointer,
318 * @param[in] SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
322 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
323 SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
332 fillPucchFormat0(ulSchedPucch, resrcInfo);
339 fillPucchFormat1(ulSchedPucch, resrcInfo);
343 memcpy(&ulSchedPucch->cmnFormatCfg, formatCfg, sizeof(SchPucchFormatCfg));
346 }/* To Add support for more Pucch Format */
349 DU_LOG("\nERROR --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
357 * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
361 * Function : fillUlSchedPucchDedicatedCfg
363 * Function to fill Pucch Dedicated Cfg for UL Sched Info
365 * @param[in] pucchFormat to be filled
366 * @param[in] SchPucchFormatCfg pointer, SchPucchCfg pointer
370 uint8_t fillUlSchedPucchDedicatedCfg(uint16_t numSlots, SchPucchCfg *pucchDedCfg,\
371 SlotTimingInfo *slotInfo, SchPucchInfo *ulSchedPucch)
373 uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
374 uint16_t srOffset = 0;
377 if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
379 //Assuming one entry in the list
380 for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
382 for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
384 if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
385 pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
387 ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
388 ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
389 ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
390 ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
391 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
392 &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
399 if(pucchDedCfg->format1)
401 memset(&ulSchedPucch->cmnFormatCfg, 0, sizeof(SchPucchFormatCfg));
402 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
407 /* setting SR and UCI flag */
408 if(pucchDedCfg->schedReq)
410 for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
412 srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
413 srOffset = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
416 if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
418 ulSchedPucch->srFlag = true;
419 ulSchedPucch->uciFlag = true;
426 * @brief Function to fill Pucch Resource Info
430 * Function : fillPucchResourceInfo
432 * Function to fill Pucch Resource Info
434 * @param[in] SchPucchInfo *schPucchInfo, Inst inst
435 * @return ROK/RFAILED
438 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
440 uint8_t ret = ROK, ueIdx = 0, pucchIdx = 0;
441 SchCellCb *cell = schCb[inst].cells[inst];
442 SchPucchCfgCmn *pucchCfg = NULLP;
443 SchBwpParams *ulBwp = NULLP;
445 GET_UE_IDX(schPucchInfo->rnti, ueIdx);
446 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
448 /* fill pucch dedicated cfg */
449 ret = fillUlSchedPucchDedicatedCfg(cell->numSlots,\
450 &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg, &cell->slotInfo, schPucchInfo);
453 memset(schPucchInfo, 0, sizeof(SchPucchInfo));
454 DU_LOG("\nERROR --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
460 /* fill pucch common cfg */
461 /* derive pucchResourceSet from schCellCfg */
462 pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
463 pucchIdx = pucchCfg->pucchResourceCommon;
464 ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
465 schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
466 schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
467 schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
468 schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
469 schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
471 /* set SR and UCI flag to false */
472 schPucchInfo->srFlag = true;
473 schPucchInfo->uciFlag = true;
475 /* set HARQ flag to true */
476 schPucchInfo->harqFlag = true;
477 schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
483 * @brief resource allocation for UL
487 * Function : schUlResAlloc
489 * This function handles UL Resource allocation
491 * @param[in] SchCellCb *cell, cellCb
494 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
497 UlSchedInfo ulSchedInfo;
498 SchUlSlotInfo *schUlSlotInfo = NULLP;
499 SlotTimingInfo ulTimingInfo;
500 memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
503 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA_UL+SCHED_DELTA);
505 ulSchedInfo.cellId = cell->cellId;
506 ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
507 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
508 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
510 /* Schedule resources for PRACH */
511 if(cell->firstSib1Transmitted)
512 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
514 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
515 if(schUlSlotInfo->schPuschInfo)
517 ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
518 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
519 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
520 sizeof(SchPuschInfo));
521 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
522 schUlSlotInfo->schPuschInfo = NULL;
525 if(schUlSlotInfo->pucchPres)
527 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
528 fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
529 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
530 sizeof(SchPucchInfo));
531 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
535 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
538 DU_LOG("\nERROR --> SCH : Sending UL Sch info from SCH to MAC failed");
541 schInitUlSlot(schUlSlotInfo);
545 /*******************************************************************
547 * @brief Fills pdcch and pdsch info for msg4
551 * Function : schDlRsrcAllocMsg4
554 * Fills pdcch and pdsch info for msg4
557 * @return ROK - success
560 * ****************************************************************/
561 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot, bool ssbPresent, bool sib1Present)
563 uint8_t coreset0Idx = 0;
565 uint8_t firstSymbol = 0;
566 uint8_t numSymbols = 0;
568 uint8_t offsetPointA;
569 uint8_t FreqDomainResource[6] = {0};
571 uint8_t numPdschSymbols = 11; /* considering pdsch region from 3 to 13 */
572 uint8_t mcs = 4; /* MCS fixed to 4 */
573 SchBwpDlCfg *initialBwp;
574 FreqDomainAlloc *sib1PdschFreqAlloc = NULL;
576 PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
577 PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
578 BwpCfg *bwp = &msg4Alloc->bwp;
580 initialBwp = &cell->cellCfg.schInitialDlBwp;
581 offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
582 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
584 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
585 numRbs = coresetIdxTable[coreset0Idx][1];
586 numSymbols = coresetIdxTable[coreset0Idx][2];
587 offset = coresetIdxTable[coreset0Idx][3];
589 /* calculate time domain parameters */
590 uint16_t mask = 0x2000;
591 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
593 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
599 /* calculate the PRBs */
600 freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
603 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
604 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
605 bwp->subcarrierSpacing = initialBwp->bwp.scs;
606 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
608 /* fill the PDCCH PDU */
609 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
610 pdcch->coresetCfg.durationSymbols = numSymbols;
611 memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
612 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
613 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
614 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
615 pdcch->coresetCfg.coreSetType = 0;
616 pdcch->coresetCfg.coreSetSize = numRbs;
617 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
618 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
620 pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
621 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
622 pdcch->dci.scramblingRnti = 0;
623 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
624 pdcch->dci.aggregLevel = 4;
625 pdcch->dci.beamPdcchInfo.numPrgs = 1;
626 pdcch->dci.beamPdcchInfo.prgSize = 1;
627 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
628 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
629 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
630 pdcch->dci.txPdcchPower.powerValue = 0;
631 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
633 /* fill the PDSCH PDU */
635 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
636 pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
638 pdsch->numCodewords = 1;
639 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
641 pdsch->codeword[cwCount].targetCodeRate = 308;
642 pdsch->codeword[cwCount].qamModOrder = 2;
643 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
644 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
645 pdsch->codeword[cwCount].rvIndex = 0;
646 tbSize = schCalcTbSize(msg4Alloc->dlMsgInfo.dlMsgPduLen + TX_PAYLOAD_HDR_LEN); /* MSG4 size + FAPI header size*/
647 pdsch->codeword[cwCount].tbSize = tbSize;
649 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
650 pdsch->numLayers = 1;
651 pdsch->transmissionScheme = 0;
653 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
654 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
655 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
656 pdsch->dmrs.scid = 0;
657 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
658 pdsch->dmrs.dmrsPorts = 0;
659 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
660 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
661 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
662 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
663 /* The RB numbering starts from coreset0 */
664 pdsch->pdschFreqAlloc.freqAlloc.startPrb = PDSCH_START_RB;
667 /* PDSCH is always above SSB */
668 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1;
672 /* Must not overlap with SIB1 */
673 sib1PdschFreqAlloc = &cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc;
674 pdsch->pdschFreqAlloc.freqAlloc.startPrb = sib1PdschFreqAlloc->startPrb + sib1PdschFreqAlloc->numPrb + 1;
676 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, numPdschSymbols);
677 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
678 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
679 pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
680 pdsch->beamPdschInfo.numPrgs = 1;
681 pdsch->beamPdschInfo.prgSize = 1;
682 pdsch->beamPdschInfo.digBfInterfaces = 0;
683 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
684 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
685 pdsch->txPdschPower.powerControlOffset = 0;
686 pdsch->txPdschPower.powerControlOffsetSS = 0;
688 pdcch->dci.pdschCfg = pdsch;
693 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot)
695 uint8_t k1 = SCH_DEFAULT_K1, ueIdx = 0, dlToUlAckIdx;
696 uint16_t pucchSlot = 0;
697 SchUlSlotInfo *schUlSlotInfo = NULLP;
698 SchPucchCfg *schPucchCfg = NULLP;
700 GET_UE_IDX(crnti, ueIdx);
701 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
703 schPucchCfg = &(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg);
704 if(schPucchCfg->dlDataToUlAck)
706 for(dlToUlAckIdx = 0; dlToUlAckIdx < schPucchCfg->dlDataToUlAck->dlDataToUlAckListCount; dlToUlAckIdx++)
708 //For now considering only the first value in the list
709 k1 = schPucchCfg->dlDataToUlAck->dlDataToUlAckList[dlToUlAckIdx];
715 pucchSlot = (slot + k1) % cell->numSlots;
716 schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
717 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
719 schUlSlotInfo->pucchPres = true;
720 schUlSlotInfo->schPucchInfo.rnti = crnti;
725 /*******************************************************************
727 * @brief Fills pdcch and pdsch info for dedicated DL msg
731 * Function : schDlRsrcAllocDlMsg
734 * Fills pdcch and pdsch info for dl msg
737 * @return ROK - success
740 * ****************************************************************/
741 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
742 uint32_t *accumalatedSize, uint16_t slot)
746 PdcchCfg *pdcch = NULLP;
747 PdschCfg *pdsch = NULLP;
750 SchControlRsrcSet coreset1;
751 SchPdschConfig pdschCfg;
753 pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
754 pdsch = &dlMsgAlloc->dlMsgPdschCfg;
755 bwp = &dlMsgAlloc->bwp;
757 GET_UE_IDX(crnti, ueIdx);
758 ueCb = cell->ueCb[ueIdx-1];
759 coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
760 pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
763 bwp->freqAlloc.numPrb = MAX_NUM_RB;
764 bwp->freqAlloc.startPrb = 0;
765 bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
766 bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
768 /* fill the PDCCH PDU */
769 //Considering coreset1 also starts from same symbol as coreset0
770 pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
771 pdcch->coresetCfg.durationSymbols = coreset1.duration;
772 memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
773 pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
774 pdcch->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
775 pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
776 pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
777 //Considering number of RBs in coreset1 is same as coreset0
778 pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
779 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
780 pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
782 pdcch->dci.rnti = ueCb.crnti;
783 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
784 pdcch->dci.scramblingRnti = 0;
785 pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
786 pdcch->dci.aggregLevel = 4;
787 pdcch->dci.beamPdcchInfo.numPrgs = 1;
788 pdcch->dci.beamPdcchInfo.prgSize = 1;
789 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
790 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
791 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
792 pdcch->dci.txPdcchPower.powerValue = 0;
793 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
795 /* fill the PDSCH PDU */
797 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
798 pdsch->rnti = ueCb.crnti;
800 pdsch->numCodewords = 1;
801 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
803 pdsch->codeword[cwCount].targetCodeRate = 308;
804 pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
805 pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
806 pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
807 pdsch->codeword[cwCount].rvIndex = 0;
808 tbSize = schCalcTbSize(*accumalatedSize + TX_PAYLOAD_HDR_LEN);
809 if(tbSize < *accumalatedSize)
810 *accumalatedSize = tbSize - TX_PAYLOAD_HDR_LEN;
811 pdsch->codeword[cwCount].tbSize = tbSize;
813 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
814 pdsch->numLayers = 1;
815 pdsch->transmissionScheme = 0;
817 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
818 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
819 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
820 pdsch->dmrs.scid = 0;
821 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
822 pdsch->dmrs.dmrsPorts = 0;
823 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
824 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
825 pdsch->dmrs.dmrsAddPos = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
826 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
827 pdsch->pdschFreqAlloc.freqAlloc.startPrb = PDSCH_START_RB;
828 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, \
829 pdschCfg.timeDomRsrcAllociList[0].symbolLength);
830 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
831 pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
832 pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
833 pdsch->beamPdschInfo.numPrgs = 1;
834 pdsch->beamPdschInfo.prgSize = 1;
835 pdsch->beamPdschInfo.digBfInterfaces = 0;
836 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
837 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
838 pdsch->txPdschPower.powerControlOffset = 0;
839 pdsch->txPdschPower.powerControlOffsetSS = 0;
841 pdcch->dci.pdschCfg = pdsch;
845 /*******************************************************************
847 * @brief Fills k0 and k1 information table for FDD
851 * Function : BuildK0K1TableForFdd
854 * Fills k0 and k1 information table for FDD
856 * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool
857 * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc
858 * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc
859 * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl
860 * @return ROK - success
863 * ****************************************************************/
864 void BuildK0K1TableForFdd(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres,SchPdschCfgCmn pdschCmnCfg,\
865 SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl)
868 uint8_t k1TmpVal =0, cfgIdx=0;
869 uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, numTimeDomAlloc=0;
871 /* TODO Commented these below lines for resolving warnings. Presently these variable are not
872 * required but this will require for harq processing */
873 // uint8_t k0TmpVal = 0;
874 // SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
875 // SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
877 /* Initialization the structure and storing the total slot values. */
878 memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl));
879 k0K1InfoTbl->tblSize = cell->numSlots;
881 /* Storing time domain resource allocation list based on common or dedicated configuration. */
882 if(pdschCfgCmnPres == true)
884 numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc;
885 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
887 /*TODO uncomment this line during harq processing */
888 //cmnTimeDomRsrcAllocList[cfgIdx] = pdschCmnCfg.timeDomRsrcAllocList[cfgIdx];
893 numTimeDomAlloc = pdschDedCfg.numTimeDomRsrcAlloc;
894 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
896 /*TODO uncomment this line during harq processing */
897 //dedTimeDomRsrcAllocList[cfgIdx] = pdschDedCfg.timeDomRsrcAllociList[cfgIdx];
901 /* Checking all the slots for K0 and K1 values. */
902 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
905 /* Storing the values of k0 based on time domain resource
906 * allocation list. If the value is unavailable then fill default values,
907 * As per 38.331 PDSCH-TimeDomainResourceAllocation field descriptions. */
908 for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++)
910 /* TODO These if 0 we will remove during harq processing */
912 if(pdschCfgCmnPres == true)
914 k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0;
918 if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP)
920 k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0);
924 k0TmpVal = DEFAULT_K0_VALUE;
928 /* Checking all the Ul Alloc values. If value is less than MIN_NUM_K1_IDX
929 * then skip else continue storing the values. */
931 for(k1Index = 0; k1Index < ulAckListCount; k1Index++)
933 k1TmpVal = UlAckTbl[k1Index];
934 if(k1TmpVal <= MIN_NUM_K1_IDX)
939 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index;
940 /* TODO Store K1 index where harq feedback will be received in harq table. */
944 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1;
945 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index;
951 k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0;
956 /*******************************************************************
958 * @brief Fills k0 and k1 information table
962 * Function : BuildK0K1Table
965 * Fills K0 and k1 information table
967 * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool
968 * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc
969 * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc
970 * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl
971 * @return ROK - success
974 * ****************************************************************/
975 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, SchPdschCfgCmn pdschCmnCfg,\
976 SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl)
981 bool ulSlotPresent = false;
982 uint8_t k0TmpVal = 0, k1TmpVal =0, tmpSlot=0, startSymbol=0, endSymbol=0, checkSymbol=0;
983 uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, cfgIdx=0, numTimeDomAlloc =0, totalCfgSlot =0;
984 SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
985 SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
988 if(cell->cellCfg.dupMode == DUPLEX_MODE_FDD)
990 BuildK0K1TableForFdd(cell, k0K1InfoTbl, pdschCfgCmnPres, pdschCmnCfg, pdschDedCfg, ulAckListCount, UlAckTbl);
996 /* Initialization the K0K1 structure, total num of slot and calculating the slot pattern length. */
997 memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl));
998 k0K1InfoTbl->tblSize = cell->numSlots;
999 totalCfgSlot = calculateSlotPatternLength(cell->cellCfg.ssbSchCfg.scsCommon, cell->cellCfg.tddCfg.tddPeriod);
1001 /* Storing time domain resource allocation list based on common or
1002 * dedicated configuration availability. */
1003 if(pdschCfgCmnPres == true)
1005 numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc;
1006 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1008 cmnTimeDomRsrcAllocList[cfgIdx] = pdschCmnCfg.timeDomRsrcAllocList[cfgIdx];
1013 numTimeDomAlloc = pdschDedCfg.numTimeDomRsrcAlloc;
1014 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1016 dedTimeDomRsrcAllocList[cfgIdx] = pdschDedCfg.timeDomRsrcAllociList[cfgIdx];
1020 /* Checking all possible indexes for K0 and K1 values. */
1021 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1023 /* If current slot is UL or FLEXI then Skip because PDCCH is sent only in DL slots. */
1024 slotCfg = schGetSlotSymbFrmt(slotIdx%totalCfgSlot, cell->slotFrmtBitMap);
1025 if(slotCfg == UL_SLOT || slotCfg == FLEXI_SLOT)
1030 /* Storing K0 , start symbol and length symbol for further processing.
1031 * If K0 value is not available then we can fill the default values
1032 * given in spec 38.331. */
1034 for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++)
1036 if(pdschCfgCmnPres == true)
1038 k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0;
1039 startSymbol = cmnTimeDomRsrcAllocList[k0Index].startSymbol;
1040 endSymbol = startSymbol + cmnTimeDomRsrcAllocList[k0Index].lengthSymbol;
1044 if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP)
1046 k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0);
1050 k0TmpVal = DEFAULT_K0_VALUE;
1052 startSymbol = dedTimeDomRsrcAllocList[k0Index].startSymbol;
1053 endSymbol = startSymbol + dedTimeDomRsrcAllocList[k0Index].symbolLength;
1056 /* If current slot + k0 is UL then skip the slot
1057 * else if it is DL slot then continue the next steps
1058 * else if it is a FLEXI slot then check symbols of slot, It should not
1059 * contain any UL slot. */
1060 tmpSlot = (slotIdx+k0TmpVal) % totalCfgSlot;
1061 slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap);
1062 if(slotCfg == UL_SLOT)
1066 if(slotCfg == FLEXI_SLOT)
1068 for(checkSymbol = startSymbol; checkSymbol<endSymbol; checkSymbol ++)
1070 slotCfg = cell->cellCfg.tddCfg.slotCfg[tmpSlot][checkSymbol];
1071 if(slotCfg == UL_SLOT)
1078 /* If current slot + k0 + k1 is a DL slot then skip the slot
1079 * else if it is UL slot then store the information
1080 * else if it is FLEXI slot then check the symbols, it must have
1081 * at least one UL symbol. */
1083 for(k1Index = 0; k1Index < ulAckListCount; k1Index++)
1085 k1TmpVal = UlAckTbl[k1Index];
1086 if(k1TmpVal > MIN_NUM_K1_IDX)
1088 tmpSlot = (slotIdx+k0TmpVal+k1TmpVal) % totalCfgSlot;
1089 slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap);
1090 if(slotCfg == DL_SLOT)
1094 if(slotCfg == FLEXI_SLOT)
1096 for(checkSymbol = 0; checkSymbol<SCH_SYMBOL_PER_SLOT;checkSymbol++)
1098 if(cell->cellCfg.tddCfg.slotCfg[tmpSlot][checkSymbol] == UL_SLOT)
1100 ulSlotPresent = true;
1105 if(ulSlotPresent == true || slotCfg == UL_SLOT)
1107 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index;
1108 /* TODO Store K1 index where harq feedback will be received
1114 /* Store all the values if all condition satisfies. */
1117 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1;
1118 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index;
1124 k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0;
1131 /*******************************************************************
1133 * @brief Fills K2 information table for FDD
1137 * Function : BuildK2InfoTableForFdd
1140 * Fills K2 information table for FDD
1142 * @params[in] SchCellCb *cell,SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[],
1143 * uint16_t puschSymTblSize,SchK2TimingInfoTbl *k2InfoTbl
1144 * @return ROK - success
1147 * ****************************************************************/
1148 void BuildK2InfoTableForFdd(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], uint16_t puschSymTblSize,\
1149 SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl)
1151 uint16_t slotIdx=0, k2Index=0, k2TmpIdx=0, msg3K2TmpIdx=0;
1153 /* Initialization the structure and storing the total slot values. */
1154 memset(k2InfoTbl, 0, sizeof(SchK2TimingInfoTbl));
1155 k2InfoTbl->tblSize = cell->numSlots;
1157 msg3K2InfoTbl->tblSize = cell->numSlots;
1159 /* Checking all possible indexes for K2. */
1160 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1162 /* Storing K2 values. */
1163 for(k2Index = 0; ((k2Index < puschSymTblSize) && (k2Index < MAX_NUM_K2_IDX)); k2Index++)
1165 k2TmpIdx= k2InfoTbl->k2TimingInfo[slotIdx].numK2;
1166 k2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[k2TmpIdx] = k2Index;
1167 k2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1169 /* Updating K2 values for MSG3 */
1172 msg3K2TmpIdx = msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2;
1173 msg3K2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[msg3K2TmpIdx] = k2Index;
1174 msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1180 /*******************************************************************
1182 * @brief Fills K2 information table
1186 * Function : BuildK2InfoTable
1189 * Fills K2 information table
1191 * @params[in] SchCellCb *cell,SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[],
1192 * uint16_t puschSymTblSize, SchK2TimingInfoTbl *k2InfoTbl
1193 * @return ROK - success
1196 * ****************************************************************/
1197 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], uint16_t puschSymTblSize,\
1198 SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl)
1202 bool dlSymbolPresent = false;
1203 uint8_t slotIdx=0, k2Index=0, k2Val=0, k2TmpVal=0, msg3K2TmpVal=0, msg3Delta=0, numK2 =0, currentSymbol =0;
1204 uint8_t startSymbol =0, endSymbol =0, checkSymbol=0, totalCfgSlot=0, slotCfg=0;
1205 SlotConfig currentSlot;
1208 if(cell->cellCfg.dupMode == DUPLEX_MODE_FDD)
1210 BuildK2InfoTableForFdd(cell, timeDomRsrcAllocList, puschSymTblSize, msg3K2InfoTbl, k2InfoTbl);
1216 /* Initialization the structure and storing the total slot values. */
1217 memset(k2InfoTbl, 0, sizeof(SchK2TimingInfoTbl));
1218 k2InfoTbl->tblSize = cell->numSlots;
1220 msg3K2InfoTbl->tblSize = cell->numSlots;
1221 totalCfgSlot = calculateSlotPatternLength(cell->cellCfg.ssbSchCfg.scsCommon, cell->cellCfg.tddCfg.tddPeriod);
1223 /* Checking all possible indexes for K2. */
1224 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1226 currentSlot = schGetSlotSymbFrmt(slotIdx % totalCfgSlot, cell->slotFrmtBitMap);
1228 /* If current slot is UL then skip because PDCCH is sent only in DL slots */
1229 if(currentSlot != UL_SLOT)
1231 for(k2Index = 0; ((k2Index < puschSymTblSize) && (k2Index < MAX_NUM_K2_IDX)); k2Index++)
1233 /* Storing k2, startSymbol, endSymbol information for further processing.
1234 * If k2 is absent then fill the default values given in spec 38.331
1235 * PUSCH-TimeDomainResourceAllocationList field descriptions */
1236 k2Val = timeDomRsrcAllocList[k2Index].k2;
1239 switch(cell->cellCfg.ssbSchCfg.scsCommon)
1242 k2Val = DEFAULT_K2_VALUE_FOR_SCS15;
1245 k2Val = DEFAULT_K2_VALUE_FOR_SCS30;
1248 k2Val = DEFAULT_K2_VALUE_FOR_SCS60;
1251 k2Val = DEFAULT_K2_VALUE_FOR_SCS120;
1256 /* Current slot + k2 should be either UL or FLEXI slot.
1257 * If slot is FLEXI then check all the symbols of that slot,
1258 * it should not contain any DL or FLEXI slot */
1259 k2TmpVal = (slotIdx + k2Val) % totalCfgSlot;
1260 slotCfg = schGetSlotSymbFrmt(k2TmpVal, cell->slotFrmtBitMap);
1261 if(slotCfg != DL_SLOT)
1263 if(slotCfg == FLEXI_SLOT)
1265 startSymbol = timeDomRsrcAllocList[k2Index].startSymbol;
1266 endSymbol = startSymbol+ timeDomRsrcAllocList[k2Index].symbolLength;
1267 dlSymbolPresent = false;
1268 for(checkSymbol= startSymbol; checkSymbol<endSymbol; checkSymbol++)
1270 currentSymbol = cell->cellCfg.tddCfg.slotCfg[k2TmpVal][checkSymbol];
1271 if(currentSymbol == DL_SLOT || currentSymbol == FLEXI_SLOT)
1273 dlSymbolPresent = true;
1278 /* Store all the values if all condition satisfies. */
1279 if(dlSymbolPresent != true || slotCfg == UL_SLOT)
1281 numK2 = k2InfoTbl->k2TimingInfo[slotIdx].numK2;
1282 k2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[numK2] = k2Index;
1283 k2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1289 msg3Delta = puschDeltaTable[cell->cellCfg.numerology];
1291 /* Check for K2 for MSG3 */
1292 /* Current slot + k2 should be either UL or FLEXI slot.
1293 * If slot is FLEXI then check all the symbols of that slot,
1294 * it should not contain any DL or FLEXI slot */
1295 msg3K2TmpVal = (slotIdx + k2Val + msg3Delta) % totalCfgSlot;
1296 slotCfg = schGetSlotSymbFrmt(msg3K2TmpVal, cell->slotFrmtBitMap);
1297 if(slotCfg != DL_SLOT)
1299 if(slotCfg == FLEXI_SLOT)
1301 startSymbol = timeDomRsrcAllocList[k2Index].startSymbol;
1302 endSymbol = startSymbol+ timeDomRsrcAllocList[k2Index].symbolLength;
1303 dlSymbolPresent = false;
1304 for(checkSymbol= startSymbol; checkSymbol<endSymbol; checkSymbol++)
1306 currentSymbol = cell->cellCfg.tddCfg.slotCfg[msg3K2TmpVal][checkSymbol];
1307 if(currentSymbol == DL_SLOT || currentSymbol == FLEXI_SLOT)
1309 dlSymbolPresent = true;
1314 /* Store all the values if all condition satisfies. */
1315 if(dlSymbolPresent != true || slotCfg == UL_SLOT)
1317 numK2 = msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2;
1318 msg3K2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[numK2] = k2Index;
1319 msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1330 /**********************************************************************
1332 **********************************************************************/