src/5gnrsch/sch_common.c

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17  *******************************************************************************/
  18
  19 /************************************************************************
  20
  21 Name:     5G NR SCH layer
  22
  23 Type:     C source file
  24
  25 Desc:     C source code for Entry point fucntions
  26
  27 File:     sch_common.c
  28
  29  **********************************************************************/
  30
  31 /** @file sch_common.c
  32   @brief This module performs common scheduling
  33  */
  34 #include "common_def.h"
  35 #include "tfu.h"
  36 #include "lrg.h"
  37
  38 #include "tfu.x"
  39 #include "lrg.x"
  40 #include "du_log.h"
  41 #include "du_app_mac_inf.h"
  42 #include "mac_sch_interface.h"
  43 #include "sch.h"
  44 #include "sch_utils.h"
  45
  46 SchCb schCb[SCH_MAX_INST];
  47 uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
  48 uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
  49 uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
  50
  51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
  52 {
  53    packSchMacUlSchInfo,
  54    MacProcUlSchInfo,
  55    packSchMacUlSchInfo
  56 };
  57
  58 /**
  59  * @brief common resource allocation for SSB
  60  *
  61  * @details
  62  *
  63  *     Function : schBroadcastAlloc
  64  *
  65  *     This function handles common scheduling for DL
  66  *
  67  *  @param[in]  SchCellCb *cell, cell cb
  68  *  @param[in]  DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
  69  *  @return  void
  70  **/
  71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
  72       uint16_t slot)
  73 {
  74    /* schedule SSB */
  75    uint8_t ssbStartPrb, ssbStartSymb, idx;
  76    SchDlSlotInfo *schDlSlotInfo;
  77    SsbInfo ssbInfo;
  78
  79    schDlSlotInfo = cell->schDlSlotInfo[slot];
  80
  81    if(dlBrdcstAlloc->ssbTrans)
  82    {
  83       ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; //+Kssb
  84       ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
  85                                                                                 supporting only 1 ssb beam */
  86
  87       /* Assign interface structure */
  88       for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
  89       {
  90          ssbInfo.ssbIdx              = idx;
  91          ssbInfo.fdAlloc.startPrb    = ssbStartPrb;
  92          ssbInfo.fdAlloc.numPrb      = SCH_SSB_NUM_PRB;
  93          ssbInfo.tdAlloc.startSymb   = ssbStartSymb;
  94          ssbInfo.tdAlloc.numSymb     = SCH_SSB_NUM_SYMB;
  95          dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
  96          schDlSlotInfo->ssbInfo[idx] = ssbInfo;
  97       }
  98
  99       schDlSlotInfo->ssbPres = true;
 100       schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
 101       for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
 102       {
 103          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
 104       }
 105    }
 106
 107    /* SIB1 allocation */
 108    if(dlBrdcstAlloc->sib1Trans)
 109    {
 110       uint16_t tbSize         = 0;
 111       uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 112       uint8_t mcs             = 4;  /* MCS fixed to 4 */
 113       uint8_t numSib1Prb      = 0;
 114       schDlSlotInfo->sib1Pres = true;
 115
 116       tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
 117       numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
 118       for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
 119       {
 120          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
 121       }
 122       memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
 123       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
 124       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
 125       dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
 126    }
 127    return ROK;
 128 }
 129
 130 /*******************************************************************
 131  *
 132  * @brief Handles sending UL scheduler info to MAC
 133  *
 134  * @details
 135  *
 136  *    Function : sendUlSchInfoToMac
 137  *
 138  *    Functionality:
 139  *     Sends UL Sch info to MAC from SCH
 140  *
 141  * @params[in]
 142  * @return ROK     - success
 143  *         RFAILED - failure
 144  *
 145  * ****************************************************************/
 146 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
 147 {
 148    Pst pst;
 149
 150    memset(&pst, 0, sizeof(Pst));
 151    FILL_PST_SCH_TO_MAC(pst, inst);
 152    pst.event = EVENT_UL_SCH_INFO;
 153
 154    return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
 155 }
 156 /**
 157  * @brief resource allocation for PRACH
 158  *
 159  * @details
 160  *
 161  *     Function : schPrachResAlloc
 162  *
 163  *     This function handles PRACH allocation
 164  *
 165  *  @param[in]  SchCellCb *cell, cell cb
 166  *  @param[in]  UlSchedInfo *ulSchedInfo, UL scheduling info
 167  *  @return  void
 168  **/
 169 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
 170 {
 171    uint8_t  puschScs;
 172    uint8_t  numPrachRb = 0;
 173    uint8_t  numRa = 0;
 174    uint8_t  freqStart = 0;
 175    uint8_t  prachCfgIdx = 0;
 176    uint8_t  prachFormat = 0;
 177    uint8_t  x = 0;
 178    uint8_t  y = 0;
 179    uint16_t prachSubframe = 0;
 180    uint8_t  prachStartSymbol = 0;
 181    uint8_t  prachOcas = 0;
 182    uint8_t  dataType = 0;
 183    uint8_t  idx = 0;
 184    uint8_t  subFrame = 0;
 185    SchUlSlotInfo *schUlSlotInfo = NULLP;
 186
 187    puschScs      = cell->cellCfg.schInitialUlBwp.bwp.scs;
 188    schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
 189    prachCfgIdx   = cell->cellCfg.schRachCfg.prachCfgIdx;
 190
 191    /* derive the prachCfgIdx table paramters */
 192    x                = prachCfgIdxTable[prachCfgIdx][1];
 193    y                = prachCfgIdxTable[prachCfgIdx][2];
 194    prachSubframe    = prachCfgIdxTable[prachCfgIdx][3];
 195
 196    if((prachOccasionTimingInfo.sfn%x) == y)
 197    {
 198 #ifdef NR_TDD
 199       subFrame = prachOccasionTimingInfo.slot/2;
 200 #else
 201       subFrame = prachOccasionTimingInfo.slot;
 202 #endif
 203       /* check for subFrame number */
 204       if ((1 << subFrame) & prachSubframe)
 205       {
 206          /* prach ocassion present in this subframe */
 207 #ifdef NR_TDD
 208          if(UL_SLOT != schGetSlotSymbFrmt(prachOccasionTimingInfo.slot%cell->numSlotsInPeriodicity,\
 209          cell->slotFrmtBitMap))
 210          {
 211             DU_LOG("\nERROR  --> SCH : PrachCfgIdx %d doesn't support UL slot", prachCfgIdx);
 212          }
 213          else
 214 #endif
 215          {
 216             prachFormat      = prachCfgIdxTable[prachCfgIdx][0];
 217             prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
 218             prachOcas        = prachCfgIdxTable[prachCfgIdx][6];
 219
 220             /* freq domain resource determination for RACH*/
 221             freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
 222             /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
 223              * where M is given by msg1Fdm */
 224             numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
 225             for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
 226             {
 227                if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
 228                {
 229                   if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
 230                   {
 231                      if(numRbForPrachTable[idx][2] == puschScs)
 232                      {
 233                         break;
 234                      }
 235                   }
 236                }
 237             }
 238             numPrachRb = numRbForPrachTable[idx][3];
 239             dataType |= SCH_DATATYPE_PRACH;
 240             /* Considering first slot in the frame for PRACH */
 241             idx = 0;
 242             schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
 243          }
 244          ulSchedInfo->dataType = dataType;
 245          /* prach info */
 246          ulSchedInfo->prachSchInfo.numPrachOcas   = prachOcas;
 247          ulSchedInfo->prachSchInfo.prachFormat    = prachFormat;
 248          ulSchedInfo->prachSchInfo.numRa          = numRa;
 249          ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
 250          DU_LOG("\nINFO  --> SCH : RACH occassion set for slot %d", prachOccasionTimingInfo.slot);
 251       }
 252    }
 253 }
 254
 255
 256 /**
 257  * @brief Function to fill Pucch Format 0
 258  *
 259  * @details
 260  *
 261  *     Function : fillPucchFormat0
 262  *
 263  *     Function to fill Pucch format 0
 264  *
 265  *  @param[in]  SchPucchInfo pointer, SchPucchResrcInfo pointer
 266  *  @return  void
 267  **/
 268
 269 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
 270 {
 271    if(resrcInfo->SchPucchFormat.format0)
 272    {
 273       ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 274       ulSchedPucch->pucchFormat  = PUCCH_FORMAT_0;
 275       ulSchedPucch->initialCyclicShift =  resrcInfo->SchPucchFormat.format0->initialCyclicShift;
 276       ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
 277       ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
 278    }
 279 }
 280
 281 /**
 282  * @brief Function to fill Pucch Format 1
 283  *
 284  * @details
 285  *
 286  *     Function : fillPucchFormat1
 287  *
 288  *     Function to fill Pucch format 1
 289  *
 290  *  @param[in]  SchPucchInfo pointer, SchPucchResrcInfo pointer
 291  *  @return  void
 292  **/
 293
 294 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
 295 {
 296    if(resrcInfo->SchPucchFormat.format1)
 297    {
 298       ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 299       ulSchedPucch->pucchFormat  = PUCCH_FORMAT_1;
 300       ulSchedPucch->initialCyclicShift =  resrcInfo->SchPucchFormat.format1->initialCyclicShift;
 301       ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
 302       ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
 303       ulSchedPucch->timeDomOCC =  resrcInfo->SchPucchFormat.format1->timeDomOCC;
 304   }
 305 }
 306
 307 /**
 308  * @brief Function to fill Pucch format for UL Sched Info
 309  *
 310  * @details
 311  *
 312  *     Function : fillUlSchedPucchFormat
 313  *
 314  *     Function to fill Pucch format for UL Sched Info
 315  *
 316  *  @param[in]  pucchFormat , SchPucchInfo pointer,
 317  *  @param[in]  SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
 318  *  @return  void
 319  **/
 320
 321 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
 322    SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
 323 {
 324    uint8_t ret = ROK;
 325
 326    switch(pucchFormat)
 327    {
 328       case PUCCH_FORMAT_0:
 329          {
 330             if(resrcInfo)
 331                fillPucchFormat0(ulSchedPucch, resrcInfo);
 332             return ret;
 333          }
 334       case PUCCH_FORMAT_1:
 335          {
 336             if(resrcInfo)
 337             {
 338                fillPucchFormat1(ulSchedPucch, resrcInfo);
 339             }
 340             if(formatCfg)
 341             {
 342                memcpy(&ulSchedPucch->cmnFormatCfg, formatCfg, sizeof(SchPucchFormatCfg));
 343             }
 344             return ret;
 345          }/* To Add support for more Pucch Format */
 346
 347       default:
 348          DU_LOG("\nERROR  --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
 349          ret = RFAILED;
 350          return ret;
 351    }
 352    return ret;
 353 }
 354
 355 /**
 356  * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
 357  *
 358  * @details
 359  *
 360  *     Function : fillUlSchedPucchDedicatedCfg
 361  *
 362  *     Function to fill Pucch Dedicated Cfg for UL Sched Info
 363  *
 364  *  @param[in]  pucchFormat to be filled
 365  *  @param[in]  SchPucchFormatCfg pointer, SchPucchCfg pointer
 366  *  @return  void
 367  **/
 368
 369 uint8_t fillUlSchedPucchDedicatedCfg(uint16_t numSlots, SchPucchCfg *pucchDedCfg,\
 370    SlotIndInfo *slotInfo, SchPucchInfo *ulSchedPucch)
 371 {
 372    uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
 373    uint16_t srOffset = 0;
 374
 375    ret = ROK;
 376    if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
 377    {
 378       //Assuming one entry in the list
 379       for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
 380       {
 381          for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
 382          {
 383             if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
 384                pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
 385             {
 386                ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
 387                ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
 388                ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
 389                ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
 390                ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
 391                         &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
 392                if(ret == RFAILED)
 393                   return ret;
 394             }
 395          }
 396       }
 397    }
 398    if(pucchDedCfg->format1)
 399    {
 400       memset(&ulSchedPucch->cmnFormatCfg, 0, sizeof(SchPucchFormatCfg));
 401       ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
 402       if(ret == RFAILED)
 403          return ret;
 404    }
 405
 406    /* setting SR and UCI flag */
 407    if(pucchDedCfg->schedReq)
 408    {
 409       for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
 410       {
 411          srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
 412          srOffset      = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
 413          break;
 414       }
 415       if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
 416       {
 417          ulSchedPucch->srFlag  = true;
 418          ulSchedPucch->uciFlag = true;
 419       }
 420    }
 421    return ret;
 422 }
 423
 424 /**
 425  * @brief Function to fill Pucch Resource Info
 426  *
 427  * @details
 428  *
 429  *     Function : fillPucchResourceInfo
 430  *
 431  *     Function to fill Pucch Resource Info
 432  *
 433  *  @param[in]  SchPucchInfo *schPucchInfo, Inst inst
 434  *  @return  ROK/RFAILED
 435  **/
 436
 437 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
 438 {
 439    uint8_t ret = ROK, ueIdx = 0, pucchIdx = 0;
 440    SchCellCb  *cell = schCb[inst].cells[inst];
 441    SchPucchCfgCmn *pucchCfg = NULLP;
 442    SchBwpParams *ulBwp = NULLP;
 443
 444    GET_UE_IDX(schPucchInfo->rnti, ueIdx);
 445    if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
 446    {
 447       /* fill pucch dedicated cfg */
 448       ret = fillUlSchedPucchDedicatedCfg(cell->numSlots,\
 449        &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg, &cell->slotInfo, schPucchInfo);
 450       if(ret == RFAILED)
 451       {
 452          memset(schPucchInfo, 0, sizeof(SchPucchInfo));
 453          DU_LOG("\nERROR  --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
 454          return ret;
 455       }
 456    }
 457    else
 458    {
 459       /* fill pucch common cfg */
 460       /* derive pucchResourceSet from schCellCfg */
 461       pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
 462       pucchIdx = pucchCfg->pucchResourceCommon;
 463       ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
 464       schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
 465       schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 466       schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
 467       schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
 468       schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
 469
 470       /* set SR and UCI flag to false */
 471       schPucchInfo->srFlag  = true;
 472       schPucchInfo->uciFlag = true;
 473    }
 474    /* set HARQ flag to true */
 475    schPucchInfo->harqFlag = true;
 476    schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
 477
 478    return ROK;
 479 }
 480
 481 /**
 482  * @brief resource allocation for UL
 483  *
 484  * @details
 485  *
 486  *     Function : schUlResAlloc
 487  *
 488  *     This function handles UL Resource allocation
 489  *
 490  *  @param[in]  SchCellCb *cell, cellCb
 491  *  @return  void
 492  **/
 493 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
 494 {
 495    int ret = ROK;
 496    UlSchedInfo ulSchedInfo;
 497    SchUlSlotInfo  *schUlSlotInfo = NULLP;
 498    SlotIndInfo ulTimingInfo;
 499    memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
 500
 501    /* add PHY delta */
 502    ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA_UL+SCHED_DELTA);
 503
 504    ulSchedInfo.cellId = cell->cellId;
 505    ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
 506    ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
 507    ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
 508
 509    /* Schedule resources for PRACH */
 510    if(cell->firstSib1Transmitted)
 511     schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
 512
 513    schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
 514    if(schUlSlotInfo->schPuschInfo)
 515    {
 516       ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
 517       ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
 518       memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
 519             sizeof(SchPuschInfo));
 520       SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
 521       schUlSlotInfo->schPuschInfo = NULL;
 522    }
 523
 524    if(schUlSlotInfo->pucchPres)
 525    {
 526       ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
 527       fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
 528       memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
 529             sizeof(SchPucchInfo));
 530       memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 531    }
 532
 533    //send msg to MAC
 534    ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
 535    if(ret != ROK)
 536    {
 537       DU_LOG("\nERROR  -->  SCH : Sending UL Sch info from SCH to MAC failed");
 538    }
 539
 540    schInitUlSlot(schUlSlotInfo);
 541    return ret;
 542 }
 543
 544 /*******************************************************************
 545  *
 546  * @brief Fills pdcch and pdsch info for msg4
 547  *
 548  * @details
 549  *
 550  *    Function : schDlRsrcAllocMsg4
 551  *
 552  *    Functionality:
 553  *       Fills pdcch and pdsch info for msg4
 554  *
 555  * @params[in]
 556  * @return ROK     - success
 557  *         RFAILED - failure
 558  *
 559  * ****************************************************************/
 560 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
 561 {
 562    uint8_t coreset0Idx = 0;
 563    uint8_t numRbs = 0;
 564    uint8_t firstSymbol = 0;
 565    uint8_t numSymbols = 0;
 566    uint8_t offset = 0;
 567    uint8_t offsetPointA;
 568    uint8_t FreqDomainResource[6] = {0};
 569    uint16_t tbSize = 0;
 570    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 571    uint8_t mcs = 4;  /* MCS fixed to 4 */
 572    SchBwpDlCfg *initialBwp;
 573
 574    PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
 575    PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
 576    BwpCfg *bwp = &msg4Alloc->bwp;
 577
 578    initialBwp   = &cell->cellCfg.schInitialDlBwp;
 579    offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
 580    coreset0Idx  = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
 581
 582    /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
 583    numRbs        = coresetIdxTable[coreset0Idx][1];
 584    numSymbols    = coresetIdxTable[coreset0Idx][2];
 585    offset        = coresetIdxTable[coreset0Idx][3];
 586
 587    /* calculate time domain parameters */
 588    uint16_t mask = 0x2000;
 589    for(firstSymbol=0; firstSymbol<14;firstSymbol++)
 590    {
 591       if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
 592          break;
 593       else
 594          mask = mask>>1;
 595    }
 596
 597    /* calculate the PRBs */
 598    freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
 599
 600    /* fill BWP */
 601    bwp->freqAlloc.numPrb   = initialBwp->bwp.freqAlloc.numPrb;
 602    bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
 603    bwp->subcarrierSpacing  = initialBwp->bwp.scs;
 604    bwp->cyclicPrefix       = initialBwp->bwp.cyclicPrefix;
 605
 606    /* fill the PDCCH PDU */
 607    pdcch->coresetCfg.startSymbolIndex = firstSymbol;
 608    pdcch->coresetCfg.durationSymbols = numSymbols;
 609    memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
 610    pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
 611    pdcch->coresetCfg.regBundleSize = 6;    /* spec-38.211 sec 7.3.2.2 */
 612    pdcch->coresetCfg.interleaverSize = 2;  /* spec-38.211 sec 7.3.2.2 */
 613    pdcch->coresetCfg.coreSetType = 0;
 614    pdcch->coresetCfg.coreSetSize = numRbs;
 615    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
 616    pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
 617    pdcch->numDlDci = 1;
 618    pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
 619    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
 620    pdcch->dci.scramblingRnti = 0;
 621    pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
 622    pdcch->dci.aggregLevel = 4;
 623    pdcch->dci.beamPdcchInfo.numPrgs = 1;
 624    pdcch->dci.beamPdcchInfo.prgSize = 1;
 625    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
 626    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
 627    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
 628    pdcch->dci.txPdcchPower.powerValue = 0;
 629    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
 630
 631    /* fill the PDSCH PDU */
 632    uint8_t cwCount = 0;
 633    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
 634    pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
 635    pdsch->pduIndex = 0;
 636    pdsch->numCodewords = 1;
 637    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
 638    {
 639       pdsch->codeword[cwCount].targetCodeRate = 308;
 640       pdsch->codeword[cwCount].qamModOrder = 2;
 641       pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
 642       pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
 643       pdsch->codeword[cwCount].rvIndex = 0;
 644       /* 38.214: Table 5.1.3.2-1,  divided by 8 to get the value in bytes */
 645       /* TODO : Calculate tbSize based of DL CCCH msg size */
 646       tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
 647       pdsch->codeword[cwCount].tbSize = tbSize;
 648    }
 649    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
 650    pdsch->numLayers = 1;
 651    pdsch->transmissionScheme = 0;
 652    pdsch->refPoint = 0;
 653    pdsch->dmrs.dlDmrsSymbPos = 2;
 654    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
 655    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
 656    pdsch->dmrs.scid = 0;
 657    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
 658    pdsch->dmrs.dmrsPorts = 0;
 659    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
 660    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
 661    pdsch->dmrs.dmrsAddPos       = DMRS_ADDITIONAL_POS;
 662    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
 663    /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
 664    pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
 665    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
 666    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
 667    pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
 668    pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
 669    pdsch->beamPdschInfo.numPrgs = 1;
 670    pdsch->beamPdschInfo.prgSize = 1;
 671    pdsch->beamPdschInfo.digBfInterfaces = 0;
 672    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
 673    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
 674    pdsch->txPdschPower.powerControlOffset = 0;
 675    pdsch->txPdschPower.powerControlOffsetSS = 0;
 676
 677    pdcch->dci.pdschCfg = pdsch;
 678
 679    return ROK;
 680 }
 681
 682 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot)
 683 {
 684    uint8_t k1 = SCH_DEFAULT_K1, ueIdx = 0, dlToUlAckIdx;
 685    uint16_t pucchSlot = 0;
 686    SchUlSlotInfo  *schUlSlotInfo = NULLP;
 687    SchPucchCfg    *schPucchCfg = NULLP;
 688
 689    GET_UE_IDX(crnti, ueIdx);
 690    if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
 691    {
 692       schPucchCfg = &(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg);
 693      if(schPucchCfg->dlDataToUlAck)
 694      {
 695         for(dlToUlAckIdx = 0; dlToUlAckIdx < schPucchCfg->dlDataToUlAck->dlDataToUlAckListCount; dlToUlAckIdx++)
 696         {
 697            //For now considering only the first value in the list
 698            k1 = schPucchCfg->dlDataToUlAck->dlDataToUlAckList[dlToUlAckIdx];
 699            break;
 700         }
 701      }
 702    }
 703
 704    pucchSlot = (slot + k1)  % cell->numSlots;
 705    schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
 706    memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 707
 708    schUlSlotInfo->pucchPres = true;
 709    schUlSlotInfo->schPucchInfo.rnti = crnti;
 710
 711    return ROK;
 712 }
 713
 714 /*******************************************************************
 715  *
 716  * @brief Fills pdcch and pdsch info for dedicated DL msg
 717  *
 718  * @details
 719  *
 720  *    Function : schDlRsrcAllocDlMsg
 721  *
 722  *    Functionality:
 723  *       Fills pdcch and pdsch info for dl msg
 724  *
 725  * @params[in]
 726  * @return ROK     - success
 727  *         RFAILED - failure
 728  *
 729  * ****************************************************************/
 730 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
 731       uint32_t *accumalatedSize, uint16_t slot)
 732 {
 733    uint8_t ueIdx;
 734    uint16_t tbSize = 0;
 735    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 736    PdcchCfg *pdcch = NULLP;
 737    PdschCfg *pdsch = NULLP;
 738    BwpCfg *bwp = NULLP;
 739    SchUeCb ueCb;
 740    SchControlRsrcSet coreset1;
 741    SchPdschConfig pdschCfg;
 742
 743    pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
 744    pdsch = &dlMsgAlloc->dlMsgPdschCfg;
 745    bwp = &dlMsgAlloc->bwp;
 746
 747    GET_UE_IDX(crnti, ueIdx);
 748    ueCb  = cell->ueCb[ueIdx-1];
 749    coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
 750    pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
 751
 752    /* fill BWP */
 753    bwp->freqAlloc.numPrb = MAX_NUM_RB;
 754    bwp->freqAlloc.startPrb = 0;
 755    bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
 756    bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
 757
 758    /* fill the PDCCH PDU */
 759    //Considering coreset1 also starts from same symbol as coreset0
 760    pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
 761    pdcch->coresetCfg.durationSymbols = coreset1.duration;
 762    memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
 763    pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
 764    pdcch->coresetCfg.regBundleSize = 6;   /* must be 6 for non-interleaved */
 765    pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
 766    pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
 767    //Considering number of RBs in coreset1 is same as coreset0
 768    pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
 769    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
 770    pdcch->coresetCfg.precoderGranularity =  coreset1.precoderGranularity;
 771    pdcch->numDlDci = 1;
 772    pdcch->dci.rnti = ueCb.crnti;
 773    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
 774    pdcch->dci.scramblingRnti = 0;
 775    pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
 776    pdcch->dci.aggregLevel = 4;
 777    pdcch->dci.beamPdcchInfo.numPrgs = 1;
 778    pdcch->dci.beamPdcchInfo.prgSize = 1;
 779    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
 780    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
 781    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
 782    pdcch->dci.txPdcchPower.powerValue = 0;
 783    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
 784
 785    /* fill the PDSCH PDU */
 786    uint8_t cwCount = 0;
 787    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
 788    pdsch->rnti = ueCb.crnti;
 789    pdsch->pduIndex = 0;
 790    pdsch->numCodewords = 1;
 791    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
 792    {
 793       pdsch->codeword[cwCount].targetCodeRate = 308;
 794       pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
 795       pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
 796       pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
 797       pdsch->codeword[cwCount].rvIndex = 0;
 798       tbSize = schCalcTbSize(*accumalatedSize);
 799       if(tbSize < *accumalatedSize)
 800          *accumalatedSize = tbSize;
 801       pdsch->codeword[cwCount].tbSize = tbSize;
 802    }
 803    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
 804    pdsch->numLayers = 1;
 805    pdsch->transmissionScheme = 0;
 806    pdsch->refPoint = 0;
 807    pdsch->dmrs.dlDmrsSymbPos = 2;
 808    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
 809    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
 810    pdsch->dmrs.scid = 0;
 811    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
 812    pdsch->dmrs.dmrsPorts = 0;
 813    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
 814    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
 815    pdsch->dmrs.dmrsAddPos       = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
 816    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
 817    pdsch->pdschFreqAlloc.freqAlloc.startPrb = 1;
 818    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, numPdschSymbols);
 819    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
 820    pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
 821    pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
 822    pdsch->beamPdschInfo.numPrgs = 1;
 823    pdsch->beamPdschInfo.prgSize = 1;
 824    pdsch->beamPdschInfo.digBfInterfaces = 0;
 825    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
 826    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
 827    pdsch->txPdschPower.powerControlOffset = 0;
 828    pdsch->txPdschPower.powerControlOffsetSS = 0;
 829
 830    pdcch->dci.pdschCfg = pdsch;
 831    return ROK;
 832 }
 833
 834 /**********************************************************************
 835   End of file
 836  **********************************************************************/
 837