src/5gnrsch/sch_common.c

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
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   7 #   You may obtain a copy of the License at                                    #
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  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17  *******************************************************************************/
  18
  19 /************************************************************************
  20
  21 Name:     5G NR SCH layer
  22
  23 Type:     C source file
  24
  25 Desc:     C source code for Entry point fucntions
  26
  27 File:     sch_common.c
  28
  29  **********************************************************************/
  30
  31 /** @file sch_common.c
  32   @brief This module performs common scheduling
  33  */
  34 #include "common_def.h"
  35 #include "tfu.h"
  36 #include "lrg.h"
  37
  38 #include "tfu.x"
  39 #include "lrg.x"
  40 #include "du_log.h"
  41 #include "du_app_mac_inf.h"
  42 #include "mac_sch_interface.h"
  43 #include "sch.h"
  44 #include "sch_utils.h"
  45
  46 extern SchCb schCb[SCH_MAX_INST];
  47 extern uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
  48 extern uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
  49 extern uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
  50
  51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
  52 {
  53         packSchMacUlSchInfo,
  54         MacProcUlSchInfo,
  55         packSchMacUlSchInfo
  56 };
  57
  58 /**
  59  * @brief common resource allocation for SSB
  60  *
  61  * @details
  62  *
  63  *     Function : schBroadcastAlloc
  64  *
  65  *     This function handles common scheduling for DL
  66  *
  67  *  @param[in]  SchCellCb *cell, cell cb
  68  *  @param[in]  DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
  69  *  @return  void
  70  **/
  71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
  72         uint16_t slot)
  73 {
  74         /* schedule SSB */
  75         uint8_t ssbStartPrb, ssbStartSymb, idx;
  76         SchDlSlotInfo *schDlSlotInfo;
  77         SsbInfo ssbInfo;
  78
  79         schDlSlotInfo = cell->schDlSlotInfo[slot];
  80         if(dlBrdcstAlloc->ssbTrans)
  81         {
  82                 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
  83       ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
  84                 supporting only 1 ssb beam */
  85
  86                 /* Assign interface structure */
  87                 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
  88                 {
  89                         ssbInfo.ssbIdx              = idx;
  90                         ssbInfo.fdAlloc.startPrb    = ssbStartPrb;
  91                         ssbInfo.fdAlloc.numPrb      = SCH_SSB_NUM_PRB;
  92                         ssbInfo.tdAlloc.startSymb   = ssbStartSymb;
  93                         ssbInfo.tdAlloc.numSymb     = SCH_SSB_NUM_SYMB;
  94                         dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
  95                         schDlSlotInfo->ssbInfo[idx] = ssbInfo;
  96                 }
  97
  98                 schDlSlotInfo->ssbPres = true;
  99                 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
 100                 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
 101                 {
 102                         schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
 103                 }
 104         }
 105
 106         /* SIB1 allocation */
 107         if(dlBrdcstAlloc->sib1Trans)
 108         {
 109                 schDlSlotInfo->sib1Pres = true;
 110                 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
 111                 {
 112                         schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + 10; /* 10 PRBs for sib1 */
 113                 }
 114            memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
 115            memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
 116            memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
 117         }
 118         return ROK;
 119 }
 120
 121 /*******************************************************************
 122  *
 123  * @brief Handles sending UL scheduler info to MAC
 124  *
 125  * @details
 126  *
 127  *    Function : sendUlSchInfoToMac
 128  *
 129  *    Functionality:
 130  *     Sends UL Sch info to MAC from SCH
 131  *
 132  * @params[in]
 133  * @return ROK     - success
 134  *         RFAILED - failure
 135  *
 136  * ****************************************************************/
 137 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
 138 {
 139         Pst pst;
 140
 141    memset(&pst, 0, sizeof(Pst));
 142    SCH_FILL_RSP_PST(pst, inst);
 143         pst.event = EVENT_UL_SCH_INFO;
 144
 145         return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
 146 }
 147 /**
 148  * @brief resource allocation for PRACH
 149  *
 150  * @details
 151  *
 152  *     Function : schPrachResAlloc
 153  *
 154  *     This function handles PRACH allocation
 155  *
 156  *  @param[in]  SchCellCb *cell, cell cb
 157  *  @param[in]  UlSchedInfo *ulSchedInfo, UL scheduling info
 158  *  @return  void
 159  **/
 160 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
 161 {
 162    uint8_t  puschScs;
 163    uint8_t  numPrachRb = 0;
 164         uint8_t  numRa = 0;
 165         uint8_t  freqStart = 0;
 166         uint8_t  prachCfgIdx = 0;
 167         uint8_t  prachFormat = 0;
 168         uint8_t  x = 0;
 169         uint8_t  y = 0;
 170         uint16_t prachSubframe = 0;
 171         uint8_t  prachStartSymbol = 0;
 172         uint8_t  prachOcas = 0;
 173         uint8_t  dataType = 0;
 174         uint8_t  idx = 0;
 175         SchUlSlotInfo *schUlSlotInfo = NULLP;
 176
 177    puschScs      = cell->cellCfg.schInitialUlBwp.bwp.scs;
 178         schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
 179         prachCfgIdx   = cell->cellCfg.schRachCfg.prachCfgIdx;
 180
 181     /* derive the prachCfgIdx table paramters */
 182         x                = prachCfgIdxTable[prachCfgIdx][1];
 183         y                = prachCfgIdxTable[prachCfgIdx][2];
 184         prachSubframe    = prachCfgIdxTable[prachCfgIdx][3];
 185
 186         if((prachOccasionTimingInfo.sfn%x) == y)
 187         {
 188            /* check for subFrame number */
 189            if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
 190            {
 191          /* prach ocassion present in this subframe */
 192
 193                 prachFormat      = prachCfgIdxTable[prachCfgIdx][0];
 194                 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
 195                 prachOcas        = prachCfgIdxTable[prachCfgIdx][6];
 196
 197                 /* freq domain resource determination for RACH*/
 198                 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
 199                 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
 200                  * where M is given by msg1Fdm */
 201                 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
 202                 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
 203                 {
 204                         if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
 205                         {
 206                                 if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
 207                                 {
 208                                         if(numRbForPrachTable[idx][2] == puschScs)
 209                                         {
 210                                                 break;
 211                                         }
 212                                 }
 213                         }
 214                 }
 215                 numPrachRb = numRbForPrachTable[idx][3];
 216                 dataType |= SCH_DATATYPE_PRACH;
 217                 /* Considering first slot in the frame for PRACH */
 218                 idx = 0;
 219                 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
 220            }
 221            ulSchedInfo->dataType = dataType;
 222            /* prach info */
 223            ulSchedInfo->prachSchInfo.numPrachOcas   = prachOcas;
 224            ulSchedInfo->prachSchInfo.prachFormat    = prachFormat;
 225            ulSchedInfo->prachSchInfo.numRa          = numRa;
 226            ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
 227         }
 228 }
 229
 230 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
 231 {
 232    /* derive pucchResourceSet from schCellCfg */
 233    SchCellCb  *cell = schCb[inst].cells[inst];
 234    SchPucchCfgCmn *pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
 235         uint8_t pucchIdx = pucchCfg->pucchResourceCommon;
 236         SchBwpParams *ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
 237
 238    schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
 239    schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0;
 240    schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
 241    schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
 242         schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
 243
 244    /* set HARQ flag to true */
 245    schPucchInfo->harqFlag = true;
 246    schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
 247
 248    /* set SR and UCI flag to false */
 249    schPucchInfo->srFlag  = false;
 250    schPucchInfo->uciFlag = false;
 251
 252    return ROK;
 253 }
 254
 255 /**
 256  * @brief resource allocation for UL
 257  *
 258  * @details
 259  *
 260  *     Function : schUlResAlloc
 261  *
 262  *     This function handles UL Resource allocation
 263  *
 264  *  @param[in]  SchCellCb *cell, cellCb
 265  *  @return  void
 266  **/
 267 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
 268 {
 269    int ret = ROK;
 270         UlSchedInfo ulSchedInfo;
 271    SchUlSlotInfo  *schUlSlotInfo = NULLP;
 272    SlotIndInfo ulTimingInfo;
 273         memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
 274
 275    /* add PHY delta */
 276    ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA+SCHED_DELTA);
 277
 278         ulSchedInfo.cellId = cell->cellId;
 279         ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
 280    ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
 281
 282    /* Schedule resources for PRACH */
 283         schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
 284
 285         schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
 286         if(schUlSlotInfo->schPuschInfo)
 287         {
 288       ulSchedInfo.crnti = cell->raCb[0].tcrnti;
 289                 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
 290                 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
 291                                 sizeof(SchPuschInfo));
 292                 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
 293                 schUlSlotInfo->schPuschInfo = NULL;
 294         }
 295
 296         if(schUlSlotInfo->pucchPres)
 297         {
 298                 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
 299                 fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
 300                 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
 301                                 sizeof(SchPucchInfo));
 302                 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 303         }
 304
 305         //send msg to MAC
 306    ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
 307    if(ret != ROK)
 308    {
 309       DU_LOG("\nSending UL Sch info from SCH to MAC failed");
 310    }
 311         memset(cell->schUlSlotInfo[ulTimingInfo.slot], 0, sizeof(SchUlSlotInfo));
 312
 313         return ret;
 314 }
 315
 316 /*******************************************************************
 317  *
 318  * @brief Fills pdcch and pdsch info for msg4
 319  *
 320  * @details
 321  *
 322  *    Function : schDlRsrcAllocMsg4
 323  *
 324  *    Functionality:
 325  *       Fills pdcch and pdsch info for msg4
 326  *
 327  * @params[in]
 328  * @return ROK     - success
 329  *         RFAILED - failure
 330  *
 331  * ****************************************************************/
 332 uint8_t schDlRsrcAllocMsg4(Msg4Alloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
 333 {
 334    uint8_t coreset0Idx = 0;
 335    uint8_t numRbs = 0;
 336    uint8_t firstSymbol = 0;
 337    uint8_t numSymbols = 0;
 338    uint8_t offset = 0;
 339    uint8_t offsetPointA;
 340    uint8_t FreqDomainResource[6] = {0};
 341    uint16_t tbSize = 0;
 342         uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 343    uint8_t mcs = 4;  /* MCS fixed to 4 */
 344    SchBwpDlCfg *initialBwp;
 345
 346    PdcchCfg *pdcch = &msg4Alloc->msg4PdcchCfg;
 347    PdschCfg *pdsch = &msg4Alloc->msg4PdschCfg;
 348    BwpCfg *bwp = &msg4Alloc->bwp;
 349
 350    initialBwp   = &cell->cellCfg.schInitialDlBwp;
 351    offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
 352    coreset0Idx  = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
 353
 354    /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
 355    numRbs        = coresetIdxTable[coreset0Idx][1];
 356    numSymbols    = coresetIdxTable[coreset0Idx][2];
 357    offset        = coresetIdxTable[coreset0Idx][3];
 358
 359    /* calculate time domain parameters */
 360    uint16_t mask = 0x2000;
 361    for(firstSymbol=0; firstSymbol<14;firstSymbol++)
 362    {
 363       if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
 364          break;
 365       else
 366          mask = mask>>1;
 367    }
 368
 369    /* calculate the PRBs */
 370    schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
 371
 372    /* fill BWP */
 373    bwp->freqAlloc.numPrb   = initialBwp->bwp.freqAlloc.numPrb;
 374    bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
 375    bwp->subcarrierSpacing  = initialBwp->bwp.scs;
 376    bwp->cyclicPrefix       = initialBwp->bwp.cyclicPrefix;
 377
 378    /* fill the PDCCH PDU */
 379    pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
 380    pdcch->coreset0Cfg.durationSymbols = numSymbols;
 381    memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
 382    pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
 383    pdcch->coreset0Cfg.regBundleSize = 6;    /* spec-38.211 sec 7.3.2.2 */
 384    pdcch->coreset0Cfg.interleaverSize = 2;  /* spec-38.211 sec 7.3.2.2 */
 385    pdcch->coreset0Cfg.coreSetType = 0;
 386    pdcch->coreset0Cfg.coreSet0Size = numRbs;
 387    pdcch->coreset0Cfg.shiftIndex = cell->cellCfg.phyCellId;
 388    pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
 389    pdcch->numDlDci = 1;
 390    pdcch->dci.rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
 391    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
 392    pdcch->dci.scramblingRnti = 0;
 393    pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
 394    pdcch->dci.aggregLevel = 4;
 395    pdcch->dci.beamPdcchInfo.numPrgs = 1;
 396    pdcch->dci.beamPdcchInfo.prgSize = 1;
 397    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
 398    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
 399    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
 400    pdcch->dci.txPdcchPower.powerValue = 0;
 401    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
 402
 403    /* fill the PDSCH PDU */
 404    uint8_t cwCount = 0;
 405    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
 406    pdsch->rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
 407    pdsch->pduIndex = 0;
 408    pdsch->numCodewords = 1;
 409    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
 410    {
 411       pdsch->codeword[cwCount].targetCodeRate = 308;
 412       pdsch->codeword[cwCount].qamModOrder = 2;
 413       pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
 414       pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
 415       pdsch->codeword[cwCount].rvIndex = 0;
 416       /* 38.214: Table 5.1.3.2-1,  divided by 8 to get the value in bytes */
 417       /* TODO : Calculate tbSize based of DL CCCH msg size */
 418                 tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
 419       pdsch->codeword[cwCount].tbSize = tbSize;
 420    }
 421    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
 422    pdsch->numLayers = 1;
 423    pdsch->transmissionScheme = 0;
 424    pdsch->refPoint = 0;
 425    pdsch->dmrs.dlDmrsSymbPos = 2;
 426    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
 427    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
 428    pdsch->dmrs.scid = 0;
 429    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
 430    pdsch->dmrs.dmrsPorts = 0;
 431    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
 432    /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
 433    pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
 434    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
 435    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
 436    pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
 437    pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
 438    pdsch->beamPdschInfo.numPrgs = 1;
 439    pdsch->beamPdschInfo.prgSize = 1;
 440    pdsch->beamPdschInfo.digBfInterfaces = 0;
 441    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
 442    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
 443    pdsch->txPdschPower.powerControlOffset = 0;
 444    pdsch->txPdschPower.powerControlOffsetSS = 0;
 445
 446    pdcch->dci.pdschCfg = pdsch;
 447    return ROK;
 448 }
 449
 450 uint16_t schAllocPucchResource(SchCellCb *cell,uint16_t crnti, uint16_t slot)
 451 {
 452    uint8_t k1 = 1; /* dl-DataToUL-ACK RRC parameter will received from DU-APP msg4-pucch config */
 453    uint16_t pucchSlot = (slot + k1)  % SCH_NUM_SLOTS;
 454         SchUlSlotInfo  *schUlSlotInfo = NULLP;
 455
 456         schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
 457         memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 458
 459         schUlSlotInfo->pucchPres = true;
 460         schUlSlotInfo->schPucchInfo.rnti = crnti;
 461
 462    return ROK;
 463 }
 464
 465 /**********************************************************************
 466   End of file
 467  **********************************************************************/
 468