src/5gnrsch/sch_common.c

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
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  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
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  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17  *******************************************************************************/
  18
  19 /************************************************************************
  20
  21 Name:     5G NR SCH layer
  22
  23 Type:     C source file
  24
  25 Desc:     C source code for Entry point fucntions
  26
  27 File:     sch_common.c
  28
  29  **********************************************************************/
  30
  31 /** @file sch_common.c
  32   @brief This module performs common scheduling
  33  */
  34 #include "common_def.h"
  35 #include "tfu.h"
  36 #include "lrg.h"
  37
  38 #include "tfu.x"
  39 #include "lrg.x"
  40 #include "du_log.h"
  41 #include "du_app_mac_inf.h"
  42 #include "mac_sch_interface.h"
  43 #include "sch.h"
  44 #include "sch_utils.h"
  45
  46 SchCb schCb[SCH_MAX_INST];
  47 uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
  48 uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
  49 uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
  50
  51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
  52 {
  53    packSchMacUlSchInfo,
  54    MacProcUlSchInfo,
  55    packSchMacUlSchInfo
  56 };
  57
  58 /**
  59  * @brief common resource allocation for SSB
  60  *
  61  * @details
  62  *
  63  *     Function : schBroadcastAlloc
  64  *
  65  *     This function handles common scheduling for DL
  66  *
  67  *  @param[in]  SchCellCb *cell, cell cb
  68  *  @param[in]  DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
  69  *  @return  void
  70  **/
  71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
  72       uint16_t slot)
  73 {
  74    /* schedule SSB */
  75    uint8_t ssbStartPrb, ssbStartSymb, idx;
  76    SchDlSlotInfo *schDlSlotInfo;
  77    SsbInfo ssbInfo;
  78
  79    schDlSlotInfo = cell->schDlSlotInfo[slot];
  80    if(dlBrdcstAlloc->ssbTrans)
  81    {
  82       ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
  83       ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
  84                                                                                 supporting only 1 ssb beam */
  85
  86       /* Assign interface structure */
  87       for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
  88       {
  89          ssbInfo.ssbIdx              = idx;
  90          ssbInfo.fdAlloc.startPrb    = ssbStartPrb;
  91          ssbInfo.fdAlloc.numPrb      = SCH_SSB_NUM_PRB;
  92          ssbInfo.tdAlloc.startSymb   = ssbStartSymb;
  93          ssbInfo.tdAlloc.numSymb     = SCH_SSB_NUM_SYMB;
  94          dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
  95          schDlSlotInfo->ssbInfo[idx] = ssbInfo;
  96       }
  97
  98       schDlSlotInfo->ssbPres = true;
  99       schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
 100       for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
 101       {
 102          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
 103       }
 104    }
 105
 106    /* SIB1 allocation */
 107    if(dlBrdcstAlloc->sib1Trans)
 108    {
 109       uint16_t tbSize         = 0;
 110       uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 111       uint8_t mcs             = 4;  /* MCS fixed to 4 */
 112       uint8_t numSib1Prb      = 0;
 113       schDlSlotInfo->sib1Pres = true;
 114
 115       tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
 116       numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
 117       for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
 118       {
 119          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
 120       }
 121       memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
 122       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
 123       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
 124       dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
 125    }
 126    return ROK;
 127 }
 128
 129 /*******************************************************************
 130  *
 131  * @brief Handles sending UL scheduler info to MAC
 132  *
 133  * @details
 134  *
 135  *    Function : sendUlSchInfoToMac
 136  *
 137  *    Functionality:
 138  *     Sends UL Sch info to MAC from SCH
 139  *
 140  * @params[in]
 141  * @return ROK     - success
 142  *         RFAILED - failure
 143  *
 144  * ****************************************************************/
 145 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
 146 {
 147    Pst pst;
 148
 149    memset(&pst, 0, sizeof(Pst));
 150    FILL_PST_SCH_TO_MAC(pst, inst);
 151    pst.event = EVENT_UL_SCH_INFO;
 152
 153    return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
 154 }
 155 /**
 156  * @brief resource allocation for PRACH
 157  *
 158  * @details
 159  *
 160  *     Function : schPrachResAlloc
 161  *
 162  *     This function handles PRACH allocation
 163  *
 164  *  @param[in]  SchCellCb *cell, cell cb
 165  *  @param[in]  UlSchedInfo *ulSchedInfo, UL scheduling info
 166  *  @return  void
 167  **/
 168 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
 169 {
 170    uint8_t  puschScs;
 171    uint8_t  numPrachRb = 0;
 172    uint8_t  numRa = 0;
 173    uint8_t  freqStart = 0;
 174    uint8_t  prachCfgIdx = 0;
 175    uint8_t  prachFormat = 0;
 176    uint8_t  x = 0;
 177    uint8_t  y = 0;
 178    uint16_t prachSubframe = 0;
 179    uint8_t  prachStartSymbol = 0;
 180    uint8_t  prachOcas = 0;
 181    uint8_t  dataType = 0;
 182    uint8_t  idx = 0;
 183    SchUlSlotInfo *schUlSlotInfo = NULLP;
 184
 185    puschScs      = cell->cellCfg.schInitialUlBwp.bwp.scs;
 186    schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
 187    prachCfgIdx   = cell->cellCfg.schRachCfg.prachCfgIdx;
 188
 189    /* derive the prachCfgIdx table paramters */
 190    x                = prachCfgIdxTable[prachCfgIdx][1];
 191    y                = prachCfgIdxTable[prachCfgIdx][2];
 192    prachSubframe    = prachCfgIdxTable[prachCfgIdx][3];
 193
 194    if((prachOccasionTimingInfo.sfn%x) == y)
 195    {
 196       /* check for subFrame number */
 197       if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
 198       {
 199          /* prach ocassion present in this subframe */
 200
 201          prachFormat      = prachCfgIdxTable[prachCfgIdx][0];
 202          prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
 203          prachOcas        = prachCfgIdxTable[prachCfgIdx][6];
 204
 205          /* freq domain resource determination for RACH*/
 206          freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
 207          /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
 208           * where M is given by msg1Fdm */
 209          numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
 210          for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
 211          {
 212             if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
 213             {
 214                if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
 215                {
 216                   if(numRbForPrachTable[idx][2] == puschScs)
 217                   {
 218                      break;
 219                   }
 220                }
 221             }
 222          }
 223          numPrachRb = numRbForPrachTable[idx][3];
 224          dataType |= SCH_DATATYPE_PRACH;
 225          /* Considering first slot in the frame for PRACH */
 226          idx = 0;
 227          schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
 228       }
 229       ulSchedInfo->dataType = dataType;
 230       /* prach info */
 231       ulSchedInfo->prachSchInfo.numPrachOcas   = prachOcas;
 232       ulSchedInfo->prachSchInfo.prachFormat    = prachFormat;
 233       ulSchedInfo->prachSchInfo.numRa          = numRa;
 234       ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
 235    }
 236 }
 237
 238
 239 /**
 240  * @brief Function to fill Pucch Format 0
 241  *
 242  * @details
 243  *
 244  *     Function : fillPucchFormat0
 245  *
 246  *     Function to fill Pucch format 0
 247  *
 248  *  @param[in]  SchPucchInfo pointer, SchPucchResrcInfo pointer
 249  *  @return  void
 250  **/
 251
 252 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
 253 {
 254    if(resrcInfo->SchPucchFormat.format0)
 255    {
 256       ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 257       ulSchedPucch->pucchFormat  = PUCCH_FORMAT_0;
 258       ulSchedPucch->initialCyclicShift =  resrcInfo->SchPucchFormat.format0->initialCyclicShift;
 259       ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
 260       ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
 261    }
 262 }
 263
 264 /**
 265  * @brief Function to fill Pucch Format 1
 266  *
 267  * @details
 268  *
 269  *     Function : fillPucchFormat1
 270  *
 271  *     Function to fill Pucch format 1
 272  *
 273  *  @param[in]  SchPucchInfo pointer, SchPucchResrcInfo pointer
 274  *  @return  void
 275  **/
 276
 277 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
 278 {
 279    if(resrcInfo->SchPucchFormat.format1)
 280    {
 281       ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 282       ulSchedPucch->pucchFormat  = PUCCH_FORMAT_1;
 283       ulSchedPucch->initialCyclicShift =  resrcInfo->SchPucchFormat.format1->initialCyclicShift;
 284       ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
 285       ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
 286       ulSchedPucch->timeDomOCC =  resrcInfo->SchPucchFormat.format1->timeDomOCC;
 287   }
 288 }
 289
 290 /**
 291  * @brief Function to fill Pucch format for UL Sched Info
 292  *
 293  * @details
 294  *
 295  *     Function : fillUlSchedPucchFormat
 296  *
 297  *     Function to fill Pucch format for UL Sched Info
 298  *
 299  *  @param[in]  pucchFormat , SchPucchInfo pointer,
 300  *  @param[in]  SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
 301  *  @return  void
 302  **/
 303
 304 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
 305    SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
 306 {
 307    uint8_t ret = ROK;
 308
 309    switch(pucchFormat)
 310    {
 311       case PUCCH_FORMAT_0:
 312          {
 313             if(resrcInfo)
 314                fillPucchFormat0(ulSchedPucch, resrcInfo);
 315             return ret;
 316          }
 317       case PUCCH_FORMAT_1:
 318          {
 319             if(resrcInfo)
 320             {
 321                fillPucchFormat1(ulSchedPucch, resrcInfo);
 322             }
 323             if(formatCfg)
 324             {
 325                memcpy(&ulSchedPucch->cmnFormatCfg, formatCfg, sizeof(SchPucchFormatCfg));
 326             }
 327             return ret;
 328          }/* To Add support for more Pucch Format */
 329
 330       default:
 331          DU_LOG("\nERROR  --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
 332          ret = RFAILED;
 333          return ret;
 334    }
 335    return ret;
 336 }
 337
 338 /**
 339  * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
 340  *
 341  * @details
 342  *
 343  *     Function : fillUlSchedPucchDedicatedCfg
 344  *
 345  *     Function to fill Pucch Dedicated Cfg for UL Sched Info
 346  *
 347  *  @param[in]  pucchFormat to be filled
 348  *  @param[in]  SchPucchFormatCfg pointer, SchPucchCfg pointer
 349  *  @return  void
 350  **/
 351
 352 uint8_t fillUlSchedPucchDedicatedCfg(uint16_t numSlots, SchPucchCfg *pucchDedCfg,\
 353    SlotIndInfo *slotInfo, SchPucchInfo *ulSchedPucch)
 354 {
 355    uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
 356    uint16_t srOffset = 0;
 357
 358    ret = ROK;
 359    if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
 360    {
 361       //Assuming one entry in the list
 362       for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
 363       {
 364          for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
 365          {
 366             if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
 367                pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
 368             {
 369                ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
 370                ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
 371                ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
 372                ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
 373                ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
 374                         &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
 375                if(ret == RFAILED)
 376                   return ret;
 377             }
 378          }
 379       }
 380    }
 381    if(pucchDedCfg->format1)
 382    {
 383       memset(&ulSchedPucch->cmnFormatCfg, 0, sizeof(SchPucchFormatCfg));
 384       ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
 385       if(ret == RFAILED)
 386          return ret;
 387    }
 388
 389    /* setting SR and UCI flag */
 390    if(pucchDedCfg->schedReq)
 391    {
 392       for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
 393       {
 394          srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
 395          srOffset      = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
 396          break;
 397       }
 398       if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
 399       {
 400          ulSchedPucch->srFlag  = true;
 401          ulSchedPucch->uciFlag = true;
 402       }
 403    }
 404    return ret;
 405 }
 406
 407 /**
 408  * @brief Function to fill Pucch Resource Info
 409  *
 410  * @details
 411  *
 412  *     Function : fillPucchResourceInfo
 413  *
 414  *     Function to fill Pucch Resource Info
 415  *
 416  *  @param[in]  SchPucchInfo *schPucchInfo, Inst inst
 417  *  @return  ROK/RFAILED
 418  **/
 419
 420 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
 421 {
 422    uint8_t ret = ROK, ueIdx = 0, pucchIdx = 0;
 423    SchCellCb  *cell = schCb[inst].cells[inst];
 424    SchPucchCfgCmn *pucchCfg = NULLP;
 425    SchBwpParams *ulBwp = NULLP;
 426
 427    GET_UE_IDX(schPucchInfo->rnti, ueIdx);
 428    if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
 429    {
 430       /* fill pucch dedicated cfg */
 431       ret = fillUlSchedPucchDedicatedCfg(cell->numSlots,\
 432        &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg, &cell->slotInfo, schPucchInfo);
 433       if(ret == RFAILED)
 434       {
 435          memset(schPucchInfo, 0, sizeof(SchPucchInfo));
 436          DU_LOG("\nERROR  --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
 437          return ret;
 438       }
 439    }
 440    else
 441    {
 442       /* fill pucch common cfg */
 443       /* derive pucchResourceSet from schCellCfg */
 444       pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
 445       pucchIdx = pucchCfg->pucchResourceCommon;
 446       ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
 447       schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
 448       schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
 449       schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
 450       schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
 451       schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
 452
 453       /* set SR and UCI flag to false */
 454       schPucchInfo->srFlag  = true;
 455       schPucchInfo->uciFlag = true;
 456    }
 457    /* set HARQ flag to true */
 458    schPucchInfo->harqFlag = true;
 459    schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
 460
 461    return ROK;
 462 }
 463
 464 /**
 465  * @brief resource allocation for UL
 466  *
 467  * @details
 468  *
 469  *     Function : schUlResAlloc
 470  *
 471  *     This function handles UL Resource allocation
 472  *
 473  *  @param[in]  SchCellCb *cell, cellCb
 474  *  @return  void
 475  **/
 476 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
 477 {
 478    int ret = ROK;
 479    UlSchedInfo ulSchedInfo;
 480    SchUlSlotInfo  *schUlSlotInfo = NULLP;
 481    SlotIndInfo ulTimingInfo;
 482    memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
 483
 484    /* add PHY delta */
 485    ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA+SCHED_DELTA);
 486
 487    ulSchedInfo.cellId = cell->cellId;
 488    ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
 489    ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
 490    ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
 491
 492    /* Schedule resources for PRACH */
 493    schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
 494
 495    schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
 496    if(schUlSlotInfo->schPuschInfo)
 497    {
 498       ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
 499       ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
 500       memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
 501             sizeof(SchPuschInfo));
 502       SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
 503       schUlSlotInfo->schPuschInfo = NULL;
 504    }
 505
 506    if(schUlSlotInfo->pucchPres)
 507    {
 508       ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
 509       fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
 510       memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
 511             sizeof(SchPucchInfo));
 512       memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 513    }
 514
 515    //send msg to MAC
 516    ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
 517    if(ret != ROK)
 518    {
 519       DU_LOG("\nERROR  -->  SCH : Sending UL Sch info from SCH to MAC failed");
 520    }
 521
 522    schInitUlSlot(schUlSlotInfo);
 523    return ret;
 524 }
 525
 526 /*******************************************************************
 527  *
 528  * @brief Fills pdcch and pdsch info for msg4
 529  *
 530  * @details
 531  *
 532  *    Function : schDlRsrcAllocMsg4
 533  *
 534  *    Functionality:
 535  *       Fills pdcch and pdsch info for msg4
 536  *
 537  * @params[in]
 538  * @return ROK     - success
 539  *         RFAILED - failure
 540  *
 541  * ****************************************************************/
 542 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
 543 {
 544    uint8_t coreset0Idx = 0;
 545    uint8_t numRbs = 0;
 546    uint8_t firstSymbol = 0;
 547    uint8_t numSymbols = 0;
 548    uint8_t offset = 0;
 549    uint8_t offsetPointA;
 550    uint8_t FreqDomainResource[6] = {0};
 551    uint16_t tbSize = 0;
 552    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 553    uint8_t mcs = 4;  /* MCS fixed to 4 */
 554    SchBwpDlCfg *initialBwp;
 555
 556    PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
 557    PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
 558    BwpCfg *bwp = &msg4Alloc->bwp;
 559
 560    initialBwp   = &cell->cellCfg.schInitialDlBwp;
 561    offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
 562    coreset0Idx  = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
 563
 564    /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
 565    numRbs        = coresetIdxTable[coreset0Idx][1];
 566    numSymbols    = coresetIdxTable[coreset0Idx][2];
 567    offset        = coresetIdxTable[coreset0Idx][3];
 568
 569    /* calculate time domain parameters */
 570    uint16_t mask = 0x2000;
 571    for(firstSymbol=0; firstSymbol<14;firstSymbol++)
 572    {
 573       if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
 574          break;
 575       else
 576          mask = mask>>1;
 577    }
 578
 579    /* calculate the PRBs */
 580    freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
 581
 582    /* fill BWP */
 583    bwp->freqAlloc.numPrb   = initialBwp->bwp.freqAlloc.numPrb;
 584    bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
 585    bwp->subcarrierSpacing  = initialBwp->bwp.scs;
 586    bwp->cyclicPrefix       = initialBwp->bwp.cyclicPrefix;
 587
 588    /* fill the PDCCH PDU */
 589    pdcch->coresetCfg.startSymbolIndex = firstSymbol;
 590    pdcch->coresetCfg.durationSymbols = numSymbols;
 591    memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
 592    pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
 593    pdcch->coresetCfg.regBundleSize = 6;    /* spec-38.211 sec 7.3.2.2 */
 594    pdcch->coresetCfg.interleaverSize = 2;  /* spec-38.211 sec 7.3.2.2 */
 595    pdcch->coresetCfg.coreSetType = 0;
 596    pdcch->coresetCfg.coreSetSize = numRbs;
 597    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
 598    pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
 599    pdcch->numDlDci = 1;
 600    pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
 601    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
 602    pdcch->dci.scramblingRnti = 0;
 603    pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
 604    pdcch->dci.aggregLevel = 4;
 605    pdcch->dci.beamPdcchInfo.numPrgs = 1;
 606    pdcch->dci.beamPdcchInfo.prgSize = 1;
 607    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
 608    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
 609    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
 610    pdcch->dci.txPdcchPower.powerValue = 0;
 611    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
 612
 613    /* fill the PDSCH PDU */
 614    uint8_t cwCount = 0;
 615    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
 616    pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
 617    pdsch->pduIndex = 0;
 618    pdsch->numCodewords = 1;
 619    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
 620    {
 621       pdsch->codeword[cwCount].targetCodeRate = 308;
 622       pdsch->codeword[cwCount].qamModOrder = 2;
 623       pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
 624       pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
 625       pdsch->codeword[cwCount].rvIndex = 0;
 626       /* 38.214: Table 5.1.3.2-1,  divided by 8 to get the value in bytes */
 627       /* TODO : Calculate tbSize based of DL CCCH msg size */
 628       tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
 629       pdsch->codeword[cwCount].tbSize = tbSize;
 630    }
 631    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
 632    pdsch->numLayers = 1;
 633    pdsch->transmissionScheme = 0;
 634    pdsch->refPoint = 0;
 635    pdsch->dmrs.dlDmrsSymbPos = 2;
 636    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
 637    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
 638    pdsch->dmrs.scid = 0;
 639    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
 640    pdsch->dmrs.dmrsPorts = 0;
 641    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
 642    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
 643    pdsch->dmrs.dmrsAddPos       = DMRS_ADDITIONAL_POS;
 644    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
 645    /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
 646    pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
 647    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
 648    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
 649    pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
 650    pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
 651    pdsch->beamPdschInfo.numPrgs = 1;
 652    pdsch->beamPdschInfo.prgSize = 1;
 653    pdsch->beamPdschInfo.digBfInterfaces = 0;
 654    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
 655    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
 656    pdsch->txPdschPower.powerControlOffset = 0;
 657    pdsch->txPdschPower.powerControlOffsetSS = 0;
 658
 659    pdcch->dci.pdschCfg = pdsch;
 660
 661    return ROK;
 662 }
 663
 664 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot)
 665 {
 666    uint8_t k1 = SCH_DEFAULT_K1, ueIdx = 0, dlToUlAckIdx;
 667    uint16_t pucchSlot = 0;
 668    SchUlSlotInfo  *schUlSlotInfo = NULLP;
 669    SchPucchCfg    *schPucchCfg = NULLP;
 670
 671    GET_UE_IDX(crnti, ueIdx);
 672    if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
 673    {
 674       schPucchCfg = &(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg);
 675      if(schPucchCfg->dlDataToUlAck)
 676      {
 677         for(dlToUlAckIdx = 0; dlToUlAckIdx < schPucchCfg->dlDataToUlAck->dlDataToUlAckListCount; dlToUlAckIdx++)
 678         {
 679            //For now considering only the first value in the list
 680            k1 = schPucchCfg->dlDataToUlAck->dlDataToUlAckList[dlToUlAckIdx];
 681            break;
 682         }
 683      }
 684    }
 685
 686    pucchSlot = (slot + k1)  % cell->numSlots;
 687    schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
 688    memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
 689
 690    schUlSlotInfo->pucchPres = true;
 691    schUlSlotInfo->schPucchInfo.rnti = crnti;
 692
 693    return ROK;
 694 }
 695
 696 /*******************************************************************
 697  *
 698  * @brief Fills pdcch and pdsch info for dedicated DL msg
 699  *
 700  * @details
 701  *
 702  *    Function : schDlRsrcAllocDlMsg
 703  *
 704  *    Functionality:
 705  *       Fills pdcch and pdsch info for dl msg
 706  *
 707  * @params[in]
 708  * @return ROK     - success
 709  *         RFAILED - failure
 710  *
 711  * ****************************************************************/
 712 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
 713       uint16_t accumalatedSize, uint16_t slot)
 714 {
 715    uint8_t ueIdx;
 716    uint16_t tbSize = 0;
 717    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
 718    PdcchCfg *pdcch = NULLP;
 719    PdschCfg *pdsch = NULLP;
 720    BwpCfg *bwp = NULLP;
 721    SchUeCb ueCb;
 722    SchControlRsrcSet coreset1;
 723    SchPdschConfig pdschCfg;
 724
 725    pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
 726    pdsch = &dlMsgAlloc->dlMsgPdschCfg;
 727    bwp = &dlMsgAlloc->bwp;
 728
 729    GET_UE_IDX(crnti, ueIdx);
 730    ueCb  = cell->ueCb[ueIdx-1];
 731    coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
 732    pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
 733
 734    /* fill BWP */
 735    bwp->freqAlloc.numPrb = MAX_NUM_RB;
 736    bwp->freqAlloc.startPrb = 0;
 737    bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
 738    bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
 739
 740    /* fill the PDCCH PDU */
 741    //Considering coreset1 also starts from same symbol as coreset0
 742    pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
 743    pdcch->coresetCfg.durationSymbols = coreset1.duration;
 744    memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
 745    pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
 746    pdcch->coresetCfg.regBundleSize = 6;   /* must be 6 for non-interleaved */
 747    pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
 748    pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
 749    //Considering number of RBs in coreset1 is same as coreset0
 750    pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
 751    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
 752    pdcch->coresetCfg.precoderGranularity =  coreset1.precoderGranularity;
 753    pdcch->numDlDci = 1;
 754    pdcch->dci.rnti = ueCb.crnti;
 755    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
 756    pdcch->dci.scramblingRnti = 0;
 757    pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
 758    pdcch->dci.aggregLevel = 4;
 759    pdcch->dci.beamPdcchInfo.numPrgs = 1;
 760    pdcch->dci.beamPdcchInfo.prgSize = 1;
 761    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
 762    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
 763    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
 764    pdcch->dci.txPdcchPower.powerValue = 0;
 765    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
 766
 767    /* fill the PDSCH PDU */
 768    uint8_t cwCount = 0;
 769    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
 770    pdsch->rnti = ueCb.crnti;
 771    pdsch->pduIndex = 0;
 772    pdsch->numCodewords = 1;
 773    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
 774    {
 775       pdsch->codeword[cwCount].targetCodeRate = 308;
 776       pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
 777       pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
 778       pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
 779       pdsch->codeword[cwCount].rvIndex = 0;
 780       tbSize = schCalcTbSize(accumalatedSize);
 781       pdsch->codeword[cwCount].tbSize = tbSize;
 782    }
 783    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
 784    pdsch->numLayers = 1;
 785    pdsch->transmissionScheme = 0;
 786    pdsch->refPoint = 0;
 787    pdsch->dmrs.dlDmrsSymbPos = 2;
 788    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
 789    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
 790    pdsch->dmrs.scid = 0;
 791    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
 792    pdsch->dmrs.dmrsPorts = 0;
 793    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
 794    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
 795    pdsch->dmrs.dmrsAddPos       = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
 796    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
 797    pdsch->pdschFreqAlloc.freqAlloc.startPrb = 1;
 798    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, numPdschSymbols);
 799    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
 800    pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
 801    pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
 802    pdsch->beamPdschInfo.numPrgs = 1;
 803    pdsch->beamPdschInfo.prgSize = 1;
 804    pdsch->beamPdschInfo.digBfInterfaces = 0;
 805    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
 806    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
 807    pdsch->txPdschPower.powerControlOffset = 0;
 808    pdsch->txPdschPower.powerControlOffsetSS = 0;
 809
 810    pdcch->dci.pdschCfg = pdsch;
 811    return ROK;
 812 }
 813
 814 /**********************************************************************
 815   End of file
 816  **********************************************************************/
 817