1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
34 #include "common_def.h"
41 #include "du_app_mac_inf.h"
42 #include "mac_sch_interface.h"
44 #include "sch_utils.h"
46 SchCb schCb[SCH_MAX_INST];
47 uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
48 uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
49 uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
59 * @brief common resource allocation for SSB
63 * Function : schBroadcastAlloc
65 * This function handles common scheduling for DL
67 * @param[in] SchCellCb *cell, cell cb
68 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
75 uint8_t ssbStartPrb, ssbStartSymb, idx;
76 SchDlSlotInfo *schDlSlotInfo;
79 schDlSlotInfo = cell->schDlSlotInfo[slot];
81 if(dlBrdcstAlloc->ssbTrans)
83 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; //+Kssb
84 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
85 supporting only 1 ssb beam */
87 /* Assign interface structure */
88 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
91 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
92 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
93 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
94 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
95 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
96 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
99 schDlSlotInfo->ssbPres = true;
100 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
101 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
103 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
107 /* SIB1 allocation */
108 if(dlBrdcstAlloc->sib1Trans)
111 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
112 uint8_t mcs = 4; /* MCS fixed to 4 */
113 uint8_t numSib1Prb = 0;
114 schDlSlotInfo->sib1Pres = true;
116 tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
117 numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
118 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
120 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
122 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
123 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
124 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
125 dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
130 /*******************************************************************
132 * @brief Handles sending UL scheduler info to MAC
136 * Function : sendUlSchInfoToMac
139 * Sends UL Sch info to MAC from SCH
142 * @return ROK - success
145 * ****************************************************************/
146 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
150 memset(&pst, 0, sizeof(Pst));
151 FILL_PST_SCH_TO_MAC(pst, inst);
152 pst.event = EVENT_UL_SCH_INFO;
154 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
157 * @brief resource allocation for PRACH
161 * Function : schPrachResAlloc
163 * This function handles PRACH allocation
165 * @param[in] SchCellCb *cell, cell cb
166 * @param[in] UlSchedInfo *ulSchedInfo, UL scheduling info
169 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
172 uint8_t numPrachRb = 0;
174 uint8_t freqStart = 0;
175 uint8_t prachCfgIdx = 0;
176 uint8_t prachFormat = 0;
179 uint16_t prachSubframe = 0;
180 uint8_t prachStartSymbol = 0;
181 uint8_t prachOcas = 0;
182 uint8_t dataType = 0;
184 uint8_t subFrame = 0;
185 SchUlSlotInfo *schUlSlotInfo = NULLP;
187 puschScs = cell->cellCfg.schInitialUlBwp.bwp.scs;
188 schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
189 prachCfgIdx = cell->cellCfg.schRachCfg.prachCfgIdx;
191 /* derive the prachCfgIdx table paramters */
192 x = prachCfgIdxTable[prachCfgIdx][1];
193 y = prachCfgIdxTable[prachCfgIdx][2];
194 prachSubframe = prachCfgIdxTable[prachCfgIdx][3];
196 if((prachOccasionTimingInfo.sfn%x) == y)
199 subFrame = prachOccasionTimingInfo.slot/2;
201 subFrame = prachOccasionTimingInfo.slot;
203 /* check for subFrame number */
204 if ((1 << subFrame) & prachSubframe)
206 /* prach ocassion present in this subframe */
208 if(UL_SLOT != schGetSlotSymbFrmt(prachOccasionTimingInfo.slot, cell->slotFrmtBitMap))
210 DU_LOG("\nERROR --> SCH : PrachCfgIdx %d doesn't support UL slot", prachCfgIdx);
215 prachFormat = prachCfgIdxTable[prachCfgIdx][0];
216 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
217 prachOcas = prachCfgIdxTable[prachCfgIdx][6];
219 /* freq domain resource determination for RACH*/
220 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
221 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
222 * where M is given by msg1Fdm */
223 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
224 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
226 if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
228 if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
230 if(numRbForPrachTable[idx][2] == puschScs)
237 numPrachRb = numRbForPrachTable[idx][3];
238 dataType |= SCH_DATATYPE_PRACH;
239 /* Considering first slot in the frame for PRACH */
241 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
243 ulSchedInfo->dataType = dataType;
245 ulSchedInfo->prachSchInfo.numPrachOcas = prachOcas;
246 ulSchedInfo->prachSchInfo.prachFormat = prachFormat;
247 ulSchedInfo->prachSchInfo.numRa = numRa;
248 ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
249 DU_LOG("\nINFO --> SCH : RACH occassion set for slot %d", prachOccasionTimingInfo.slot);
256 * @brief Function to fill Pucch Format 0
260 * Function : fillPucchFormat0
262 * Function to fill Pucch format 0
264 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
268 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
270 if(resrcInfo->SchPucchFormat.format0)
272 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
273 ulSchedPucch->pucchFormat = PUCCH_FORMAT_0;
274 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format0->initialCyclicShift;
275 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
276 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
281 * @brief Function to fill Pucch Format 1
285 * Function : fillPucchFormat1
287 * Function to fill Pucch format 1
289 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
293 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
295 if(resrcInfo->SchPucchFormat.format1)
297 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
298 ulSchedPucch->pucchFormat = PUCCH_FORMAT_1;
299 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format1->initialCyclicShift;
300 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
301 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
302 ulSchedPucch->timeDomOCC = resrcInfo->SchPucchFormat.format1->timeDomOCC;
307 * @brief Function to fill Pucch format for UL Sched Info
311 * Function : fillUlSchedPucchFormat
313 * Function to fill Pucch format for UL Sched Info
315 * @param[in] pucchFormat , SchPucchInfo pointer,
316 * @param[in] SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
320 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
321 SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
330 fillPucchFormat0(ulSchedPucch, resrcInfo);
337 fillPucchFormat1(ulSchedPucch, resrcInfo);
341 memcpy(&ulSchedPucch->cmnFormatCfg, formatCfg, sizeof(SchPucchFormatCfg));
344 }/* To Add support for more Pucch Format */
347 DU_LOG("\nERROR --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
355 * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
359 * Function : fillUlSchedPucchDedicatedCfg
361 * Function to fill Pucch Dedicated Cfg for UL Sched Info
363 * @param[in] pucchFormat to be filled
364 * @param[in] SchPucchFormatCfg pointer, SchPucchCfg pointer
368 uint8_t fillUlSchedPucchDedicatedCfg(uint16_t numSlots, SchPucchCfg *pucchDedCfg,\
369 SlotIndInfo *slotInfo, SchPucchInfo *ulSchedPucch)
371 uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
372 uint16_t srOffset = 0;
375 if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
377 //Assuming one entry in the list
378 for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
380 for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
382 if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
383 pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
385 ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
386 ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
387 ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
388 ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
389 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
390 &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
397 if(pucchDedCfg->format1)
399 memset(&ulSchedPucch->cmnFormatCfg, 0, sizeof(SchPucchFormatCfg));
400 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
405 /* setting SR and UCI flag */
406 if(pucchDedCfg->schedReq)
408 for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
410 srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
411 srOffset = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
414 if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
416 ulSchedPucch->srFlag = true;
417 ulSchedPucch->uciFlag = true;
424 * @brief Function to fill Pucch Resource Info
428 * Function : fillPucchResourceInfo
430 * Function to fill Pucch Resource Info
432 * @param[in] SchPucchInfo *schPucchInfo, Inst inst
433 * @return ROK/RFAILED
436 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
438 uint8_t ret = ROK, ueIdx = 0, pucchIdx = 0;
439 SchCellCb *cell = schCb[inst].cells[inst];
440 SchPucchCfgCmn *pucchCfg = NULLP;
441 SchBwpParams *ulBwp = NULLP;
443 GET_UE_IDX(schPucchInfo->rnti, ueIdx);
444 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
446 /* fill pucch dedicated cfg */
447 ret = fillUlSchedPucchDedicatedCfg(cell->numSlots,\
448 &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg, &cell->slotInfo, schPucchInfo);
451 memset(schPucchInfo, 0, sizeof(SchPucchInfo));
452 DU_LOG("\nERROR --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
458 /* fill pucch common cfg */
459 /* derive pucchResourceSet from schCellCfg */
460 pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
461 pucchIdx = pucchCfg->pucchResourceCommon;
462 ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
463 schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
464 schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
465 schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
466 schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
467 schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
469 /* set SR and UCI flag to false */
470 schPucchInfo->srFlag = true;
471 schPucchInfo->uciFlag = true;
473 /* set HARQ flag to true */
474 schPucchInfo->harqFlag = true;
475 schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
481 * @brief resource allocation for UL
485 * Function : schUlResAlloc
487 * This function handles UL Resource allocation
489 * @param[in] SchCellCb *cell, cellCb
492 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
495 UlSchedInfo ulSchedInfo;
496 SchUlSlotInfo *schUlSlotInfo = NULLP;
497 SlotIndInfo ulTimingInfo;
498 memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
501 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA_UL+SCHED_DELTA);
503 ulSchedInfo.cellId = cell->cellId;
504 ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
505 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
506 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
508 /* Schedule resources for PRACH */
509 if(cell->firstSib1Transmitted)
510 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
512 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
513 if(schUlSlotInfo->schPuschInfo)
515 ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
516 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
517 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
518 sizeof(SchPuschInfo));
519 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
520 schUlSlotInfo->schPuschInfo = NULL;
523 if(schUlSlotInfo->pucchPres)
525 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
526 fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
527 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
528 sizeof(SchPucchInfo));
529 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
533 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
536 DU_LOG("\nERROR --> SCH : Sending UL Sch info from SCH to MAC failed");
539 schInitUlSlot(schUlSlotInfo);
543 /*******************************************************************
545 * @brief Fills pdcch and pdsch info for msg4
549 * Function : schDlRsrcAllocMsg4
552 * Fills pdcch and pdsch info for msg4
555 * @return ROK - success
558 * ****************************************************************/
559 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
561 uint8_t coreset0Idx = 0;
563 uint8_t firstSymbol = 0;
564 uint8_t numSymbols = 0;
566 uint8_t offsetPointA;
567 uint8_t FreqDomainResource[6] = {0};
569 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
570 uint8_t mcs = 4; /* MCS fixed to 4 */
571 SchBwpDlCfg *initialBwp;
573 PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
574 PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
575 BwpCfg *bwp = &msg4Alloc->bwp;
577 initialBwp = &cell->cellCfg.schInitialDlBwp;
578 offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
579 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
581 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
582 numRbs = coresetIdxTable[coreset0Idx][1];
583 numSymbols = coresetIdxTable[coreset0Idx][2];
584 offset = coresetIdxTable[coreset0Idx][3];
586 /* calculate time domain parameters */
587 uint16_t mask = 0x2000;
588 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
590 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
596 /* calculate the PRBs */
597 freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
600 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
601 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
602 bwp->subcarrierSpacing = initialBwp->bwp.scs;
603 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
605 /* fill the PDCCH PDU */
606 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
607 pdcch->coresetCfg.durationSymbols = numSymbols;
608 memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
609 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
610 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
611 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
612 pdcch->coresetCfg.coreSetType = 0;
613 pdcch->coresetCfg.coreSetSize = numRbs;
614 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
615 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
617 pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
618 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
619 pdcch->dci.scramblingRnti = 0;
620 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
621 pdcch->dci.aggregLevel = 4;
622 pdcch->dci.beamPdcchInfo.numPrgs = 1;
623 pdcch->dci.beamPdcchInfo.prgSize = 1;
624 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
625 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
626 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
627 pdcch->dci.txPdcchPower.powerValue = 0;
628 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
630 /* fill the PDSCH PDU */
632 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
633 pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
635 pdsch->numCodewords = 1;
636 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
638 pdsch->codeword[cwCount].targetCodeRate = 308;
639 pdsch->codeword[cwCount].qamModOrder = 2;
640 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
641 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
642 pdsch->codeword[cwCount].rvIndex = 0;
643 /* 38.214: Table 5.1.3.2-1, divided by 8 to get the value in bytes */
644 /* TODO : Calculate tbSize based of DL CCCH msg size */
645 tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
646 pdsch->codeword[cwCount].tbSize = tbSize;
648 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
649 pdsch->numLayers = 1;
650 pdsch->transmissionScheme = 0;
652 pdsch->dmrs.dlDmrsSymbPos = 2;
653 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
654 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
655 pdsch->dmrs.scid = 0;
656 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
657 pdsch->dmrs.dmrsPorts = 0;
658 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
659 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
660 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
661 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
662 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
663 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
664 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
665 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
666 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
667 pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
668 pdsch->beamPdschInfo.numPrgs = 1;
669 pdsch->beamPdschInfo.prgSize = 1;
670 pdsch->beamPdschInfo.digBfInterfaces = 0;
671 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
672 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
673 pdsch->txPdschPower.powerControlOffset = 0;
674 pdsch->txPdschPower.powerControlOffsetSS = 0;
676 pdcch->dci.pdschCfg = pdsch;
681 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot)
683 uint8_t k1 = SCH_DEFAULT_K1, ueIdx = 0, dlToUlAckIdx;
684 uint16_t pucchSlot = 0;
685 SchUlSlotInfo *schUlSlotInfo = NULLP;
686 SchPucchCfg *schPucchCfg = NULLP;
688 GET_UE_IDX(crnti, ueIdx);
689 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
691 schPucchCfg = &(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg);
692 if(schPucchCfg->dlDataToUlAck)
694 for(dlToUlAckIdx = 0; dlToUlAckIdx < schPucchCfg->dlDataToUlAck->dlDataToUlAckListCount; dlToUlAckIdx++)
696 //For now considering only the first value in the list
697 k1 = schPucchCfg->dlDataToUlAck->dlDataToUlAckList[dlToUlAckIdx];
703 pucchSlot = (slot + k1) % cell->numSlots;
704 schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
705 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
707 schUlSlotInfo->pucchPres = true;
708 schUlSlotInfo->schPucchInfo.rnti = crnti;
713 /*******************************************************************
715 * @brief Fills pdcch and pdsch info for dedicated DL msg
719 * Function : schDlRsrcAllocDlMsg
722 * Fills pdcch and pdsch info for dl msg
725 * @return ROK - success
728 * ****************************************************************/
729 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
730 uint32_t *accumalatedSize, uint16_t slot)
734 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
735 PdcchCfg *pdcch = NULLP;
736 PdschCfg *pdsch = NULLP;
739 SchControlRsrcSet coreset1;
740 SchPdschConfig pdschCfg;
742 pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
743 pdsch = &dlMsgAlloc->dlMsgPdschCfg;
744 bwp = &dlMsgAlloc->bwp;
746 GET_UE_IDX(crnti, ueIdx);
747 ueCb = cell->ueCb[ueIdx-1];
748 coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
749 pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
752 bwp->freqAlloc.numPrb = MAX_NUM_RB;
753 bwp->freqAlloc.startPrb = 0;
754 bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
755 bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
757 /* fill the PDCCH PDU */
758 //Considering coreset1 also starts from same symbol as coreset0
759 pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
760 pdcch->coresetCfg.durationSymbols = coreset1.duration;
761 memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
762 pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
763 pdcch->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
764 pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
765 pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
766 //Considering number of RBs in coreset1 is same as coreset0
767 pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
768 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
769 pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
771 pdcch->dci.rnti = ueCb.crnti;
772 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
773 pdcch->dci.scramblingRnti = 0;
774 pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
775 pdcch->dci.aggregLevel = 4;
776 pdcch->dci.beamPdcchInfo.numPrgs = 1;
777 pdcch->dci.beamPdcchInfo.prgSize = 1;
778 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
779 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
780 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
781 pdcch->dci.txPdcchPower.powerValue = 0;
782 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
784 /* fill the PDSCH PDU */
786 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
787 pdsch->rnti = ueCb.crnti;
789 pdsch->numCodewords = 1;
790 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
792 pdsch->codeword[cwCount].targetCodeRate = 308;
793 pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
794 pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
795 pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
796 pdsch->codeword[cwCount].rvIndex = 0;
797 tbSize = schCalcTbSize(*accumalatedSize);
798 if(tbSize < *accumalatedSize)
799 *accumalatedSize = tbSize;
800 pdsch->codeword[cwCount].tbSize = tbSize;
802 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
803 pdsch->numLayers = 1;
804 pdsch->transmissionScheme = 0;
806 pdsch->dmrs.dlDmrsSymbPos = 2;
807 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
808 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
809 pdsch->dmrs.scid = 0;
810 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
811 pdsch->dmrs.dmrsPorts = 0;
812 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
813 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
814 pdsch->dmrs.dmrsAddPos = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
815 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
816 pdsch->pdschFreqAlloc.freqAlloc.startPrb = 1;
817 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, numPdschSymbols);
818 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
819 pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
820 pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
821 pdsch->beamPdschInfo.numPrgs = 1;
822 pdsch->beamPdschInfo.prgSize = 1;
823 pdsch->beamPdschInfo.digBfInterfaces = 0;
824 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
825 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
826 pdsch->txPdschPower.powerControlOffset = 0;
827 pdsch->txPdschPower.powerControlOffsetSS = 0;
829 pdcch->dci.pdschCfg = pdsch;
833 /**********************************************************************
835 **********************************************************************/