1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
35 #include "envopt.h" /* environment options */
36 #include "envdep.h" /* environment dependent */
37 #include "envind.h" /* environment independent */
38 #include "gen.h" /* general layer */
39 #include "ssi.h" /* system service interface */
40 #include "cm_tkns.h" /* Common Token Defines */
41 #include "cm_llist.h" /* Common Link List Defines */
42 #include "cm_hash.h" /* Common Hash List Defines */
43 #include "cm_mblk.h" /* common memory link list library */
44 #include "cm_lte.h" /* Common LTE Defines */
48 #include "gen.x" /* general layer typedefs */
49 #include "ssi.x" /* system services typedefs */
50 #include "cm5.x" /* system services */
51 #include "cm_tkns.x" /* Common Token Definitions */
52 #include "cm_llist.x" /* Common Link List Definitions */
53 #include "cm_lib.x" /* Common Library Definitions */
54 #include "cm_hash.x" /* Common Hash List Definitions */
55 #include "cm_mblk.x" /* common memory link list library */
56 #include "cm_lte.x" /* Common LTE Defines */
60 #include "du_app_mac_inf.h"
61 #include "mac_sch_interface.h"
63 #include "sch_utils.h"
64 #include "common_def.h"
66 extern SchCb schCb[SCH_MAX_INST];
67 extern uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
68 extern uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
70 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
78 * @brief Time domain allocation for SSB
82 * Function : ssbDlTdAlloc
84 * This function handles common scheduling for DL
86 * @param[in] uint8_t scs, uint8_t *ssbStartSym
89 void ssbDlTdAlloc(uint8_t scs, uint8_t *ssbStartSymb)
92 /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
98 n = 2;/* n = 0, 1 for SCS = 15KHz */
99 for(uint8_t idx=0; idx<n; idx++)
101 /* start symbol determined using {2, 8} + 14n */
102 ssbStartSymb[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
103 ssbStartSymb[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
108 DU_LOG("\nSCS %d is currently not supported", scs);
113 * @brief common resource allocation for SSB
117 * Function : schBroadcastAlloc
119 * This function handles common scheduling for DL
121 * @param[in] SchCellCb *cell, cell cb
122 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
125 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
129 uint8_t scs, ssbStartPrb, ssbStartSymb, idx;
130 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM];
131 SchDlSlotInfo *schDlSlotInfo;
134 schDlSlotInfo = cell->schDlSlotInfo[slot];
135 if(dlBrdcstAlloc->ssbTrans)
137 scs = cell->cellCfg.ssbSchCfg.scsCommon;
138 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
140 memset(ssbStartSymbArr, 0, SCH_MAX_SSB_BEAM);
141 ssbDlTdAlloc(scs, ssbStartSymbArr);
142 ssbStartSymb = ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are supporting only 1 ssb beam */
143 /* Assign interface structure */
144 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
146 ssbInfo.ssbIdx = idx;
147 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
148 ssbInfo.fdAlloc.numPrb = SCH_SSB_PRB_DURATION;
149 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
150 ssbInfo.tdAlloc.numSymb = SCH_SSB_SYMB_DURATION;
151 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
152 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
155 schDlSlotInfo->ssbPres = true;
156 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
157 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_SYMB_DURATION; idx++)
159 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_PRB_DURATION + 1; /* +1 for kSsb */
163 /* SIB1 allocation */
164 if(dlBrdcstAlloc->sib1Trans)
166 schDlSlotInfo->sib1Pres = true;
167 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
169 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_PRB_DURATION + 1 + 10; /* 10 PRBs for sib1 */
171 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
172 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
173 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
178 /*******************************************************************
180 * @brief Handles sending UL scheduler info to MAC
184 * Function : sendUlSchInfoToMac
187 * Sends UL Sch info to MAC from SCH
190 * @return ROK - success
193 * ****************************************************************/
194 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
198 memset(&pst, 0, sizeof(Pst));
199 SCH_FILL_RSP_PST(pst, inst);
200 pst.event = EVENT_UL_SCH_INFO;
202 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
205 * @brief resource allocation for PRACH
209 * Function : schPrachResAlloc
211 * This function handles PRACH allocation
213 * @param[in] SchCellCb *cell, cell cb
214 * @param[in] UlSchedInfo *ulSchedInfo, UL scheduling info
217 int schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
219 uint8_t numPrachRb = 0;
221 uint8_t freqStart = 0;
222 uint8_t prachCfgIdx = 0;
223 uint8_t prachFormat = 0;
226 uint16_t prachSubframe = 0;
227 uint8_t prachStartSymbol = 0;
228 uint8_t prachOcas = 0;
229 uint8_t dataType = 0;
231 SchUlSlotInfo *schUlSlotInfo = NULLP;
233 schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
234 prachCfgIdx = cell->cellCfg.schRachCfg.prachCfgIdx;
236 /* derive the prachCfgIdx table paramters */
237 x = prachCfgIdxTable[prachCfgIdx][1];
238 y = prachCfgIdxTable[prachCfgIdx][2];
239 prachSubframe = prachCfgIdxTable[prachCfgIdx][3];
241 if((prachOccasionTimingInfo.sfn%x) != y)
243 /* prach occasion does not lie in this SFN */
244 DU_LOG("\nPRACH ocassion doesn't lie in this SFN");
247 /* check for subFrame number */
248 if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
250 /* prach ocassion present in this subframe */
252 prachFormat = prachCfgIdxTable[prachCfgIdx][0];
253 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
254 prachOcas = prachCfgIdxTable[prachCfgIdx][6];
256 /* freq domain resource determination for RACH*/
257 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
258 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
259 * where M is given by msg1Fdm */
260 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
261 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
263 if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqIdx)
266 numPrachRb = numRbForPrachTable[idx][3];
267 dataType |= SCH_DATATYPE_PRACH;
268 /* Considering first slot in the frame for PRACH */
270 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
273 ulSchedInfo->dataType = dataType;
275 ulSchedInfo->prachSchInfo.numPrachOcas = prachOcas;
276 ulSchedInfo->prachSchInfo.prachFormat = prachFormat;
277 ulSchedInfo->prachSchInfo.numRa = numRa;
278 ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
284 * @brief resource allocation for UL
288 * Function : schUlResAlloc
290 * This function handles UL Resource allocation
292 * @param[in] SchCellCb *cell, cellCb
295 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
298 UlSchedInfo ulSchedInfo;
299 SchUlSlotInfo *schUlSlotInfo;
300 SlotIndInfo ulTimingInfo;
303 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA+SCHED_DELTA);
305 ulSchedInfo.cellId = cell->cellId;
306 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
307 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
309 /* Schedule resources for PRACH */
310 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
312 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
314 if(schUlSlotInfo->schPuschInfo)
316 ulSchedInfo.crnti = cell->raCb[0].tcrnti;
317 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
318 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
319 sizeof(SchPuschInfo));
320 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
321 schUlSlotInfo->schPuschInfo = NULL;
325 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
328 DU_LOG("\nSending UL Sch info from SCH to MAC failed");
334 /*******************************************************************
336 * @brief Fills pdcch and pdsch info for msg4
340 * Function : schDlRsrcAllocMsg4
343 * Fills pdcch and pdsch info for msg4
346 * @return ROK - success
349 * ****************************************************************/
350 uint8_t schDlRsrcAllocMsg4(Msg4Alloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
352 uint8_t coreset0Idx = 0;
354 uint8_t firstSymbol = 0;
355 uint8_t numSymbols = 0;
357 uint8_t offsetPointA;
358 uint8_t FreqDomainResource[6] = {0};
359 SchBwpDlCfg *initialBwp;
361 PdcchCfg *pdcch = &msg4Alloc->msg4PdcchCfg;
362 PdschCfg *pdsch = &msg4Alloc->msg4PdschCfg;
363 BwpCfg *bwp = &msg4Alloc->bwp;
365 initialBwp = &cell->cellCfg.schInitialDlBwp;
366 offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
367 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
369 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
370 numRbs = coresetIdxTable[coreset0Idx][1];
371 numSymbols = coresetIdxTable[coreset0Idx][2];
372 offset = coresetIdxTable[coreset0Idx][3];
374 /* calculate time domain parameters */
375 uint16_t mask = 0x2000;
376 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
378 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
384 /* calculate the PRBs */
385 calculatePRB( ((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
388 bwp->BWPSize = initialBwp->bwp.numPrb;
389 bwp->BWPStart = initialBwp->bwp.firstPrb;
390 bwp->subcarrierSpacing = initialBwp->bwp.scs;
391 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
393 /* fill the PDCCH PDU */
394 pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
395 pdcch->coreset0Cfg.durationSymbols = numSymbols;
396 memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
397 pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
398 pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
399 pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
400 pdcch->coreset0Cfg.coreSetType = 0;
401 pdcch->coreset0Cfg.coreSet0Size = numRbs;
402 pdcch->coreset0Cfg.shiftIndex = cell->cellCfg.phyCellId;
403 pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
405 pdcch->dci.rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
406 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
407 pdcch->dci.scramblingRnti = 0;
408 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
409 pdcch->dci.aggregLevel = 4;
410 pdcch->dci.beamPdcchInfo.numPrgs = 1;
411 pdcch->dci.beamPdcchInfo.prgSize = 1;
412 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
413 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
414 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
415 pdcch->dci.txPdcchPower.powerValue = 0;
416 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
418 /* fill the PDSCH PDU */
420 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
421 pdsch->rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
423 pdsch->numCodewords = 1;
424 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
426 pdsch->codeword[cwCount].targetCodeRate = 308;
427 pdsch->codeword[cwCount].qamModOrder = 2;
428 pdsch->codeword[cwCount].mcsIndex = 4; /* mcs configured to 4 */
429 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
430 pdsch->codeword[cwCount].rvIndex = 0;
431 /* 38.214: Table 5.1.3.2-1, divided by 8 to get the value in bytes */
432 /* TODO : Calculate tbSize based of DL CCCH msg size */
433 pdsch->codeword[cwCount].tbSize = 2664/8;
435 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
436 pdsch->numLayers = 1;
437 pdsch->transmissionScheme = 0;
439 pdsch->dmrs.dlDmrsSymbPos = 2;
440 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
441 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
442 pdsch->dmrs.scid = 0;
443 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
444 pdsch->dmrs.dmrsPorts = 0;
445 pdsch->freqAlloc.resourceAlloc = 1; /* RAT type-1 RIV format */
446 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
447 pdsch->freqAlloc.rbStart = offset + SCH_SSB_PRB_DURATION;
448 /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 *
449 * Ninfo = S . Nre . R . Qm . v *
450 * Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh *
451 * Nre = min(156,Nre') . nPrb */
452 /* TODO : Calculate rbSize based on tbSize calculated */
453 pdsch->freqAlloc.rbSize = 34;
454 pdsch->freqAlloc.vrbPrbMapping = 0; /* non-interleaved */
455 pdsch->timeAlloc.startSymbolIndex = 2; /* spec-38.214, Table 5.1.2.1-1 */
456 pdsch->timeAlloc.numSymbols = 12;
457 pdsch->beamPdschInfo.numPrgs = 1;
458 pdsch->beamPdschInfo.prgSize = 1;
459 pdsch->beamPdschInfo.digBfInterfaces = 0;
460 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
461 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
462 pdsch->txPdschPower.powerControlOffset = 0;
463 pdsch->txPdschPower.powerControlOffsetSS = 0;
465 pdcch->dci.pdschCfg = pdsch;
469 /**********************************************************************
471 **********************************************************************/