1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
34 #include "common_def.h"
41 #include "du_app_mac_inf.h"
42 #include "mac_sch_interface.h"
44 #include "sch_utils.h"
46 SchCb schCb[SCH_MAX_INST];
47 uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
48 uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
49 uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
59 * @brief common resource allocation for SSB
63 * Function : schBroadcastAlloc
65 * This function handles common scheduling for DL
67 * @param[in] SchCellCb *cell, cell cb
68 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
75 uint8_t ssbStartPrb, ssbStartSymb, idx;
76 SchDlSlotInfo *schDlSlotInfo;
79 schDlSlotInfo = cell->schDlSlotInfo[slot];
81 if(dlBrdcstAlloc->ssbTrans)
83 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; //+Kssb
84 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
85 supporting only 1 ssb beam */
87 /* Assign interface structure */
88 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
91 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
92 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
93 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
94 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
95 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
96 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
99 schDlSlotInfo->ssbPres = true;
100 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
101 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
103 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
107 /* SIB1 allocation */
108 if(dlBrdcstAlloc->sib1Trans)
111 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
112 uint8_t mcs = 4; /* MCS fixed to 4 */
113 uint8_t numSib1Prb = 0;
114 schDlSlotInfo->sib1Pres = true;
116 tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
117 numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
118 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
120 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
122 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
123 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
124 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
125 dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
130 /*******************************************************************
132 * @brief Handles sending UL scheduler info to MAC
136 * Function : sendUlSchInfoToMac
139 * Sends UL Sch info to MAC from SCH
142 * @return ROK - success
145 * ****************************************************************/
146 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
150 memset(&pst, 0, sizeof(Pst));
151 FILL_PST_SCH_TO_MAC(pst, inst);
152 pst.event = EVENT_UL_SCH_INFO;
154 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
157 * @brief resource allocation for PRACH
161 * Function : schPrachResAlloc
163 * This function handles PRACH allocation
165 * @param[in] SchCellCb *cell, cell cb
166 * @param[in] UlSchedInfo *ulSchedInfo, UL scheduling info
169 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
172 uint8_t numPrachRb = 0;
174 uint8_t freqStart = 0;
175 uint8_t prachCfgIdx = 0;
176 uint8_t prachFormat = 0;
179 uint16_t prachSubframe = 0;
180 uint8_t prachStartSymbol = 0;
181 uint8_t prachOcas = 0;
182 uint8_t dataType = 0;
184 SchUlSlotInfo *schUlSlotInfo = NULLP;
186 puschScs = cell->cellCfg.schInitialUlBwp.bwp.scs;
187 schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
188 prachCfgIdx = cell->cellCfg.schRachCfg.prachCfgIdx;
190 /* derive the prachCfgIdx table paramters */
191 x = prachCfgIdxTable[prachCfgIdx][1];
192 y = prachCfgIdxTable[prachCfgIdx][2];
193 prachSubframe = prachCfgIdxTable[prachCfgIdx][3];
195 if((prachOccasionTimingInfo.sfn%x) == y)
197 /* check for subFrame number */
198 if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
200 /* prach ocassion present in this subframe */
202 prachFormat = prachCfgIdxTable[prachCfgIdx][0];
203 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
204 prachOcas = prachCfgIdxTable[prachCfgIdx][6];
206 /* freq domain resource determination for RACH*/
207 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
208 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
209 * where M is given by msg1Fdm */
210 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
211 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
213 if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
215 if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
217 if(numRbForPrachTable[idx][2] == puschScs)
224 numPrachRb = numRbForPrachTable[idx][3];
225 dataType |= SCH_DATATYPE_PRACH;
226 /* Considering first slot in the frame for PRACH */
228 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
230 ulSchedInfo->dataType = dataType;
232 ulSchedInfo->prachSchInfo.numPrachOcas = prachOcas;
233 ulSchedInfo->prachSchInfo.prachFormat = prachFormat;
234 ulSchedInfo->prachSchInfo.numRa = numRa;
235 ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
241 * @brief Function to fill Pucch Format 0
245 * Function : fillPucchFormat0
247 * Function to fill Pucch format 0
249 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
253 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
255 if(resrcInfo->SchPucchFormat.format0)
257 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
258 ulSchedPucch->pucchFormat = PUCCH_FORMAT_0;
259 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format0->initialCyclicShift;
260 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
261 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
266 * @brief Function to fill Pucch Format 1
270 * Function : fillPucchFormat1
272 * Function to fill Pucch format 1
274 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
278 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
280 if(resrcInfo->SchPucchFormat.format1)
282 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
283 ulSchedPucch->pucchFormat = PUCCH_FORMAT_1;
284 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format1->initialCyclicShift;
285 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
286 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
287 ulSchedPucch->timeDomOCC = resrcInfo->SchPucchFormat.format1->timeDomOCC;
292 * @brief Function to fill Pucch format for UL Sched Info
296 * Function : fillUlSchedPucchFormat
298 * Function to fill Pucch format for UL Sched Info
300 * @param[in] pucchFormat , SchPucchInfo pointer,
301 * @param[in] SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
305 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
306 SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
315 fillPucchFormat0(ulSchedPucch, resrcInfo);
322 fillPucchFormat1(ulSchedPucch, resrcInfo);
326 memcpy(&ulSchedPucch->cmnFormatCfg, formatCfg, sizeof(SchPucchFormatCfg));
329 }/* To Add support for more Pucch Format */
332 DU_LOG("\nERROR --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
340 * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
344 * Function : fillUlSchedPucchDedicatedCfg
346 * Function to fill Pucch Dedicated Cfg for UL Sched Info
348 * @param[in] pucchFormat to be filled
349 * @param[in] SchPucchFormatCfg pointer, SchPucchCfg pointer
353 uint8_t fillUlSchedPucchDedicatedCfg(uint16_t numSlots, SchPucchCfg *pucchDedCfg,\
354 SlotIndInfo *slotInfo, SchPucchInfo *ulSchedPucch)
356 uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
357 uint16_t srOffset = 0;
360 if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
362 //Assuming one entry in the list
363 for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
365 for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
367 if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
368 pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
370 ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
371 ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
372 ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
373 ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
374 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
375 &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
382 if(pucchDedCfg->format1)
384 memset(&ulSchedPucch->cmnFormatCfg, 0, sizeof(SchPucchFormatCfg));
385 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
390 /* setting SR and UCI flag */
391 if(pucchDedCfg->schedReq)
393 for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
395 srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
396 srOffset = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
399 if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
401 ulSchedPucch->srFlag = true;
402 ulSchedPucch->uciFlag = true;
409 * @brief Function to fill Pucch Resource Info
413 * Function : fillPucchResourceInfo
415 * Function to fill Pucch Resource Info
417 * @param[in] SchPucchInfo *schPucchInfo, Inst inst
418 * @return ROK/RFAILED
421 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
423 uint8_t ret = ROK, ueIdx = 0, pucchIdx = 0;
424 SchCellCb *cell = schCb[inst].cells[inst];
425 SchPucchCfgCmn *pucchCfg = NULLP;
426 SchBwpParams *ulBwp = NULLP;
428 GET_UE_IDX(schPucchInfo->rnti, ueIdx);
429 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
431 /* fill pucch dedicated cfg */
432 ret = fillUlSchedPucchDedicatedCfg(cell->numSlots,\
433 &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg, &cell->slotInfo, schPucchInfo);
436 memset(schPucchInfo, 0, sizeof(SchPucchInfo));
437 DU_LOG("\nERROR --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
443 /* fill pucch common cfg */
444 /* derive pucchResourceSet from schCellCfg */
445 pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
446 pucchIdx = pucchCfg->pucchResourceCommon;
447 ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
448 schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
449 schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
450 schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
451 schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
452 schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
454 /* set SR and UCI flag to false */
455 schPucchInfo->srFlag = true;
456 schPucchInfo->uciFlag = true;
458 /* set HARQ flag to true */
459 schPucchInfo->harqFlag = true;
460 schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
466 * @brief resource allocation for UL
470 * Function : schUlResAlloc
472 * This function handles UL Resource allocation
474 * @param[in] SchCellCb *cell, cellCb
477 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
480 UlSchedInfo ulSchedInfo;
481 SchUlSlotInfo *schUlSlotInfo = NULLP;
482 SlotIndInfo ulTimingInfo;
483 memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
486 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA_UL+SCHED_DELTA);
488 ulSchedInfo.cellId = cell->cellId;
489 ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
490 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
491 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
493 /* Schedule resources for PRACH */
494 if(cell->firstSib1Transmitted)
495 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
497 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
498 if(schUlSlotInfo->schPuschInfo)
500 ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
501 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
502 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
503 sizeof(SchPuschInfo));
504 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
505 schUlSlotInfo->schPuschInfo = NULL;
508 if(schUlSlotInfo->pucchPres)
510 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
511 fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
512 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
513 sizeof(SchPucchInfo));
514 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
518 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
521 DU_LOG("\nERROR --> SCH : Sending UL Sch info from SCH to MAC failed");
524 schInitUlSlot(schUlSlotInfo);
528 /*******************************************************************
530 * @brief Fills pdcch and pdsch info for msg4
534 * Function : schDlRsrcAllocMsg4
537 * Fills pdcch and pdsch info for msg4
540 * @return ROK - success
543 * ****************************************************************/
544 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
546 uint8_t coreset0Idx = 0;
548 uint8_t firstSymbol = 0;
549 uint8_t numSymbols = 0;
551 uint8_t offsetPointA;
552 uint8_t FreqDomainResource[6] = {0};
554 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
555 uint8_t mcs = 4; /* MCS fixed to 4 */
556 SchBwpDlCfg *initialBwp;
558 PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
559 PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
560 BwpCfg *bwp = &msg4Alloc->bwp;
562 initialBwp = &cell->cellCfg.schInitialDlBwp;
563 offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
564 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
566 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
567 numRbs = coresetIdxTable[coreset0Idx][1];
568 numSymbols = coresetIdxTable[coreset0Idx][2];
569 offset = coresetIdxTable[coreset0Idx][3];
571 /* calculate time domain parameters */
572 uint16_t mask = 0x2000;
573 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
575 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
581 /* calculate the PRBs */
582 freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
585 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
586 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
587 bwp->subcarrierSpacing = initialBwp->bwp.scs;
588 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
590 /* fill the PDCCH PDU */
591 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
592 pdcch->coresetCfg.durationSymbols = numSymbols;
593 memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
594 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
595 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
596 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
597 pdcch->coresetCfg.coreSetType = 0;
598 pdcch->coresetCfg.coreSetSize = numRbs;
599 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
600 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
602 pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
603 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
604 pdcch->dci.scramblingRnti = 0;
605 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
606 pdcch->dci.aggregLevel = 4;
607 pdcch->dci.beamPdcchInfo.numPrgs = 1;
608 pdcch->dci.beamPdcchInfo.prgSize = 1;
609 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
610 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
611 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
612 pdcch->dci.txPdcchPower.powerValue = 0;
613 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
615 /* fill the PDSCH PDU */
617 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
618 pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
620 pdsch->numCodewords = 1;
621 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
623 pdsch->codeword[cwCount].targetCodeRate = 308;
624 pdsch->codeword[cwCount].qamModOrder = 2;
625 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
626 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
627 pdsch->codeword[cwCount].rvIndex = 0;
628 /* 38.214: Table 5.1.3.2-1, divided by 8 to get the value in bytes */
629 /* TODO : Calculate tbSize based of DL CCCH msg size */
630 tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
631 pdsch->codeword[cwCount].tbSize = tbSize;
633 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
634 pdsch->numLayers = 1;
635 pdsch->transmissionScheme = 0;
637 pdsch->dmrs.dlDmrsSymbPos = 2;
638 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
639 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
640 pdsch->dmrs.scid = 0;
641 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
642 pdsch->dmrs.dmrsPorts = 0;
643 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
644 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
645 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
646 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
647 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
648 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
649 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
650 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
651 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
652 pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
653 pdsch->beamPdschInfo.numPrgs = 1;
654 pdsch->beamPdschInfo.prgSize = 1;
655 pdsch->beamPdschInfo.digBfInterfaces = 0;
656 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
657 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
658 pdsch->txPdschPower.powerControlOffset = 0;
659 pdsch->txPdschPower.powerControlOffsetSS = 0;
661 pdcch->dci.pdschCfg = pdsch;
666 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot)
668 uint8_t k1 = SCH_DEFAULT_K1, ueIdx = 0, dlToUlAckIdx;
669 uint16_t pucchSlot = 0;
670 SchUlSlotInfo *schUlSlotInfo = NULLP;
671 SchPucchCfg *schPucchCfg = NULLP;
673 GET_UE_IDX(crnti, ueIdx);
674 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
676 schPucchCfg = &(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg);
677 if(schPucchCfg->dlDataToUlAck)
679 for(dlToUlAckIdx = 0; dlToUlAckIdx < schPucchCfg->dlDataToUlAck->dlDataToUlAckListCount; dlToUlAckIdx++)
681 //For now considering only the first value in the list
682 k1 = schPucchCfg->dlDataToUlAck->dlDataToUlAckList[dlToUlAckIdx];
688 pucchSlot = (slot + k1) % cell->numSlots;
689 schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
690 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
692 schUlSlotInfo->pucchPres = true;
693 schUlSlotInfo->schPucchInfo.rnti = crnti;
698 /*******************************************************************
700 * @brief Fills pdcch and pdsch info for dedicated DL msg
704 * Function : schDlRsrcAllocDlMsg
707 * Fills pdcch and pdsch info for dl msg
710 * @return ROK - success
713 * ****************************************************************/
714 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
715 uint32_t *accumalatedSize, uint16_t slot)
719 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
720 PdcchCfg *pdcch = NULLP;
721 PdschCfg *pdsch = NULLP;
724 SchControlRsrcSet coreset1;
725 SchPdschConfig pdschCfg;
727 pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
728 pdsch = &dlMsgAlloc->dlMsgPdschCfg;
729 bwp = &dlMsgAlloc->bwp;
731 GET_UE_IDX(crnti, ueIdx);
732 ueCb = cell->ueCb[ueIdx-1];
733 coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
734 pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
737 bwp->freqAlloc.numPrb = MAX_NUM_RB;
738 bwp->freqAlloc.startPrb = 0;
739 bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
740 bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
742 /* fill the PDCCH PDU */
743 //Considering coreset1 also starts from same symbol as coreset0
744 pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
745 pdcch->coresetCfg.durationSymbols = coreset1.duration;
746 memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
747 pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
748 pdcch->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
749 pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
750 pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
751 //Considering number of RBs in coreset1 is same as coreset0
752 pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
753 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
754 pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
756 pdcch->dci.rnti = ueCb.crnti;
757 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
758 pdcch->dci.scramblingRnti = 0;
759 pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
760 pdcch->dci.aggregLevel = 4;
761 pdcch->dci.beamPdcchInfo.numPrgs = 1;
762 pdcch->dci.beamPdcchInfo.prgSize = 1;
763 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
764 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
765 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
766 pdcch->dci.txPdcchPower.powerValue = 0;
767 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
769 /* fill the PDSCH PDU */
771 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
772 pdsch->rnti = ueCb.crnti;
774 pdsch->numCodewords = 1;
775 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
777 pdsch->codeword[cwCount].targetCodeRate = 308;
778 pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
779 pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
780 pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
781 pdsch->codeword[cwCount].rvIndex = 0;
782 tbSize = schCalcTbSize(*accumalatedSize);
783 if(tbSize < *accumalatedSize)
784 *accumalatedSize = tbSize;
785 pdsch->codeword[cwCount].tbSize = tbSize;
787 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
788 pdsch->numLayers = 1;
789 pdsch->transmissionScheme = 0;
791 pdsch->dmrs.dlDmrsSymbPos = 2;
792 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
793 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
794 pdsch->dmrs.scid = 0;
795 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
796 pdsch->dmrs.dmrsPorts = 0;
797 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
798 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
799 pdsch->dmrs.dmrsAddPos = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
800 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
801 pdsch->pdschFreqAlloc.freqAlloc.startPrb = 1;
802 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, numPdschSymbols);
803 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
804 pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
805 pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
806 pdsch->beamPdschInfo.numPrgs = 1;
807 pdsch->beamPdschInfo.prgSize = 1;
808 pdsch->beamPdschInfo.digBfInterfaces = 0;
809 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
810 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
811 pdsch->txPdschPower.powerControlOffset = 0;
812 pdsch->txPdschPower.powerControlOffsetSS = 0;
814 pdcch->dci.pdschCfg = pdsch;
818 /**********************************************************************
820 **********************************************************************/