Moved macCellCfg to duCellCb
[o-du/l2.git] / src / 5gnrsch / sch_common.c
1 /*******************************************************************************
2 ################################################################################
3 #   Copyright (c) [2017-2019] [Radisys]                                        #
4 #                                                                              #
5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
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16 ################################################################################
17  *******************************************************************************/
18
19 /************************************************************************
20
21 Name:     5G NR SCH layer
22
23 Type:     C source file
24
25 Desc:     C source code for Entry point fucntions
26
27 File:     sch_common.c
28
29  **********************************************************************/
30
31 /** @file sch_common.c
32   @brief This module performs common scheduling
33  */
34 #include "common_def.h"
35 #include "tfu.h"
36 #include "lrg.h"
37
38 #include "tfu.x"
39 #include "lrg.x"
40 #include "du_log.h"
41 #include "du_app_mac_inf.h"
42 #include "mac_sch_interface.h"
43 #include "sch.h"
44 #include "sch_utils.h"
45
46 extern SchCb schCb[SCH_MAX_INST];
47 extern uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
48 extern uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
49 extern uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
50
51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
52 {
53    packSchMacUlSchInfo,
54    MacProcUlSchInfo,
55    packSchMacUlSchInfo
56 };
57
58 /**
59  * @brief common resource allocation for SSB
60  *
61  * @details
62  *
63  *     Function : schBroadcastAlloc
64  *     
65  *     This function handles common scheduling for DL
66  *     
67  *  @param[in]  SchCellCb *cell, cell cb
68  *  @param[in]  DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
69  *  @return  void
70  **/
71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
72       uint16_t slot)
73 {
74    /* schedule SSB */
75    uint8_t ssbStartPrb, ssbStartSymb, idx;
76    SchDlSlotInfo *schDlSlotInfo;
77    SsbInfo ssbInfo;
78
79    schDlSlotInfo = cell->schDlSlotInfo[slot];
80    if(dlBrdcstAlloc->ssbTrans)
81    {
82       ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
83       ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
84                                                                                 supporting only 1 ssb beam */
85
86       /* Assign interface structure */
87       for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
88       {
89          ssbInfo.ssbIdx              = idx;
90          ssbInfo.fdAlloc.startPrb    = ssbStartPrb;
91          ssbInfo.fdAlloc.numPrb      = SCH_SSB_NUM_PRB;
92          ssbInfo.tdAlloc.startSymb   = ssbStartSymb;
93          ssbInfo.tdAlloc.numSymb     = SCH_SSB_NUM_SYMB;
94          dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
95          schDlSlotInfo->ssbInfo[idx] = ssbInfo;
96       }
97
98       schDlSlotInfo->ssbPres = true;
99       schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
100       for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
101       {
102          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
103       }
104    }
105
106    /* SIB1 allocation */
107    if(dlBrdcstAlloc->sib1Trans)
108    {
109       uint16_t tbSize         = 0;
110       uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
111       uint8_t mcs             = 4;  /* MCS fixed to 4 */
112       uint8_t numSib1Prb      = 0;
113       schDlSlotInfo->sib1Pres = true;
114
115       tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
116       numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
117       for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
118       {
119          schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
120       }
121       memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg)); 
122       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg)); 
123       memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg)); 
124    }
125    return ROK;
126 }
127
128 /*******************************************************************
129  *
130  * @brief Handles sending UL scheduler info to MAC 
131  *
132  * @details
133  *
134  *    Function : sendUlSchInfoToMac
135  *
136  *    Functionality:
137  *     Sends UL Sch info to MAC from SCH
138  *
139  * @params[in] 
140  * @return ROK     - success
141  *         RFAILED - failure
142  *
143  * ****************************************************************/
144 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
145 {
146    Pst pst;
147
148    memset(&pst, 0, sizeof(Pst));
149    FILL_PST_SCH_TO_MAC(pst, inst);
150    pst.event = EVENT_UL_SCH_INFO;
151
152    return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
153 }
154 /**
155  * @brief resource allocation for PRACH
156  *
157  * @details
158  *
159  *     Function : schPrachResAlloc
160  *     
161  *     This function handles PRACH allocation
162  *     
163  *  @param[in]  SchCellCb *cell, cell cb
164  *  @param[in]  UlSchedInfo *ulSchedInfo, UL scheduling info
165  *  @return  void
166  **/
167 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
168 {
169    uint8_t  puschScs;
170    uint8_t  numPrachRb = 0;
171    uint8_t  numRa = 0;
172    uint8_t  freqStart = 0;
173    uint8_t  prachCfgIdx = 0;
174    uint8_t  prachFormat = 0;
175    uint8_t  x = 0;
176    uint8_t  y = 0;
177    uint16_t prachSubframe = 0;
178    uint8_t  prachStartSymbol = 0;
179    uint8_t  prachOcas = 0;
180    uint8_t  dataType = 0;
181    uint8_t  idx = 0;
182    SchUlSlotInfo *schUlSlotInfo = NULLP;
183
184    puschScs      = cell->cellCfg.schInitialUlBwp.bwp.scs;
185    schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
186    prachCfgIdx   = cell->cellCfg.schRachCfg.prachCfgIdx;
187
188    /* derive the prachCfgIdx table paramters */
189    x                = prachCfgIdxTable[prachCfgIdx][1];
190    y                = prachCfgIdxTable[prachCfgIdx][2];
191    prachSubframe    = prachCfgIdxTable[prachCfgIdx][3];
192
193    if((prachOccasionTimingInfo.sfn%x) == y)
194    {
195       /* check for subFrame number */
196       if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
197       {
198          /* prach ocassion present in this subframe */
199
200          prachFormat      = prachCfgIdxTable[prachCfgIdx][0];
201          prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
202          prachOcas        = prachCfgIdxTable[prachCfgIdx][6];
203
204          /* freq domain resource determination for RACH*/
205          freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
206          /* numRa determined as 𝑛 belonging {0,1,.., M − 1}, 
207           * where M is given by msg1Fdm */
208          numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
209          for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
210          {
211             if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
212             {
213                if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
214                {
215                   if(numRbForPrachTable[idx][2] == puschScs)
216                   {
217                      break;
218                   }
219                }
220             }
221          }
222          numPrachRb = numRbForPrachTable[idx][3];
223          dataType |= SCH_DATATYPE_PRACH;
224          /* Considering first slot in the frame for PRACH */
225          idx = 0;
226          schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
227       }
228       ulSchedInfo->dataType = dataType;
229       /* prach info */
230       ulSchedInfo->prachSchInfo.numPrachOcas   = prachOcas;
231       ulSchedInfo->prachSchInfo.prachFormat    = prachFormat;
232       ulSchedInfo->prachSchInfo.numRa          = numRa;
233       ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
234    }
235 }
236
237 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
238 {
239    /* derive pucchResourceSet from schCellCfg */
240    SchCellCb  *cell = schCb[inst].cells[inst];
241    SchPucchCfgCmn *pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
242    uint8_t pucchIdx = pucchCfg->pucchResourceCommon;
243    SchBwpParams *ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
244
245    schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
246    schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0;
247    schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
248    schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
249    schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
250
251    /* set HARQ flag to true */
252    schPucchInfo->harqFlag = true;
253    schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
254
255    /* set SR and UCI flag to false */
256    schPucchInfo->srFlag  = true;
257    schPucchInfo->uciFlag = true;
258
259    return ROK;
260 }
261
262 /**
263  * @brief resource allocation for UL
264  *
265  * @details
266  *
267  *     Function : schUlResAlloc
268  *     
269  *     This function handles UL Resource allocation
270  *     
271  *  @param[in]  SchCellCb *cell, cellCb
272  *  @return  void
273  **/
274 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
275 {
276    int ret = ROK;
277    UlSchedInfo ulSchedInfo;
278    SchUlSlotInfo  *schUlSlotInfo = NULLP;
279    SlotIndInfo ulTimingInfo;
280    memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
281
282    /* add PHY delta */
283    ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA+SCHED_DELTA);
284
285    ulSchedInfo.cellId = cell->cellId;
286    ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
287    ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
288    ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
289
290    /* Schedule resources for PRACH */
291    schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
292
293    schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot]; 
294    if(schUlSlotInfo->schPuschInfo)
295    {
296       ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
297       ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
298       memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
299             sizeof(SchPuschInfo));
300       SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
301       schUlSlotInfo->schPuschInfo = NULL;
302    }
303
304    if(schUlSlotInfo->pucchPres)
305    {
306       ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
307       fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
308       memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
309             sizeof(SchPucchInfo));
310       memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
311    }
312
313    //send msg to MAC
314    ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
315    if(ret != ROK)
316    {
317       DU_LOG("\nSending UL Sch info from SCH to MAC failed");
318    }
319
320    schInitUlSlot(schUlSlotInfo);
321    return ret;
322 }
323
324 /*******************************************************************
325  *
326  * @brief Fills pdcch and pdsch info for msg4
327  *
328  * @details
329  *
330  *    Function : schDlRsrcAllocMsg4
331  *
332  *    Functionality:
333  *       Fills pdcch and pdsch info for msg4
334  *
335  * @params[in] 
336  * @return ROK     - success
337  *         RFAILED - failure
338  *
339  * ****************************************************************/
340 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
341 {
342    uint8_t coreset0Idx = 0;
343    uint8_t numRbs = 0;
344    uint8_t firstSymbol = 0;
345    uint8_t numSymbols = 0;
346    uint8_t offset = 0;
347    uint8_t offsetPointA;
348    uint8_t FreqDomainResource[6] = {0};
349    uint16_t tbSize = 0;
350    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
351    uint8_t mcs = 4;  /* MCS fixed to 4 */
352    SchBwpDlCfg *initialBwp;
353
354    PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
355    PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
356    BwpCfg *bwp = &msg4Alloc->bwp;
357
358    initialBwp   = &cell->cellCfg.schInitialDlBwp;
359    offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
360    coreset0Idx  = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
361
362    /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
363    numRbs        = coresetIdxTable[coreset0Idx][1];
364    numSymbols    = coresetIdxTable[coreset0Idx][2];
365    offset        = coresetIdxTable[coreset0Idx][3];
366
367    /* calculate time domain parameters */
368    uint16_t mask = 0x2000;
369    for(firstSymbol=0; firstSymbol<14;firstSymbol++)
370    {
371       if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
372          break;
373       else
374          mask = mask>>1;
375    }
376
377    /* calculate the PRBs */
378    schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
379
380    /* fill BWP */
381    bwp->freqAlloc.numPrb   = initialBwp->bwp.freqAlloc.numPrb;
382    bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
383    bwp->subcarrierSpacing  = initialBwp->bwp.scs;
384    bwp->cyclicPrefix       = initialBwp->bwp.cyclicPrefix;
385
386    /* fill the PDCCH PDU */
387    pdcch->coresetCfg.startSymbolIndex = firstSymbol;
388    pdcch->coresetCfg.durationSymbols = numSymbols;
389    memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
390    pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
391    pdcch->coresetCfg.regBundleSize = 6;    /* spec-38.211 sec 7.3.2.2 */
392    pdcch->coresetCfg.interleaverSize = 2;  /* spec-38.211 sec 7.3.2.2 */
393    pdcch->coresetCfg.coreSetType = 0;
394    pdcch->coresetCfg.coreSetSize = numRbs;
395    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
396    pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
397    pdcch->numDlDci = 1;
398    pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
399    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
400    pdcch->dci.scramblingRnti = 0;
401    pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
402    pdcch->dci.aggregLevel = 4;
403    pdcch->dci.beamPdcchInfo.numPrgs = 1;
404    pdcch->dci.beamPdcchInfo.prgSize = 1;
405    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
406    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
407    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
408    pdcch->dci.txPdcchPower.powerValue = 0;
409    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
410
411    /* fill the PDSCH PDU */
412    uint8_t cwCount = 0;
413    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
414    pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
415    pdsch->pduIndex = 0;
416    pdsch->numCodewords = 1;
417    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
418    {
419       pdsch->codeword[cwCount].targetCodeRate = 308;
420       pdsch->codeword[cwCount].qamModOrder = 2;
421       pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
422       pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
423       pdsch->codeword[cwCount].rvIndex = 0;
424       /* 38.214: Table 5.1.3.2-1,  divided by 8 to get the value in bytes */
425       /* TODO : Calculate tbSize based of DL CCCH msg size */
426       tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
427       pdsch->codeword[cwCount].tbSize = tbSize;
428    }
429    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
430    pdsch->numLayers = 1;
431    pdsch->transmissionScheme = 0;
432    pdsch->refPoint = 0;
433    pdsch->dmrs.dlDmrsSymbPos = 2;
434    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
435    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
436    pdsch->dmrs.scid = 0;
437    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
438    pdsch->dmrs.dmrsPorts = 0;
439    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
440    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
441    pdsch->dmrs.dmrsAddPos       = DMRS_ADDITIONAL_POS;
442    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
443    /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
444    pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
445    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
446    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
447    pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
448    pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
449    pdsch->beamPdschInfo.numPrgs = 1;
450    pdsch->beamPdschInfo.prgSize = 1;
451    pdsch->beamPdschInfo.digBfInterfaces = 0;
452    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
453    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
454    pdsch->txPdschPower.powerControlOffset = 0;
455    pdsch->txPdschPower.powerControlOffsetSS = 0;
456
457    pdcch->dci.pdschCfg = pdsch;
458    return ROK;
459 }
460
461 uint16_t schAllocPucchResource(SchCellCb *cell,uint16_t crnti, uint16_t slot)
462 {
463    uint8_t k1 = 1; /* dl-DataToUL-ACK RRC parameter will received from DU-APP msg4-pucch config */
464    uint16_t pucchSlot = (slot + k1)  % SCH_NUM_SLOTS;
465    SchUlSlotInfo  *schUlSlotInfo = NULLP;
466
467    schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
468    memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
469
470    schUlSlotInfo->pucchPres = true;
471    schUlSlotInfo->schPucchInfo.rnti = crnti;
472
473    return ROK;
474 }
475
476 /*******************************************************************
477  *
478  * @brief Fills pdcch and pdsch info for dedicated DL msg
479  *
480  * @details
481  *
482  *    Function : schDlRsrcAllocDlMsg
483  *
484  *    Functionality:
485  *       Fills pdcch and pdsch info for dl msg
486  *
487  * @params[in]
488  * @return ROK     - success
489  *         RFAILED - failure
490  *
491  * ****************************************************************/
492 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
493       uint16_t accumalatedSize, uint16_t slot)
494 {
495    uint8_t ueIdx;
496    uint16_t tbSize = 0;
497    uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
498    uint8_t mcs = 4;  /* MCS fixed to 4 */
499    PdcchCfg *pdcch = NULLP;
500    PdschCfg *pdsch = NULLP;
501    BwpCfg *bwp = NULLP;
502    SchUeCb ueCb;
503    SchControlRsrcSet coreset1;
504    SchPdschConfig pdschCfg;
505
506    pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
507    pdsch = &dlMsgAlloc->dlMsgPdschCfg;
508    bwp = &dlMsgAlloc->bwp;
509
510    GET_UE_IDX(crnti, ueIdx);
511    ueCb  = cell->ueCb[ueIdx-1];
512    coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
513    pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
514
515    /* fill BWP */
516    bwp->freqAlloc.numPrb = MAX_NUM_RB;
517    bwp->freqAlloc.startPrb = 0;
518    bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
519    bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
520
521    /* fill the PDCCH PDU */
522    //Considering coreset1 also starts from same symbol as coreset0
523    pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
524    pdcch->coresetCfg.durationSymbols = coreset1.duration;
525    memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
526    pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
527    pdcch->coresetCfg.regBundleSize = 6;   /* must be 6 for non-interleaved */
528    pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
529    pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
530    //Considering number of RBs in coreset1 is same as coreset0
531    pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
532    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
533    pdcch->coresetCfg.precoderGranularity =  coreset1.precoderGranularity;
534    pdcch->numDlDci = 1;
535    pdcch->dci.rnti = ueCb.crnti;
536    pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
537    pdcch->dci.scramblingRnti = 0;
538    pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
539    pdcch->dci.aggregLevel = 4;
540    pdcch->dci.beamPdcchInfo.numPrgs = 1;
541    pdcch->dci.beamPdcchInfo.prgSize = 1;
542    pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
543    pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
544    pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
545    pdcch->dci.txPdcchPower.powerValue = 0;
546    pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
547
548    /* fill the PDSCH PDU */
549    uint8_t cwCount = 0;
550    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
551    pdsch->rnti = ueCb.crnti;
552    pdsch->pduIndex = 0;
553    pdsch->numCodewords = 1;
554    for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
555    {
556       pdsch->codeword[cwCount].targetCodeRate = 308;
557       pdsch->codeword[cwCount].qamModOrder = 2;
558       pdsch->codeword[cwCount].mcsIndex = 4; /* mcs configured to 4 */
559       pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
560       pdsch->codeword[cwCount].rvIndex = 0;
561       tbSize = schCalcTbSize(accumalatedSize);
562       pdsch->codeword[cwCount].tbSize = tbSize;
563    }
564    pdsch->dataScramblingId = cell->cellCfg.phyCellId;
565    pdsch->numLayers = 1;
566    pdsch->transmissionScheme = 0;
567    pdsch->refPoint = 0;
568    pdsch->dmrs.dlDmrsSymbPos = 2;
569    pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
570    pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
571    pdsch->dmrs.scid = 0;
572    pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
573    pdsch->dmrs.dmrsPorts = 0;
574    pdsch->dmrs.mappingType      = DMRS_MAP_TYPE_A; /* Setting to Type-A */
575    pdsch->dmrs.nrOfDmrsSymbols  = NUM_DMRS_SYMBOLS;
576    pdsch->dmrs.dmrsAddPos       = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
577    pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
578    pdsch->pdschFreqAlloc.freqAlloc.startPrb = 1;
579    pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
580    pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
581    pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
582    pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
583    pdsch->beamPdschInfo.numPrgs = 1;
584    pdsch->beamPdschInfo.prgSize = 1;
585    pdsch->beamPdschInfo.digBfInterfaces = 0;
586    pdsch->beamPdschInfo.prg[0].pmIdx = 0;
587    pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
588    pdsch->txPdschPower.powerControlOffset = 0;
589    pdsch->txPdschPower.powerControlOffsetSS = 0;
590
591    pdcch->dci.pdschCfg = pdsch;
592    return ROK;
593 }
594
595 /**********************************************************************
596   End of file
597  **********************************************************************/
598