1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
34 #include "common_def.h"
41 #include "du_app_mac_inf.h"
42 #include "mac_sch_interface.h"
44 #include "sch_utils.h"
46 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
54 * @brief common resource allocation for SSB
58 * Function : schBroadcastSsbAlloc
60 * This function handles common scheduling for SSB
62 * @param[in] SchCellCb *cell, cell cb
63 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
66 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc)
69 uint8_t ssbStartSymb, idx;
71 SchDlSlotInfo *schDlSlotInfo;
76 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : Cell is NULL");
80 if(dlBrdcstAlloc == NULL)
82 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : dlBrdcstAlloc is NULL");
86 schDlSlotInfo = cell->schDlSlotInfo[slotTime.slot];
87 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; //+Kssb
88 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are supporting only 1 ssb beam */
90 /* Assign interface structure */
91 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
94 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
95 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
96 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
97 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
98 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
99 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
102 if((allocatePrbDl(cell, slotTime, ssbStartSymb, SCH_SSB_NUM_SYMB, &ssbInfo.fdAlloc.startPrb, ssbInfo.fdAlloc.numPrb)) != ROK)
104 DU_LOG("\nERROR --> SCH: PRB allocation failed for SSB in SFN:SLOT [%d : %d]", slotTime.sfn, slotTime.slot);
109 schDlSlotInfo->ssbPres = true;
110 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
115 * @brief common resource allocation for SIB1
119 * Function : schBroadcastSib1Alloc
121 * This function handles common scheduling for SIB1
123 * @param[in] SchCellCb *cell, cell cb
124 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
127 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc)
129 uint8_t dmrsStartSymbol, startSymbol, numSymbol ;
131 FreqDomainAlloc freqAlloc;
132 TimeDomainAlloc timeAlloc;
133 SchDlSlotInfo *schDlSlotInfo = NULLP;
137 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : Cell is NULL");
141 if(dlBrdcstAlloc == NULL)
143 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : dlBrdcstAlloc is NULL");
147 dmrs = cell->cellCfg.sib1SchCfg.sib1PdschCfg.dmrs;
148 freqAlloc = cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc;
149 timeAlloc = cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschTimeAlloc.timeAlloc;
150 schDlSlotInfo = cell->schDlSlotInfo[slotTime.slot];
152 /* Find total symbols used including DMRS */
153 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
154 * in that case only PDSCH symbols are marked as occupied */
155 dmrsStartSymbol = findDmrsStartSymbol(dmrs.dlDmrsSymbPos);
156 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
158 startSymbol = timeAlloc.startSymb;
159 numSymbol = timeAlloc.numSymb;
161 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
164 startSymbol = dmrsStartSymbol;
165 numSymbol = dmrs.nrOfDmrsSymbols + timeAlloc.numSymb;
169 if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol, &freqAlloc.startPrb, freqAlloc.numPrb)) != ROK)
171 DU_LOG("\nERROR --> SCH: PRB allocation failed for SIB1 in SFN:Slot [%d : %d]", slotTime.sfn, slotTime.slot);
175 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
176 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
177 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
178 dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
179 schDlSlotInfo->sib1Pres = true;
183 /*******************************************************************
185 * @brief Handles sending UL scheduler info to MAC
189 * Function : sendUlSchInfoToMac
192 * Sends UL Sch info to MAC from SCH
195 * @return ROK - success
198 * ****************************************************************/
199 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
203 memset(&pst, 0, sizeof(Pst));
204 FILL_PST_SCH_TO_MAC(pst, inst);
205 pst.event = EVENT_UL_SCH_INFO;
207 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
211 * @brief Function to fill Pucch Format 0
215 * Function : fillPucchFormat0
217 * Function to fill Pucch format 0
219 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
223 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
225 if(resrcInfo->SchPucchFormat.format0)
227 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
228 ulSchedPucch->pucchFormat = PUCCH_FORMAT_0;
229 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format0->initialCyclicShift;
230 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
231 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
236 * @brief Function to fill Pucch Format 1
240 * Function : fillPucchFormat1
242 * Function to fill Pucch format 1
244 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
248 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
250 if(resrcInfo->SchPucchFormat.format1)
252 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
253 ulSchedPucch->pucchFormat = PUCCH_FORMAT_1;
254 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format1->initialCyclicShift;
255 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
256 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
257 ulSchedPucch->timeDomOCC = resrcInfo->SchPucchFormat.format1->timeDomOCC;
262 * @brief Function to fill Pucch format for UL Sched Info
266 * Function : fillUlSchedPucchFormat
268 * Function to fill Pucch format for UL Sched Info
270 * @param[in] pucchFormat , SchPucchInfo pointer,
271 * @param[in] SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
275 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
276 SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
285 fillPucchFormat0(ulSchedPucch, resrcInfo);
292 fillPucchFormat1(ulSchedPucch, resrcInfo);
296 memcpy(&ulSchedPucch->cmnFormatCfg, formatCfg, sizeof(SchPucchFormatCfg));
299 }/* To Add support for more Pucch Format */
302 DU_LOG("\nERROR --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
310 * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
314 * Function : fillUlSchedPucchDedicatedCfg
316 * Function to fill Pucch Dedicated Cfg for UL Sched Info
318 * @param[in] pucchFormat to be filled
319 * @param[in] SchPucchFormatCfg pointer, SchPucchCfg pointer
323 uint8_t fillUlSchedPucchDedicatedCfg(SchCellCb *cell, SchPucchCfg *pucchDedCfg,\
324 SlotTimingInfo *slotInfo, SchPucchInfo *ulSchedPucch)
326 uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
327 uint16_t srOffset = 0;
328 uint16_t numSlots = cell->numSlots;
329 bool isAllocated = false;
330 uint16_t pucchStartPrb;
332 if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
334 //Assuming one entry in the list
335 for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
337 for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
339 if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
340 pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
342 ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
343 ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
344 ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
345 ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
346 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
347 &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
351 pucchStartPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
352 ret = allocatePrbUl(cell, *slotInfo, ulSchedPucch->tdAlloc.startSymb, ulSchedPucch->tdAlloc.numSymb, &pucchStartPrb, PUCCH_NUM_PRB_FORMAT_0_1_4);
365 if(pucchDedCfg->format1)
367 memset(&ulSchedPucch->cmnFormatCfg, 0, sizeof(SchPucchFormatCfg));
368 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
378 /* setting SR and UCI flag */
379 if(pucchDedCfg->schedReq)
381 for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
383 srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
384 srOffset = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
387 if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
389 ulSchedPucch->srFlag = true;
390 ulSchedPucch->uciFlag = true;
392 ulSchedPucch->harqFlag = true;//check how to enable?
398 * @brief Function to fill Pucch Resource Info
402 * Function : fillPucchResourceInfo
404 * Function to fill Pucch Resource Info
406 * @param[in] SchPucchInfo *schPucchInfo, Inst inst
407 * @return ROK/RFAILED
410 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst, SlotTimingInfo slotInfo)
412 uint8_t ret = ROK, ueId = 0, ueIdx = 0, pucchIdx = 0;
413 SchCellCb *cell = schCb[inst].cells[inst];
414 SchPucchCfgCmn *pucchCfg = NULLP;
415 SchBwpParams *ulBwp = NULLP;
418 GET_UE_ID(schPucchInfo->rnti, ueId);
420 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfgPres)
422 /* fill pucch dedicated cfg */
423 ret = fillUlSchedPucchDedicatedCfg(cell,\
424 &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellCfg.initUlBwp.pucchCfg, &slotInfo, schPucchInfo);
427 memset(schPucchInfo, 0, sizeof(SchPucchInfo));
428 DU_LOG("\nERROR --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
434 /* fill pucch common cfg */
435 /* derive pucchResourceSet from schCellCfg */
436 pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
437 pucchIdx = pucchCfg->pucchResourceCommon;
438 ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
439 startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
440 ret = allocatePrbUl(cell, slotInfo, pucchResourceSet[pucchIdx][1], pucchResourceSet[pucchIdx][2],\
441 &startPrb, PUCCH_NUM_PRB_FORMAT_0_1_4);
444 schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
445 schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
446 schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
447 schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
448 schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
450 /* set SR and UCI flag to false */
451 schPucchInfo->srFlag = true;
452 schPucchInfo->uciFlag = true;
459 * @brief resource allocation for UL
463 * Function : schUlResAlloc
465 * This function handles UL Resource allocation
467 * @param[in] SchCellCb *cell, cellCb
470 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
473 UlSchedInfo ulSchedInfo;
474 SchUlSlotInfo *schUlSlotInfo = NULLP;
475 SlotTimingInfo ulTimingInfo;
476 memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
479 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA_UL+SCHED_DELTA);
481 ulSchedInfo.cellId = cell->cellId;
482 ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
483 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
484 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
486 /* Schedule resources for PRACH */
487 if(cell->firstSib1Transmitted)
488 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
490 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
491 if(schUlSlotInfo->schPuschInfo)
493 ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
494 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
495 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
496 sizeof(SchPuschInfo));
497 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
498 schUlSlotInfo->schPuschInfo = NULL;
501 if(schUlSlotInfo->pucchPres)
503 ret = fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst, ulTimingInfo);
506 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
507 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
508 sizeof(SchPucchInfo));
510 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
514 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
517 DU_LOG("\nERROR --> SCH : Sending UL Sch info from SCH to MAC failed");
520 schInitUlSlot(schUlSlotInfo);
524 /*******************************************************************
526 * @brief Fills pdcch and pdsch info for msg4
530 * Function : schDlRsrcAllocMsg4
533 * Fills pdcch and pdsch info for msg4
535 * @params[in] SchCellCb *cell, SlotTimingInfo msg4Time
536 * @params[in] uint8_t ueId, DlMsgAlloc *dlMsgAlloc
537 * @params[in] uint8_t pdschStartSymbol, uint8_t pdschNumSymbols
538 * @params[in] bool isRetx, SchDlHqProcCb *hqP
539 * @return ROK - success
542 * ****************************************************************/
543 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgAlloc *dlMsgAlloc,\
544 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP)
546 uint8_t coreset0Idx = 0;
547 uint8_t firstSymbol = 0;
548 uint8_t numSymbols = 0;
549 uint8_t mcs = DEFAULT_MCS; /* MCS fixed to 4 */
550 uint8_t dmrsStartSymbol = 0, startSymbol = 0, numSymbol = 0;
553 SchBwpDlCfg *initialBwp = NULLP;
554 PdcchCfg *pdcch = NULLP;
555 PdschCfg *pdsch = NULLP;
557 DlMsgSchInfo *msg4Alloc = NULLP;
561 DU_LOG("\nERROR --> SCH: schDlRsrcAllocMsg4() : Cell is NULL");
565 if(dlMsgAlloc == NULL)
567 DU_LOG("\nERROR --> SCH: schDlRsrcAllocMsg4() : dlMsgAlloc is NULL");
571 msg4Alloc = &dlMsgAlloc->dlMsgSchedInfo[dlMsgAlloc->numSchedInfo];
572 initialBwp = &cell->cellCfg.schInitialDlBwp;
573 pdcch = &msg4Alloc->dlMsgPdcchCfg;
574 pdsch = &msg4Alloc->dlMsgPdschCfg;
575 bwp = &msg4Alloc->bwp;
576 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
578 fillDlMsgInfo(&msg4Alloc->dlMsgInfo, cell->raCb[ueId-1].tcrnti, isRetx, hqP);
579 msg4Alloc->dlMsgInfo.dlMsgPduLen = cell->raCb[ueId-1].dlMsgPduLen;
581 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
582 numRbs = coresetIdxTable[coreset0Idx][1];
583 numSymbols = coresetIdxTable[coreset0Idx][2];
585 /* calculate time domain parameters */
586 uint16_t mask = 0x2000;
587 for(firstSymbol=0; firstSymbol<MAX_SYMB_PER_SLOT; firstSymbol++)
589 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
596 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
597 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
598 bwp->subcarrierSpacing = initialBwp->bwp.scs;
599 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
601 /* fill the PDCCH PDU */
602 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
603 pdcch->coresetCfg.durationSymbols = numSymbols;
604 memcpy(pdcch->coresetCfg.freqDomainResource, \
605 cell->cellCfg.schInitialDlBwp.pdcchCommon.commonSearchSpace.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
607 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
608 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
609 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
610 pdcch->coresetCfg.coreSetType = 0;
611 pdcch->coresetCfg.coreSetSize = numRbs;
612 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
613 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
615 pdcch->dci.rnti = cell->raCb[ueId-1].tcrnti;
616 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
617 pdcch->dci.scramblingRnti = 0;
618 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
619 pdcch->dci.aggregLevel = 4;
620 pdcch->dci.beamPdcchInfo.numPrgs = 1;
621 pdcch->dci.beamPdcchInfo.prgSize = 1;
622 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
623 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
624 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
625 pdcch->dci.txPdcchPower.powerValue = 0;
626 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
627 pdcch->dci.pdschCfg = pdsch;
629 /* fill the PDSCH PDU */
631 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
632 pdsch->rnti = cell->raCb[ueId-1].tcrnti;
634 pdsch->numCodewords = 1;
635 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
637 pdsch->codeword[cwCount].targetCodeRate = 308;
638 pdsch->codeword[cwCount].qamModOrder = 2;
639 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
640 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
643 tbSize = schCalcTbSize(msg4Alloc->dlMsgInfo.dlMsgPduLen + TX_PAYLOAD_HDR_LEN); /* MSG4 size + FAPI header size*/
644 hqP->tbInfo[cwCount].tbSzReq = tbSize;
645 pdsch->codeword[cwCount].rvIndex = 0;
649 pdsch->codeword[cwCount].rvIndex = (pdsch->codeword[cwCount].rvIndex +1) & 0x03;
650 tbSize = hqP->tbInfo[cwCount].tbSzReq;
652 pdsch->codeword[cwCount].tbSize = tbSize;
654 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
655 pdsch->numLayers = 1;
656 pdsch->transmissionScheme = 0;
658 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
659 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
660 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
661 pdsch->dmrs.scid = 0;
662 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
663 pdsch->dmrs.dmrsPorts = 0;
664 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
665 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
666 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
668 pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschStartSymbol;
669 pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschNumSymbols;
671 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
672 pdsch->pdschFreqAlloc.freqAlloc.startPrb = MAX_NUM_RB;
673 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, pdschNumSymbols);
674 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
676 /* Find total symbols occupied including DMRS */
677 dmrsStartSymbol = findDmrsStartSymbol(pdsch->dmrs.dlDmrsSymbPos);
678 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
679 * in that case only PDSCH symbols are marked as occupied */
680 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
682 startSymbol = pdsch->pdschTimeAlloc.timeAlloc.startSymb;
683 numSymbol = pdsch->pdschTimeAlloc.timeAlloc.numSymb;
685 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
688 startSymbol = dmrsStartSymbol;
689 numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.timeAlloc.numSymb;
692 /* Allocate the number of PRBs required for RAR PDSCH */
693 if((allocatePrbDl(cell, msg4Time, startSymbol, numSymbol,\
694 &pdsch->pdschFreqAlloc.freqAlloc.startPrb, pdsch->pdschFreqAlloc.freqAlloc.numPrb)) != ROK)
696 DU_LOG("\nERROR --> SCH : Resource allocation failed for MSG4");
700 pdsch->beamPdschInfo.numPrgs = 1;
701 pdsch->beamPdschInfo.prgSize = 1;
702 pdsch->beamPdschInfo.digBfInterfaces = 0;
703 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
704 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
705 pdsch->txPdschPower.powerControlOffset = 0;
706 pdsch->txPdschPower.powerControlOffsetSS = 0;
708 msg4Alloc->dlMsgInfo.isMsg4Pdu = true;
712 /*******************************************************************
714 * @brief Scheduling for Pucch Resource
718 * Function : schAllocPucchResource
721 * Scheduling for Pucch Resource
723 * @params[in] SchCellCb *cell, SlotTimingInfo pucchTime, crnti
724 * @params[in] SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP
725 * @return ROK - success
728 *******************************************************************/
730 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,
731 SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP)
733 uint16_t pucchSlot = 0;
734 SchUlSlotInfo *schUlSlotInfo = NULLP;
736 pucchSlot = pucchTime.slot;
737 schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
738 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
740 schUlSlotInfo->pucchPres = true;
741 schUlSlotInfo->schPucchInfo.rnti = crnti;
744 /* set HARQ flag to true */
745 schUlSlotInfo->schPucchInfo.harqFlag = true;
746 schUlSlotInfo->schPucchInfo.numHarqBits = 1; /* 1 bit for HARQ */
747 ADD_DELTA_TO_TIME(pucchTime, pucchTime, 3); /* SLOT_DELAY=3 */
748 cmLListAdd2Tail(&(ueCb->hqDlmap[pucchTime.slot]->hqList), &hqP->ulSlotLnk);
753 /*******************************************************************
755 * @brief Fills pdcch and pdsch info for dedicated DL msg
759 * Function : schDlRsrcAllocDlMsg
762 * Fills pdcch and pdsch info for dl msg
764 * @params[in] SchCellCb *cell, SlotTimingInfo slotTime
765 * @params[in] uint16_t crnti, uint32_t tbSize
766 * @params[in] DlMsgAlloc *dlMsgAlloc, uint16_t startPRB
767 * @params[in] uint8_t pdschStartSymbol, uint8_t pdschNumSymbols
768 * @params[in] bool isRetx, SchDlHqProcCb *hqP
769 * @return ROK - success
772 * ****************************************************************/
773 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
774 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol,
775 uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP)
778 PdcchCfg *pdcch = NULLP;
779 PdschCfg *pdsch = NULLP;
782 SchControlRsrcSet coreset1;
783 SchPdschConfig pdschCfg;
784 uint8_t dmrsStartSymbol, startSymbol, numSymbol;
786 pdcch = &dlMsgAlloc->dlMsgSchedInfo[dlMsgAlloc->numSchedInfo].dlMsgPdcchCfg;
787 pdsch = &dlMsgAlloc->dlMsgSchedInfo[dlMsgAlloc->numSchedInfo].dlMsgPdschCfg;
788 bwp = &dlMsgAlloc->dlMsgSchedInfo[dlMsgAlloc->numSchedInfo].bwp;
790 GET_UE_ID(crnti, ueId);
791 ueCb = cell->ueCb[ueId-1];
792 coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
793 pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
796 bwp->freqAlloc.numPrb = MAX_NUM_RB;
797 bwp->freqAlloc.startPrb = 0;
798 bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
799 bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
801 /* fill the PDCCH PDU */
802 //Considering coreset1 also starts from same symbol as coreset0
803 pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
804 pdcch->coresetCfg.durationSymbols = coreset1.duration;
805 memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
806 pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
807 pdcch->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
808 pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
809 pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
810 //Considering number of RBs in coreset1 is same as coreset0
811 pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
812 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
813 pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
815 pdcch->dci.rnti = ueCb.crnti;
816 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
817 pdcch->dci.scramblingRnti = 0;
818 pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
819 pdcch->dci.aggregLevel = 4;
820 pdcch->dci.beamPdcchInfo.numPrgs = 1;
821 pdcch->dci.beamPdcchInfo.prgSize = 1;
822 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
823 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
824 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
825 pdcch->dci.txPdcchPower.powerValue = 0;
826 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
828 /* fill the PDSCH PDU */
830 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
831 pdsch->rnti = ueCb.crnti;
833 pdsch->numCodewords = 1;
834 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
836 pdsch->codeword[cwCount].targetCodeRate = 308;
837 pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
838 pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
839 pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
840 pdsch->codeword[cwCount].rvIndex = 0;
844 tbSize +=TX_PAYLOAD_HDR_LEN;
845 hqP->tbInfo[cwCount].tbSzReq = tbSize;
847 pdsch->codeword[cwCount].tbSize = tbSize;
849 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
850 pdsch->numLayers = 1;
851 pdsch->transmissionScheme = 0;
853 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
854 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
855 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
856 pdsch->dmrs.scid = 0;
857 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
858 pdsch->dmrs.dmrsPorts = 0;
859 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
860 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
861 pdsch->dmrs.dmrsAddPos = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
863 pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschStartSymbol;
864 pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschNumSymbols;
866 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
867 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
868 pdsch->pdschFreqAlloc.freqAlloc.startPrb = startPRB; /*Start PRB will be already known*/
869 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, pdschNumSymbols);
871 /* Find total symbols occupied including DMRS */
872 dmrsStartSymbol = findDmrsStartSymbol(pdsch->dmrs.dlDmrsSymbPos);
873 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
874 * in that case only PDSCH symbols are marked as occupied */
875 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
877 startSymbol = pdsch->pdschTimeAlloc.timeAlloc.startSymb;
878 numSymbol = pdsch->pdschTimeAlloc.timeAlloc.numSymb;
880 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
883 startSymbol = dmrsStartSymbol;
884 numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.timeAlloc.numSymb;
887 /* Allocate the number of PRBs required for DL PDSCH */
888 if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol,\
889 &pdsch->pdschFreqAlloc.freqAlloc.startPrb, pdsch->pdschFreqAlloc.freqAlloc.numPrb)) != ROK)
891 DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for DL MSG");
895 pdsch->beamPdschInfo.numPrgs = 1;
896 pdsch->beamPdschInfo.prgSize = 1;
897 pdsch->beamPdschInfo.digBfInterfaces = 0;
898 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
899 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
900 pdsch->txPdschPower.powerControlOffset = 0;
901 pdsch->txPdschPower.powerControlOffsetSS = 0;
903 pdcch->dci.pdschCfg = pdsch;
907 /*******************************************************************
909 * @brief Fills k0 and k1 information table for FDD
913 * Function : BuildK0K1TableForFdd
916 * Fills k0 and k1 information table for FDD
918 * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool
919 * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc
920 * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc
921 * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl
922 * @return ROK - success
925 * ****************************************************************/
926 void BuildK0K1TableForFdd(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres,SchPdschCfgCmn pdschCmnCfg,\
927 SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl)
930 uint8_t k1TmpVal =0, cfgIdx=0;
931 uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, numTimeDomAlloc=0;
933 /* TODO Commented these below lines for resolving warnings. Presently these variable are not
934 * required but this will require for harq processing */
935 // uint8_t k0TmpVal = 0;
936 // SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
937 // SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
939 /* Initialization the structure and storing the total slot values. */
940 memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl));
941 k0K1InfoTbl->tblSize = cell->numSlots;
943 /* Storing time domain resource allocation list based on common or dedicated configuration. */
944 if(pdschCfgCmnPres == true)
946 numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc;
947 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
949 /*TODO uncomment this line during harq processing */
950 //cmnTimeDomRsrcAllocList[cfgIdx] = pdschCmnCfg.timeDomRsrcAllocList[cfgIdx];
955 numTimeDomAlloc = pdschDedCfg.numTimeDomRsrcAlloc;
956 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
958 /*TODO uncomment this line during harq processing */
959 //dedTimeDomRsrcAllocList[cfgIdx] = pdschDedCfg.timeDomRsrcAllociList[cfgIdx];
963 /* Checking all the slots for K0 and K1 values. */
964 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
967 /* Storing the values of k0 based on time domain resource
968 * allocation list. If the value is unavailable then fill default values,
969 * As per 38.331 PDSCH-TimeDomainResourceAllocation field descriptions. */
970 for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++)
972 /* TODO These if 0 we will remove during harq processing */
974 if(pdschCfgCmnPres == true)
976 k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0;
980 if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP)
982 k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0);
986 k0TmpVal = DEFAULT_K0_VALUE;
990 /* Checking all the Ul Alloc values. If value is less than MIN_NUM_K1_IDX
991 * then skip else continue storing the values. */
993 for(k1Index = 0; k1Index < ulAckListCount; k1Index++)
995 k1TmpVal = UlAckTbl[k1Index];
996 if(k1TmpVal <= MIN_NUM_K1_IDX)
1001 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index;
1002 /* TODO Store K1 index where harq feedback will be received in harq table. */
1006 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1;
1007 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index;
1013 k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0;
1018 /*******************************************************************
1020 * @brief Fills k0 and k1 information table
1024 * Function : BuildK0K1Table
1027 * Fills K0 and k1 information table
1029 * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool
1030 * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc
1031 * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc
1032 * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl
1033 * @return ROK - success
1036 * ****************************************************************/
1037 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, SchPdschCfgCmn pdschCmnCfg,\
1038 SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl)
1043 bool ulSlotPresent = false;
1044 uint8_t k0TmpVal = 0, k1TmpVal =0, tmpSlot=0, startSymbol=0, endSymbol=0, checkSymbol=0;
1045 uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, cfgIdx=0, numTimeDomAlloc =0, totalCfgSlot =0;
1046 SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
1047 SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
1050 if(cell->cellCfg.dupMode == DUPLEX_MODE_FDD)
1052 BuildK0K1TableForFdd(cell, k0K1InfoTbl, pdschCfgCmnPres, pdschCmnCfg, pdschDedCfg, ulAckListCount, UlAckTbl);
1058 /* Initialization the K0K1 structure, total num of slot and calculating the slot pattern length. */
1059 memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl));
1060 k0K1InfoTbl->tblSize = cell->numSlots;
1061 totalCfgSlot = calculateSlotPatternLength(cell->cellCfg.ssbSchCfg.scsCommon, cell->cellCfg.tddCfg.tddPeriod);
1063 /* Storing time domain resource allocation list based on common or
1064 * dedicated configuration availability. */
1065 if(pdschCfgCmnPres == true)
1067 numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc;
1068 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1070 cmnTimeDomRsrcAllocList[cfgIdx] = pdschCmnCfg.timeDomRsrcAllocList[cfgIdx];
1075 numTimeDomAlloc = pdschDedCfg.numTimeDomRsrcAlloc;
1076 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1078 dedTimeDomRsrcAllocList[cfgIdx] = pdschDedCfg.timeDomRsrcAllociList[cfgIdx];
1082 /* Checking all possible indexes for K0 and K1 values. */
1083 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1085 /* If current slot is UL or FLEXI then Skip because PDCCH is sent only in DL slots. */
1086 slotCfg = schGetSlotSymbFrmt(slotIdx%totalCfgSlot, cell->slotFrmtBitMap);
1087 if(slotCfg == UL_SLOT || slotCfg == FLEXI_SLOT)
1092 /* Storing K0 , start symbol and length symbol for further processing.
1093 * If K0 value is not available then we can fill the default values
1094 * given in spec 38.331. */
1096 for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++)
1098 if(pdschCfgCmnPres == true)
1100 k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0;
1101 startSymbol = cmnTimeDomRsrcAllocList[k0Index].startSymbol;
1102 endSymbol = startSymbol + cmnTimeDomRsrcAllocList[k0Index].lengthSymbol;
1106 if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP)
1108 k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0);
1112 k0TmpVal = DEFAULT_K0_VALUE;
1114 startSymbol = dedTimeDomRsrcAllocList[k0Index].startSymbol;
1115 endSymbol = startSymbol + dedTimeDomRsrcAllocList[k0Index].symbolLength;
1118 /* If current slot + k0 is UL then skip the slot
1119 * else if it is DL slot then continue the next steps
1120 * else if it is a FLEXI slot then check symbols of slot, It should not
1121 * contain any UL slot. */
1122 tmpSlot = (slotIdx+k0TmpVal) % totalCfgSlot;
1123 slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap);
1124 if(slotCfg == UL_SLOT)
1128 if(slotCfg == FLEXI_SLOT)
1130 for(checkSymbol = startSymbol; checkSymbol<endSymbol; checkSymbol ++)
1132 slotCfg = cell->cellCfg.tddCfg.slotCfg[tmpSlot][checkSymbol];
1133 if(slotCfg == UL_SLOT)
1140 /* If current slot + k0 + k1 is a DL slot then skip the slot
1141 * else if it is UL slot then store the information
1142 * else if it is FLEXI slot then check the symbols, it must have
1143 * at least one UL symbol. */
1145 for(k1Index = 0; k1Index < ulAckListCount; k1Index++)
1147 k1TmpVal = UlAckTbl[k1Index];
1148 if(k1TmpVal > MIN_NUM_K1_IDX)
1150 tmpSlot = (slotIdx+k0TmpVal+k1TmpVal) % totalCfgSlot;
1151 slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap);
1152 if(slotCfg == DL_SLOT)
1156 if(slotCfg == FLEXI_SLOT)
1158 for(checkSymbol = 0; checkSymbol< MAX_SYMB_PER_SLOT;checkSymbol++)
1160 if(cell->cellCfg.tddCfg.slotCfg[tmpSlot][checkSymbol] == UL_SLOT)
1162 ulSlotPresent = true;
1167 if(ulSlotPresent == true || slotCfg == UL_SLOT)
1169 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index;
1170 /* TODO Store K1 index where harq feedback will be received
1176 /* Store all the values if all condition satisfies. */
1179 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1;
1180 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index;
1186 k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0;
1193 /*******************************************************************
1195 * @brief Fills K2 information table for FDD
1199 * Function : BuildK2InfoTableForFdd
1202 * Fills K2 information table for FDD
1204 * @params[in] SchCellCb *cell,SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[],
1205 * uint16_t puschSymTblSize,SchK2TimingInfoTbl *k2InfoTbl
1206 * @return ROK - success
1209 * ****************************************************************/
1210 void BuildK2InfoTableForFdd(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], uint16_t puschSymTblSize,\
1211 SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl)
1213 uint16_t slotIdx=0, k2Index=0, k2TmpIdx=0, msg3K2TmpIdx=0;
1215 /* Initialization the structure and storing the total slot values. */
1216 memset(k2InfoTbl, 0, sizeof(SchK2TimingInfoTbl));
1217 k2InfoTbl->tblSize = cell->numSlots;
1219 msg3K2InfoTbl->tblSize = cell->numSlots;
1221 /* Checking all possible indexes for K2. */
1222 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1224 /* Storing K2 values. */
1225 for(k2Index = 0; ((k2Index < puschSymTblSize) && (k2Index < MAX_NUM_K2_IDX)); k2Index++)
1227 k2TmpIdx= k2InfoTbl->k2TimingInfo[slotIdx].numK2;
1228 k2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[k2TmpIdx] = k2Index;
1229 k2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1231 /* Updating K2 values for MSG3 */
1234 msg3K2TmpIdx = msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2;
1235 msg3K2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[msg3K2TmpIdx] = k2Index;
1236 msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1242 /*******************************************************************
1244 * @brief Fills K2 information table
1248 * Function : BuildK2InfoTable
1251 * Fills K2 information table
1253 * @params[in] SchCellCb *cell,SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[],
1254 * uint16_t puschSymTblSize, SchK2TimingInfoTbl *k2InfoTbl
1255 * @return ROK - success
1258 * ****************************************************************/
1259 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], uint16_t puschSymTblSize,\
1260 SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl)
1264 bool dlSymbolPresent = false;
1265 uint8_t slotIdx=0, k2Index=0, k2Val=0, k2TmpVal=0, msg3K2TmpVal=0, msg3Delta=0, numK2 =0, currentSymbol =0;
1266 uint8_t startSymbol =0, endSymbol =0, checkSymbol=0, totalCfgSlot=0, slotCfg=0;
1267 SlotConfig currentSlot;
1270 if(cell->cellCfg.dupMode == DUPLEX_MODE_FDD)
1272 BuildK2InfoTableForFdd(cell, timeDomRsrcAllocList, puschSymTblSize, msg3K2InfoTbl, k2InfoTbl);
1278 /* Initialization the structure and storing the total slot values. */
1279 memset(k2InfoTbl, 0, sizeof(SchK2TimingInfoTbl));
1280 k2InfoTbl->tblSize = cell->numSlots;
1282 msg3K2InfoTbl->tblSize = cell->numSlots;
1283 totalCfgSlot = calculateSlotPatternLength(cell->cellCfg.ssbSchCfg.scsCommon, cell->cellCfg.tddCfg.tddPeriod);
1285 /* Checking all possible indexes for K2. */
1286 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1288 currentSlot = schGetSlotSymbFrmt(slotIdx % totalCfgSlot, cell->slotFrmtBitMap);
1290 /* If current slot is UL then skip because PDCCH is sent only in DL slots */
1291 if(currentSlot != UL_SLOT)
1293 for(k2Index = 0; ((k2Index < puschSymTblSize) && (k2Index < MAX_NUM_K2_IDX)); k2Index++)
1295 /* Storing k2, startSymbol, endSymbol information for further processing.
1296 * If k2 is absent then fill the default values given in spec 38.331
1297 * PUSCH-TimeDomainResourceAllocationList field descriptions */
1298 k2Val = timeDomRsrcAllocList[k2Index].k2;
1301 switch(cell->cellCfg.ssbSchCfg.scsCommon)
1304 k2Val = DEFAULT_K2_VALUE_FOR_SCS15;
1307 k2Val = DEFAULT_K2_VALUE_FOR_SCS30;
1310 k2Val = DEFAULT_K2_VALUE_FOR_SCS60;
1313 k2Val = DEFAULT_K2_VALUE_FOR_SCS120;
1318 /* Current slot + k2 should be either UL or FLEXI slot.
1319 * If slot is FLEXI then check all the symbols of that slot,
1320 * it should not contain any DL or FLEXI slot */
1321 k2TmpVal = (slotIdx + k2Val) % totalCfgSlot;
1322 slotCfg = schGetSlotSymbFrmt(k2TmpVal, cell->slotFrmtBitMap);
1323 if(slotCfg != DL_SLOT)
1325 if(slotCfg == FLEXI_SLOT)
1327 startSymbol = timeDomRsrcAllocList[k2Index].startSymbol;
1328 endSymbol = startSymbol+ timeDomRsrcAllocList[k2Index].symbolLength;
1329 dlSymbolPresent = false;
1330 for(checkSymbol= startSymbol; checkSymbol<endSymbol; checkSymbol++)
1332 currentSymbol = cell->cellCfg.tddCfg.slotCfg[k2TmpVal][checkSymbol];
1333 if(currentSymbol == DL_SLOT || currentSymbol == FLEXI_SLOT)
1335 dlSymbolPresent = true;
1340 /* Store all the values if all condition satisfies. */
1341 if(dlSymbolPresent != true || slotCfg == UL_SLOT)
1343 numK2 = k2InfoTbl->k2TimingInfo[slotIdx].numK2;
1344 k2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[numK2] = k2Index;
1345 k2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1351 msg3Delta = puschDeltaTable[cell->cellCfg.numerology];
1353 /* Check for K2 for MSG3 */
1354 /* Current slot + k2 should be either UL or FLEXI slot.
1355 * If slot is FLEXI then check all the symbols of that slot,
1356 * it should not contain any DL or FLEXI slot */
1357 msg3K2TmpVal = (slotIdx + k2Val + msg3Delta) % totalCfgSlot;
1358 slotCfg = schGetSlotSymbFrmt(msg3K2TmpVal, cell->slotFrmtBitMap);
1359 if(slotCfg != DL_SLOT)
1361 if(slotCfg == FLEXI_SLOT)
1363 startSymbol = timeDomRsrcAllocList[k2Index].startSymbol;
1364 endSymbol = startSymbol+ timeDomRsrcAllocList[k2Index].symbolLength;
1365 dlSymbolPresent = false;
1366 for(checkSymbol= startSymbol; checkSymbol<endSymbol; checkSymbol++)
1368 currentSymbol = cell->cellCfg.tddCfg.slotCfg[msg3K2TmpVal][checkSymbol];
1369 if(currentSymbol == DL_SLOT || currentSymbol == FLEXI_SLOT)
1371 dlSymbolPresent = true;
1376 /* Store all the values if all condition satisfies. */
1377 if(dlSymbolPresent != true || slotCfg == UL_SLOT)
1379 numK2 = msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2;
1380 msg3K2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[numK2] = k2Index;
1381 msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1392 /*******************************************************************************************
1394 * @brief Allocate the PRB using RRM policy
1398 * Function : prbAllocUsingRRMPolicy
1401 * [Step1]: Traverse each Node in the LC list
1402 * [Step2]: Check whether the LC has ZERO requirement then clean this LC
1403 * [Step3]: Calcualte the maxPRB for this LC.
1404 * a. For Dedicated LC, maxPRB = sum of remainingReservedPRB and
1406 * b. For Default, just SharedPRB count
1407 * [Step4]: If the LC is the First one to be allocated for this UE then add
1408 * TX_PAYLODN_LEN to reqBO
1409 * [Step5]: Calculate the estimate PRB and estimate BO to be allocated
1410 * based on reqBO and maxPRB left.
1411 * [Step6]: Based on calculated PRB, Update Reserved PRB and Shared PRB counts
1412 * [Step7]: Deduce the reqBO based on allocBO and move the LC node to last.
1413 * [Step8]: Continue the next loop from List->head
1416 * [Exit1]: If all the LCs are allocated in list
1417 * [Exit2]: If PRBs are exhausted
1419 * @params[in] I/P > lcLinkList pointer (LcInfo list)
1420 * I/P > IsDedicatedPRB (Flag to indicate that RESERVED PRB to use
1421 * I/P > mcsIdx and PDSCH symbols count
1422 * I/P & O/P > Shared PRB , reserved PRB Count
1423 * I/P & O/P > Total TBS size accumulated
1424 * I/P & O/P > isTxPayloadLenAdded[For DL] : Decision flag to add the TX_PAYLOAD_HDR_LEN
1425 * I/P & O/P > srRcvd Flag[For UL] : Decision flag to add UL_GRANT_SIZE
1429 * *******************************************************************************************/
1430 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool isDedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
1431 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd)
1433 CmLList *node = NULLP;
1434 LcInfo *lcNode = NULLP;
1435 uint16_t remReservedPRB = 0, estPrb = 0, maxPRB = 0;
1439 DU_LOG("\nERROR --> SCH: LcList not present");
1444 /*Only for Dedicated LcList, Valid value will be assigned to remReservedPRB
1445 * For Other LcList, remReservedPRB = 0*/
1446 if(reservedPRB != NULLP && isDedicatedPRB == TRUE)
1448 remReservedPRB = *reservedPRB;
1455 /*For Debugging purpose*/
1458 lcNode = (LcInfo *)node->node;
1460 /* [Step2]: Below condition will hit in rare case as it has been taken care during the cleaning
1461 * process of LCID which was fully allocated. Check is just for safety purpose*/
1462 if(lcNode->reqBO == 0 && lcNode->allocBO == 0)
1464 DU_LOG("\nERROR --> SCH: LCID:%d has no requirement, clearing this node",\
1466 deleteNodeFromLList(lcLL, node);
1467 SCH_FREE(lcNode, sizeof(LcInfo));
1472 /*[Exit1]: All LCs are allocated(allocBO = 0 for fully unallocated LC)*/
1473 if(lcNode->allocBO != 0)
1475 DU_LOG("\nDEBUG --> SCH: All LC are allocated [SharedPRB:%d]",*sharedPRB);
1479 /*[Exit2]: If PRBs are exhausted*/
1482 /*Loop Exit: All resources exhausted*/
1483 if(remReservedPRB == 0 && *sharedPRB == 0)
1485 DU_LOG("\nDEBUG --> SCH: Dedicated resources exhausted for LC:%d",lcNode->lcId);
1491 /*Loop Exit: All resources exhausted*/
1494 DU_LOG("\nDEBUG --> SCH: Default resources exhausted for LC:%d",lcNode->lcId);
1500 maxPRB = remReservedPRB + *sharedPRB;
1503 if((isTxPayloadLenAdded != NULLP) && (*isTxPayloadLenAdded == FALSE))
1505 DU_LOG("\nDEBUG --> SCH: LC:%d is the First node to be allocated which includes TX_PAYLOAD_HDR_LEN",\
1507 *isTxPayloadLenAdded = TRUE;
1508 lcNode->allocBO = calculateEstimateTBSize((lcNode->reqBO + TX_PAYLOAD_HDR_LEN),\
1509 mcsIdx, numSymbols, maxPRB, &estPrb);
1510 lcNode->allocBO -=TX_PAYLOAD_HDR_LEN;
1512 else if((srRcvd != NULLP) && (*srRcvd == TRUE))
1514 DU_LOG("\nDEBUG --> SCH: LC:%d is the First node to be allocated which includes UL_GRANT_SIZE",\
1517 lcNode->reqBO += UL_GRANT_SIZE;
1518 lcNode->allocBO = calculateEstimateTBSize(lcNode->reqBO, mcsIdx, numSymbols, maxPRB, &estPrb);
1523 lcNode->allocBO = calculateEstimateTBSize(lcNode->reqBO,\
1524 mcsIdx, numSymbols, maxPRB, &estPrb);
1527 /*[Step6]:Re-adjust the reservedPRB pool count and *SharedPRB Count based on
1528 * estimated PRB allocated*/
1529 if((isDedicatedPRB == TRUE) && (estPrb <= remReservedPRB))
1531 remReservedPRB = remReservedPRB - estPrb;
1533 else /*LC requirement need PRB share from SharedPRB*/
1535 if(*sharedPRB <= (estPrb - remReservedPRB))
1537 DU_LOG("\nDEBUG --> SCH: SharedPRB is less");
1542 *sharedPRB = *sharedPRB - (estPrb - remReservedPRB);
1548 lcNode->reqBO -= lcNode->allocBO; /*Update the reqBO with remaining bytes unallocated*/
1549 lcNode->allocPRB = estPrb;
1550 cmLListAdd2Tail(lcLL, cmLListDelFrm(lcLL, node));
1552 /*[Step8]:Next loop: First LC to be picked from the list
1553 * because Allocated Nodes are moved to the last*/
1560 /*******************************************************************************************
1562 * @brief Check the LC List and fill the LC and GrantSize to be sent to MAC as
1567 * Function : updateGrantSizeForBoRpt
1570 * Check the LC List and fill the LC and GrantSize to be sent to MAC as
1571 * BO Report in dlMsgAlloc Pointer
1573 * @params[in] I/P > lcLinkList pointer (LcInfo list)
1574 * I/P & O/P > dlMsgAlloc[for DL](Pending LC to be added in this context)
1575 * I/P & O/P > BsrInfo (applicable for UL)
1576 * I/P & O/P > accumalatedBOSize
1579 * *******************************************************************************************/
1580 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc,\
1581 BsrInfo *bsrInfo, uint32_t *accumalatedBOSize)
1583 CmLList *node = NULLP, *next = NULLP;
1584 LcInfo *lcNode = NULLP;
1585 DlMsgSchInfo *dlMsgSchInfo = NULLP;
1589 DU_LOG("\nERROR --> SCH: LcList not present");
1607 lcNode = (LcInfo *)node->node;
1610 DU_LOG("\nINFO --> SCH : LcID:%d, [reqBO, allocBO, allocPRB]:[%d,%d,%d]",\
1611 lcNode->lcId, lcNode->reqBO, lcNode->allocBO, lcNode->allocPRB);
1612 if(dlMsgAlloc != NULLP)
1614 dlMsgSchInfo = &dlMsgAlloc->dlMsgSchedInfo[dlMsgAlloc->numSchedInfo];
1616 /*Add this LC to dlMsgAlloc so that if this LC gets allocated, BO
1617 * report for allocation can be sent to MAC*/
1618 dlMsgSchInfo->lcSchInfo[dlMsgSchInfo->numLc].lcId = lcNode->lcId;
1619 dlMsgSchInfo->lcSchInfo[dlMsgSchInfo->numLc].schBytes = lcNode->allocBO;
1621 /*Calculate the Total Payload/BO size allocated*/
1622 *accumalatedBOSize += dlMsgSchInfo->lcSchInfo[dlMsgSchInfo->numLc].schBytes;
1624 DU_LOG("\nINFO --> SCH: Added in MAC BO report: LCID:%d,reqBO:%d,Idx:%d, TotalBO Size:%d",\
1625 lcNode->lcId,lcNode->reqBO, dlMsgSchInfo->numLc, *accumalatedBOSize);
1627 dlMsgSchInfo->numLc++;
1628 /*The LC has been fully allocated, clean it*/
1629 if(lcNode->reqBO == 0)
1631 handleLcLList(lcLL, lcNode->lcId, DELETE);
1634 else if(bsrInfo != NULLP)
1636 *accumalatedBOSize += lcNode->allocBO;
1637 DU_LOG("\nINFO --> SCH: UL : LCID:%d,reqBO:%d, TotalBO Size:%d",\
1638 lcNode->lcId,lcNode->reqBO, *accumalatedBOSize);
1646 /*******************************************************************
1648 * @brief fill DL message information for MSG4 and Dedicated DL Msg
1652 * Function : fillDlMsgInfo
1655 * fill DL message information for MSG4 and Dedicated DL Msg
1657 * @params[in] DlMsgInfo *dlMsgInfo, uint8_t crnti
1658 * @params[in] bool isRetx, SchDlHqProcCb *hqP
1661 *******************************************************************/
1662 void fillDlMsgInfo(DlMsgInfo *dlMsgInfo, uint8_t crnti, bool isRetx, SchDlHqProcCb *hqP)
1664 hqP->tbInfo[0].isEnabled = TRUE;
1665 hqP->tbInfo[0].state = HQ_TB_WAITING;
1666 hqP->tbInfo[0].txCntr++;
1667 hqP->tbInfo[1].isEnabled = TRUE;
1668 hqP->tbInfo[1].state = HQ_TB_WAITING;
1669 hqP->tbInfo[1].txCntr++;
1670 dlMsgInfo->crnti = crnti;
1671 dlMsgInfo->ndi = hqP->tbInfo[0].ndi; /*How to handle two tb case?TBD*/
1672 dlMsgInfo->harqProcNum = hqP->procId;
1673 dlMsgInfo->dlAssignIdx = 0;
1674 dlMsgInfo->pucchTpc = 0;
1675 dlMsgInfo->pucchResInd = 0;
1676 dlMsgInfo->harqFeedbackInd = hqP->k1;
1677 dlMsgInfo->dciFormatId = 1;
1680 /*******************************************************************
1682 * @brief sch Process pending Msg4 Req
1686 * Function : schProcessMsg4Req
1689 * sch Process pending Msg4 Req
1691 * @params[in] SchCellCb *cell, cell cb struct pointer
1692 * @params[in] SlotTimingInfo currTime, current timing info
1693 * @params[in] uint8_t ueId, ue ID
1694 * @params[in] bool isRetxMsg4, indicator to MSG4 retransmission
1695 * @params[in] SchDlHqProcCb **msg4HqProc, address of MSG4 HARQ proc pointer
1696 * @return ROK - success
1699 *******************************************************************/
1701 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetxMsg4, SchDlHqProcCb **msg4HqProc)
1703 uint8_t pdschStartSymbol = 0, pdschNumSymbols = 0;
1704 SlotTimingInfo pdcchTime, pdschTime, pucchTime;
1705 DlMsgAlloc *dciSlotAlloc = NULLP; /* Stores info for transmission of PDCCH for Msg4 */
1706 DlMsgAlloc *msg4SlotAlloc = NULLP; /* Stores info for transmission of PDSCH for Msg4 */
1710 DU_LOG("\nERROR --> SCH: schDlRsrcAllocMsg4() : Cell is NULL");
1714 if (isRetxMsg4 == FALSE)
1716 if (RFAILED == schDlGetAvlHqProcess(cell, &cell->ueCb[ueId - 1], msg4HqProc))
1718 DU_LOG("\nERROR --> SCH: schDlRsrcAllocMsg4() : No process");
1723 if(findValidK0K1Value(cell, currTime, ueId, false, &pdschStartSymbol, &pdschNumSymbols, &pdcchTime, &pdschTime,\
1724 &pucchTime, isRetxMsg4, *msg4HqProc) != true )
1726 DU_LOG("\nERROR --> SCH: schDlRsrcAllocMsg4() : k0 k1 not found");
1730 if(cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] == NULL)
1732 SCH_ALLOC(dciSlotAlloc, sizeof(DlMsgAlloc));
1733 if(dciSlotAlloc == NULLP)
1735 DU_LOG("\nERROR --> SCH : Memory Allocation failed for dciSlotAlloc");
1738 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = dciSlotAlloc;
1739 memset(dciSlotAlloc, 0, sizeof(DlMsgAlloc));
1740 GET_CRNTI(dciSlotAlloc->crnti, ueId);
1743 dciSlotAlloc = cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1];
1745 /* Fill PDCCH and PDSCH scheduling information for Msg4 */
1746 if((schDlRsrcAllocMsg4(cell, pdschTime, ueId, dciSlotAlloc, pdschStartSymbol, pdschNumSymbols, isRetxMsg4, *msg4HqProc)) != ROK)
1748 DU_LOG("\nERROR --> SCH: Scheduling of Msg4 failed in slot [%d]", pdschTime.slot);
1749 if(dciSlotAlloc->numSchedInfo == 0)
1751 SCH_FREE(dciSlotAlloc, sizeof(DlMsgAlloc));
1752 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP;
1755 memset(&dciSlotAlloc->dlMsgSchedInfo[dciSlotAlloc->numSchedInfo], 0, sizeof(DlMsgSchInfo));
1759 /* Check if both DCI and RAR are sent in the same slot.
1760 * If not, allocate memory RAR PDSCH slot to store RAR info
1762 if(pdcchTime.slot == pdschTime.slot)
1764 dciSlotAlloc->dlMsgSchedInfo[dciSlotAlloc->numSchedInfo].pduPres = BOTH;
1765 dciSlotAlloc->numSchedInfo++;
1769 /* Allocate memory to schedule rarSlot to send RAR, pointer will be checked at schProcessSlotInd() */
1770 if(cell->schDlSlotInfo[pdschTime.slot]->dlMsgAlloc[ueId-1] == NULL)
1772 SCH_ALLOC(msg4SlotAlloc, sizeof(DlMsgAlloc));
1773 if(msg4SlotAlloc == NULLP)
1775 DU_LOG("\nERROR --> SCH : Memory Allocation failed for msg4SlotAlloc");
1776 if(dciSlotAlloc->numSchedInfo == 0)
1778 SCH_FREE(dciSlotAlloc, sizeof(DlMsgAlloc));
1779 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP;
1782 memset(&dciSlotAlloc->dlMsgSchedInfo[dciSlotAlloc->numSchedInfo], 0, sizeof(DlMsgSchInfo));
1785 cell->schDlSlotInfo[pdschTime.slot]->dlMsgAlloc[ueId-1] = msg4SlotAlloc;
1786 memset(msg4SlotAlloc, 0, sizeof(DlMsgAlloc));
1787 msg4SlotAlloc->crnti = dciSlotAlloc->crnti;
1790 msg4SlotAlloc = cell->schDlSlotInfo[pdschTime.slot]->dlMsgAlloc[ueId-1];
1792 /* Copy all RAR info */
1793 memcpy(&msg4SlotAlloc->dlMsgSchedInfo[msg4SlotAlloc->numSchedInfo], \
1794 &dciSlotAlloc->dlMsgSchedInfo[dciSlotAlloc->numSchedInfo], sizeof(DlMsgSchInfo));
1795 msg4SlotAlloc->dlMsgSchedInfo[msg4SlotAlloc->numSchedInfo].dlMsgPdcchCfg.dci.pdschCfg = \
1796 &msg4SlotAlloc->dlMsgSchedInfo[msg4SlotAlloc->numSchedInfo].dlMsgPdschCfg;
1798 /* Assign correct PDU types in corresponding slots */
1799 msg4SlotAlloc->dlMsgSchedInfo[msg4SlotAlloc->numSchedInfo].pduPres = PDSCH_PDU;
1800 dciSlotAlloc->dlMsgSchedInfo[dciSlotAlloc->numSchedInfo].pduPres = PDCCH_PDU;
1801 dciSlotAlloc->dlMsgSchedInfo[dciSlotAlloc->numSchedInfo].pdschSlot = pdschTime.slot;
1803 dciSlotAlloc->numSchedInfo++;
1804 msg4SlotAlloc->numSchedInfo++;
1807 /* PUCCH resource */
1808 schAllocPucchResource(cell, pucchTime, cell->raCb[ueId-1].tcrnti, &cell->ueCb[ueId-1], isRetxMsg4, *msg4HqProc);
1810 cell->schDlSlotInfo[pdcchTime.slot]->pdcchUe = ueId;
1811 cell->schDlSlotInfo[pdschTime.slot]->pdschUe = ueId;
1812 cell->schUlSlotInfo[pucchTime.slot]->pucchUe = ueId;
1813 cell->raCb[ueId-1].msg4recvd = FALSE;
1816 cell->ueCb[ueId-1].retxMsg4HqProc= NULLP;
1821 /*******************************************************************
1823 * @brief Handler to calculate TBS size for BSR requested
1827 * Function : schCalculateUlTbs
1829 * Functionality: Function will note the required TBS for each LCGIDX and use
1830 * the Priority LCG List and RRM policy to allocate the TBS size
1832 * @params [in] ueCb (Pointer to UE CB)
1833 * [in] puschTime (Time slot where PUSCH will be sent)
1834 * [in] symbLen (No of Symbols used for PUSCH transmission)
1835 * [out] startPrb(Pointer to startPRB which will be calculated while
1836 * finding the best Free Block)
1837 * [out] totTBS(Pointer to total TBS size)
1838 * [in] isRetx (to indicate retransmission)
1839 * [in] hqP (UL Harq process pointer)
1841 * @return uint8_t : ROK > Scheduling of UL grant is successful
1842 * RFAILED > vice versa
1844 * ****************************************************************/
1845 uint8_t schCalculateUlTbs(SchUeCb *ueCb, SlotTimingInfo puschTime, uint8_t symbLen,\
1846 uint16_t *startPrb, uint32_t *totTBS, bool isRetx, SchUlHqProcCb *hqP)
1848 uint16_t mcsIdx = 0;
1849 CmLListCp *lcLL = NULLP;
1850 uint16_t lcgIdx = 0, lcId =0, maxFreePRB = 0;
1851 uint16_t rsvdDedicatedPRB;
1856 for(lcgIdx=0; lcgIdx<MAX_NUM_LOGICAL_CHANNEL_GROUPS; lcgIdx++)
1858 if(ueCb->bsrInfo[lcgIdx].dataVol == 0)
1863 /*TODO: lcgIdx and LCID has been implemented as one to one mapping.
1864 * Need to check the mapping to figure out the LCID and lcgIdx once L2
1865 * spec specifies any logic*/
1867 if(ueCb->ulInfo.ulLcCtxt[lcId].isDedicated)
1869 lcLL = &(hqP->ulLcPrbEst.dedLcList);
1870 rsvdDedicatedPRB = ueCb->ulInfo.ulLcCtxt[lcId].rsvdDedicatedPRB;
1874 lcLL = &(hqP->ulLcPrbEst.defLcList);
1877 /*[Step2]: Update the reqPRB and Payloadsize for this LC in the appropriate List*/
1878 if(updateLcListReqPRB(lcLL, lcId, ueCb->bsrInfo[lcgIdx].dataVol) != ROK)
1880 DU_LOG("\nERROR --> SCH: LcgId:%d updation failed",lcId);
1885 if ((hqP->ulLcPrbEst.defLcList.count == 0) && (hqP->ulLcPrbEst.dedLcList.count == 0))
1887 if( (ueCb->srRcvd) || (isRetx) )
1889 *startPrb = MAX_NUM_RB;
1890 *totTBS = schCalcTbSize(UL_GRANT_SIZE);
1892 /*Returning true when NO Grant is there for UE as this is not scheduling
1897 maxFreePRB = searchLargestFreeBlock(ueCb->cellCb, puschTime, startPrb, DIR_UL);
1899 /*[Step4]: Estimation of PRB and BO which can be allocated to each LC in
1900 * the list based on RRM policy*/
1902 /*Either this UE contains no reservedPRB pool fir dedicated S-NSSAI or
1903 * Num of Free PRB available is not enough to reserve Dedicated PRBs*/
1906 mcsIdx = ueCb->ueCfg.ulModInfo.mcsIndex;
1907 if((hqP->ulLcPrbEst.dedLcList.count == 0) || ((maxFreePRB < rsvdDedicatedPRB)))
1909 hqP->ulLcPrbEst.sharedNumPrb = maxFreePRB;
1910 DU_LOG("\nDEBUG --> SCH : UL Only Default Slice is scheduled, sharedPRB Count:%d",\
1911 hqP->ulLcPrbEst.sharedNumPrb);
1913 /*PRB Alloc for Default LCs*/
1914 prbAllocUsingRRMPolicy(&(hqP->ulLcPrbEst.defLcList), FALSE, mcsIdx, symbLen,\
1915 &(hqP->ulLcPrbEst.sharedNumPrb), NULLP, NULLP,&(ueCb->srRcvd));
1919 hqP->ulLcPrbEst.sharedNumPrb = maxFreePRB - rsvdDedicatedPRB;
1921 /*PRB Alloc for Dedicated LCs*/
1922 prbAllocUsingRRMPolicy(&(hqP->ulLcPrbEst.dedLcList), TRUE, mcsIdx, symbLen,\
1923 &(hqP->ulLcPrbEst.sharedNumPrb), &(rsvdDedicatedPRB),\
1924 NULLP,&(ueCb->srRcvd));
1926 /*PRB Alloc for Default LCs*/
1927 prbAllocUsingRRMPolicy(&(hqP->ulLcPrbEst.defLcList), FALSE, mcsIdx, symbLen, \
1928 &(hqP->ulLcPrbEst.sharedNumPrb), &(rsvdDedicatedPRB),\
1929 NULLP,&(ueCb->srRcvd));
1932 /*[Step5]:Traverse each LCID in LcList to calculate the exact Scheduled Bytes
1933 * using allocated BO per LC and Update dlMsgAlloc(BO report for MAC*/
1934 if(hqP->ulLcPrbEst.dedLcList.count != 0)
1935 updateGrantSizeForBoRpt(&(hqP->ulLcPrbEst.dedLcList), NULLP, ueCb->bsrInfo, totTBS);
1937 updateGrantSizeForBoRpt(&(hqP->ulLcPrbEst.defLcList), NULLP, ueCb->bsrInfo, totTBS);
1939 /*Below case will hit if NO LC(s) are allocated due to resource crunch*/
1944 DU_LOG("\nERROR --> SCH : NO FREE PRB!!");
1948 /*Schedule the LC for next slot*/
1949 DU_LOG("\nDEBUG --> SCH : No LC has been scheduled");
1956 /*******************************************************************
1958 * @brief sch Process pending Sr or Bsr Req
1962 * Function : schProcessSrOrBsrReq
1965 * sch Process pending Sr or Bsr Req
1967 * @params[in] SchCellCb *cell, SlotTimingInfo currTime
1968 * @params[in] uint8_t ueId, Bool isRetx, SchUlHqProcCb **hqP
1969 * @return true - success
1972 *******************************************************************/
1973 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP)
1975 bool k2Found = FALSE, ret = RFAILED;
1976 uint8_t startSymb = 0, symbLen = 0;
1977 uint8_t k2TblIdx = 0, k2Index = 0, k2Val = 0;
1978 uint16_t startPrb = 0;
1979 uint32_t totDataReq = 0; /* in bytes */
1981 SchPuschInfo *puschInfo;
1982 DciInfo *dciInfo = NULLP;
1983 SchK2TimingInfoTbl *k2InfoTbl=NULLP;
1984 SlotTimingInfo dciTime, puschTime;
1988 DU_LOG("\nERROR --> SCH: schProcessSrOrBsrReq() : Cell is NULL");
1992 ueCb = &cell->ueCb[ueId-1];
1996 DU_LOG("\nERROR --> SCH: schProcessSrOrBsrReq() : UE is NULL");
2000 if (isRetx == FALSE)
2002 if (schUlGetAvlHqProcess(cell, ueCb, hqP) != ROK)
2008 /* Calculating time frame to send DCI for SR */
2009 ADD_DELTA_TO_TIME(currTime, dciTime, PHY_DELTA_DL + SCHED_DELTA);
2011 if(schGetSlotSymbFrmt(dciTime.slot, cell->slotFrmtBitMap) == DL_SLOT)
2014 if(ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.k2TblPrsnt)
2015 k2InfoTbl = &ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.k2InfoTbl;
2017 k2InfoTbl = &cell->cellCfg.schInitialUlBwp.k2InfoTbl;
2019 for(k2TblIdx = 0; k2TblIdx < k2InfoTbl->k2TimingInfo[dciTime.slot].numK2; k2TblIdx++)
2021 k2Index = k2InfoTbl->k2TimingInfo[dciTime.slot].k2Indexes[k2TblIdx];
2023 if(!ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.k2TblPrsnt)
2025 k2Val = cell->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].k2;
2026 startSymb = cell->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].startSymbol;
2027 symbLen = cell->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].symbolLength;
2031 k2Val = ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.puschCfg.timeDomRsrcAllocList[k2Index].k2;
2032 startSymb = ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.puschCfg.timeDomRsrcAllocList[k2Index].startSymbol;
2033 symbLen = ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.puschCfg.timeDomRsrcAllocList[k2Index].symbolLength;
2035 /* Check for number of Symbol of PUSCH should be same as original in case of transmisson*/
2036 /* Calculating time frame to send PUSCH for SR */
2037 ADD_DELTA_TO_TIME(dciTime, puschTime, k2Val);
2039 if(schGetSlotSymbFrmt(puschTime.slot, cell->slotFrmtBitMap) == DL_SLOT)
2042 if(cell->schUlSlotInfo[puschTime.slot]->puschUe != 0)
2053 ret = schCalculateUlTbs(ueCb, puschTime, symbLen, &startPrb, &totDataReq, isRetx, *hqP);
2055 if(totDataReq > 0 && ret == ROK)
2057 SCH_ALLOC(dciInfo, sizeof(DciInfo));
2060 DU_LOG("\nERROR --> SCH : Memory Allocation failed for dciInfo alloc");
2063 if((*hqP)->ulLcPrbEst.dedLcList.count != 0)
2064 updateBsrAndLcList(&((*hqP)->ulLcPrbEst.dedLcList), ueCb->bsrInfo, RFAILED);
2066 updateBsrAndLcList(&((*hqP)->ulLcPrbEst.defLcList), ueCb->bsrInfo, RFAILED);
2070 cell->schDlSlotInfo[dciTime.slot]->ulGrant = dciInfo;
2071 memset(dciInfo,0,sizeof(DciInfo));
2073 /* Update PUSCH allocation */
2074 if(schFillPuschAlloc(ueCb, puschTime, totDataReq, startSymb, symbLen, startPrb, isRetx, *hqP) == ROK)
2076 if(cell->schUlSlotInfo[puschTime.slot]->schPuschInfo)
2078 puschInfo = cell->schUlSlotInfo[puschTime.slot]->schPuschInfo;
2079 if(puschInfo != NULLP)
2081 /* Fill DCI for UL grant */
2082 schFillUlDci(ueCb, puschInfo, dciInfo, isRetx, *hqP);
2083 memcpy(&dciInfo->slotIndInfo, &dciTime, sizeof(SlotTimingInfo));
2084 ueCb->srRcvd = false;
2085 ueCb->bsrRcvd = false;
2086 cell->schUlSlotInfo[puschTime.slot]->puschUe = ueId;
2087 if((*hqP)->ulLcPrbEst.dedLcList.count != 0)
2088 updateBsrAndLcList(&((*hqP)->ulLcPrbEst.dedLcList), ueCb->bsrInfo, ROK);
2089 updateBsrAndLcList(&((*hqP)->ulLcPrbEst.defLcList), ueCb->bsrInfo, ROK);
2090 cmLListAdd2Tail(&(ueCb->hqUlmap[puschTime.slot]->hqList), &(*hqP)->ulSlotLnk);
2095 if((*hqP)->ulLcPrbEst.dedLcList.count != 0)
2096 updateBsrAndLcList(&((*hqP)->ulLcPrbEst.dedLcList), ueCb->bsrInfo, RFAILED);
2097 updateBsrAndLcList(&((*hqP)->ulLcPrbEst.defLcList), ueCb->bsrInfo, RFAILED);
2104 /*******************************************************************
2106 * @brief sch Process pending Sr or Bsr Req
2110 * Function : updateBsrAndLcList
2113 * Updating the BSRInfo in UECB and Lclist
2115 * @params[in] SchCellCb *cell, SlotTimingInfo currTime
2116 * @return ROK - success
2119 *******************************************************************/
2120 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status)
2122 CmLList *node = NULLP, *next = NULLP;
2123 LcInfo *lcNode = NULLP;
2127 DU_LOG("\nERROR --> SCH: LcList not present");
2144 lcNode = (LcInfo *)node->node;
2147 /*Only when Status is OK then allocation is marked as ZERO and reqBO
2148 * is updated in UE's DB. If Failure, then allocation is added to reqBO
2149 * and same is updated in Ue's DB inside BSR Info structure*/
2152 lcNode->allocBO = 0;
2155 lcNode->reqBO += lcNode->allocBO;
2156 bsrInfo[lcNode->lcId].dataVol = lcNode->reqBO;
2157 if(lcNode->reqBO == 0)
2159 handleLcLList(lcLL, lcNode->lcId, DELETE);
2166 /********************************************************************************
2168 * @brief Increment the Slot by a input factor
2172 * Function : schIncrSlot
2175 * Increment the slot by a input factor till num of Slots configured in a
2176 * Radio Frame. If it exceeds, move to next sfn.
2178 * @params[in/out] SlotTimingInfo timingInfo
2179 * [in] uint8_t incr [Increment factor]
2180 * [in] numSlotsPerRF [Number of Slots configured per RF as per
2182 * @return ROK - success
2185 *******************************************************************/
2186 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF)
2188 timingInfo->slot += incr;
2189 if(timingInfo->slot >= numSlotsPerRF)
2191 timingInfo->sfn += timingInfo->slot/numSlotsPerRF;
2192 timingInfo->slot %= numSlotsPerRF;
2193 if(timingInfo->sfn > MAX_SFN)
2195 timingInfo->sfn %= MAX_SFN;
2200 /*******************************************************************
2202 * @brief Fill PDSCH info in Page Alloc
2206 * Function : schFillPagePdschCfg
2208 * Functionality: Fill PDSCH info in Page Alloc
2210 * @params[in] SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingInfo slotTime,
2211 * uint16_t tbsSize, uint8_t mcs, uint16_t startPrb
2213 * @return pointer to return Value(ROK, RFAILED)
2215 * ****************************************************************/
2216 uint8_t schFillPagePdschCfg(SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingInfo slotTime, uint16_t tbSize, uint8_t mcs, uint16_t startPrb)
2218 uint8_t cwCount = 0;
2219 uint8_t dmrsStartSymbol, startSymbol, numSymbol;
2221 /* fill the PDSCH PDU */
2223 pagePdschCfg->pduBitmap = 0; /* PTRS and CBG params are excluded */
2224 pagePdschCfg->rnti = P_RNTI; /* SI-RNTI */
2225 pagePdschCfg->pduIndex = 0;
2226 pagePdschCfg->numCodewords = 1;
2227 for(cwCount = 0; cwCount < pagePdschCfg->numCodewords; cwCount++)
2229 pagePdschCfg->codeword[cwCount].targetCodeRate = 308;
2230 pagePdschCfg->codeword[cwCount].qamModOrder = 2;
2231 pagePdschCfg->codeword[cwCount].mcsIndex = mcs;
2232 pagePdschCfg->codeword[cwCount].mcsTable = 0; /* notqam256 */
2233 pagePdschCfg->codeword[cwCount].rvIndex = 0;
2234 tbSize = tbSize + TX_PAYLOAD_HDR_LEN;
2235 pagePdschCfg->codeword[cwCount].tbSize = tbSize;
2237 pagePdschCfg->dataScramblingId = cell->cellCfg.phyCellId;
2238 pagePdschCfg->numLayers = 1;
2239 pagePdschCfg->transmissionScheme = 0;
2240 pagePdschCfg->refPoint = 0;
2241 pagePdschCfg->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
2242 pagePdschCfg->dmrs.dmrsConfigType = 0; /* type-1 */
2243 pagePdschCfg->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
2244 pagePdschCfg->dmrs.scid = 0;
2245 pagePdschCfg->dmrs.numDmrsCdmGrpsNoData = 1;
2246 pagePdschCfg->dmrs.dmrsPorts = 0x0001;
2247 pagePdschCfg->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
2248 pagePdschCfg->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
2249 pagePdschCfg->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
2251 pagePdschCfg->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
2252 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
2253 pagePdschCfg->pdschFreqAlloc.freqAlloc.startPrb = startPrb;
2254 pagePdschCfg->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, NUM_PDSCH_SYMBOL);
2255 pagePdschCfg->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
2256 pagePdschCfg->pdschTimeAlloc.rowIndex = 1;
2257 /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */
2258 pagePdschCfg->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
2259 pagePdschCfg->pdschTimeAlloc.timeAlloc.numSymb = NUM_PDSCH_SYMBOL;
2261 /* Find total symbols occupied including DMRS */
2262 dmrsStartSymbol = findDmrsStartSymbol(pagePdschCfg->dmrs.dlDmrsSymbPos);
2263 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
2264 * in that case only PDSCH symbols are marked as occupied */
2265 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
2267 startSymbol = pagePdschCfg->pdschTimeAlloc.timeAlloc.startSymb;
2268 numSymbol = pagePdschCfg->pdschTimeAlloc.timeAlloc.numSymb;
2270 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
2273 startSymbol = dmrsStartSymbol;
2274 numSymbol = pagePdschCfg->dmrs.nrOfDmrsSymbols + pagePdschCfg->pdschTimeAlloc.timeAlloc.numSymb;
2277 /* Allocate the number of PRBs required for DL PDSCH */
2278 if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol,\
2279 &pagePdschCfg->pdschFreqAlloc.freqAlloc.startPrb, pagePdschCfg->pdschFreqAlloc.freqAlloc.numPrb)) != ROK)
2281 DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for DL MSG");
2285 pagePdschCfg->beamPdschInfo.numPrgs = 1;
2286 pagePdschCfg->beamPdschInfo.prgSize = 1;
2287 pagePdschCfg->beamPdschInfo.digBfInterfaces = 0;
2288 pagePdschCfg->beamPdschInfo.prg[0].pmIdx = 0;
2289 pagePdschCfg->beamPdschInfo.prg[0].beamIdx[0] = 0;
2290 pagePdschCfg->txPdschPower.powerControlOffset = 0;
2291 pagePdschCfg->txPdschPower.powerControlOffsetSS = 0;
2296 /**********************************************************************
2298 **********************************************************************/