1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
34 #include "common_def.h"
41 #include "du_app_mac_inf.h"
42 #include "mac_sch_interface.h"
45 #include "sch_utils.h"
48 * @brief common resource allocation for SSB
52 * Function : schBroadcastSsbAlloc
54 * This function handles common scheduling for SSB
56 * @param[in] SchCellCb *cell, cell cb
57 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
60 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc)
63 uint8_t ssbStartSymb, idx;
65 SchDlSlotInfo *schDlSlotInfo;
70 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : Cell is NULL");
74 if(dlBrdcstAlloc == NULL)
76 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : dlBrdcstAlloc is NULL");
80 schDlSlotInfo = cell->schDlSlotInfo[slotTime.slot];
81 ssbStartPrb = cell->cellCfg.ssbSubcOffset; //+Kssb
82 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are supporting only 1 ssb beam */
84 /* Assign interface structure */
85 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
88 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
89 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
90 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
91 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
92 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
93 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
96 if((allocatePrbDl(cell, slotTime, ssbStartSymb, SCH_SSB_NUM_SYMB, &ssbInfo.fdAlloc.startPrb, ssbInfo.fdAlloc.numPrb)) != ROK)
98 DU_LOG("\nERROR --> SCH: PRB allocation failed for SSB in SFN:SLOT [%d : %d]", slotTime.sfn, slotTime.slot);
103 schDlSlotInfo->ssbPres = true;
104 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
109 * @brief common resource allocation for SIB1
113 * Function : schBroadcastSib1Alloc
115 * This function handles common scheduling for SIB1
117 * @param[in] SchCellCb *cell, cell cb
118 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
121 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc)
123 uint8_t dmrsStartSymbol, startSymbol, numSymbol ;
125 PdschFreqAlloc freqAlloc;
126 PdschTimeAlloc timeAlloc;
127 SchDlSlotInfo *schDlSlotInfo = NULLP;
131 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : Cell is NULL");
135 if(dlBrdcstAlloc == NULL)
137 DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : dlBrdcstAlloc is NULL");
141 dlBrdcstAlloc->crnti = SI_RNTI;
142 dmrs = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.dmrs;
143 freqAlloc = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc;
144 timeAlloc = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschTimeAlloc;
145 schDlSlotInfo = cell->schDlSlotInfo[slotTime.slot];
147 /* Find total symbols used including DMRS */
148 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
149 * in that case only PDSCH symbols are marked as occupied */
150 dmrsStartSymbol = findDmrsStartSymbol(dmrs.dlDmrsSymbPos);
151 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
153 startSymbol = timeAlloc.startSymb;
154 numSymbol = timeAlloc.numSymb;
156 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
159 startSymbol = dmrsStartSymbol;
160 numSymbol = dmrs.nrOfDmrsSymbols + timeAlloc.numSymb;
164 if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol, &freqAlloc.startPrb, freqAlloc.numPrb)) != ROK)
166 DU_LOG("\nERROR --> SCH: PRB allocation failed for SIB1 in SFN:Slot [%d : %d]", slotTime.sfn, slotTime.slot);
170 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->sib1SchCfg.bwp, sizeof(BwpCfg));
171 SCH_ALLOC(dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg,sizeof(PdcchCfg));
172 if(dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg)
174 memcpy(dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
175 schDlSlotInfo->sib1Pres = true;
179 DU_LOG("\nERROR --> SCH : Memory allocation failed in %s", __func__);
185 /*******************************************************************
187 * @brief Handles sending UL scheduler info to MAC
191 * Function : sendUlSchInfoToMac
194 * Sends UL Sch info to MAC from SCH
197 * @return ROK - success
200 * ****************************************************************/
201 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
205 memset(&pst, 0, sizeof(Pst));
206 FILL_PST_SCH_TO_MAC(pst, inst);
207 pst.event = EVENT_UL_SCH_INFO;
209 return(MacMessageRouter(&pst, (void *)ulSchedInfo));
213 * @brief Function to fill Pucch Format 0
217 * Function : fillPucchFormat0
219 * Function to fill Pucch format 0
221 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
225 void fillPucchFormat0(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
227 if(resrcInfo->SchPucchFormat.format0)
229 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
230 ulSchedPucch->pucchFormat = PUCCH_FORMAT_0;
231 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format0->initialCyclicShift;
232 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format0->numSymbols;
233 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format0->startSymbolIdx;
238 * @brief Function to fill Pucch Format 1
242 * Function : fillPucchFormat1
244 * Function to fill Pucch format 1
246 * @param[in] SchPucchInfo pointer, SchPucchResrcInfo pointer
250 void fillPucchFormat1(SchPucchInfo *ulSchedPucch, SchPucchResrcInfo *resrcInfo)
252 if(resrcInfo->SchPucchFormat.format1)
254 ulSchedPucch->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
255 ulSchedPucch->pucchFormat = PUCCH_FORMAT_1;
256 ulSchedPucch->initialCyclicShift = resrcInfo->SchPucchFormat.format1->initialCyclicShift;
257 ulSchedPucch->tdAlloc.numSymb = resrcInfo->SchPucchFormat.format1->numSymbols;
258 ulSchedPucch->tdAlloc.startSymb = resrcInfo->SchPucchFormat.format1->startSymbolIdx;
259 ulSchedPucch->timeDomOCC = resrcInfo->SchPucchFormat.format1->timeDomOCC;
264 * @brief Function to fill Pucch format for UL Sched Info
268 * Function : fillUlSchedPucchFormat
270 * Function to fill Pucch format for UL Sched Info
272 * @param[in] pucchFormat , SchPucchInfo pointer,
273 * @param[in] SchPucchFormatCfg pointer, SchPucchResrcInfo pointer
277 uint8_t fillUlSchedPucchFormat(uint8_t pucchFormat, SchPucchInfo *ulSchedPucch,\
278 SchPucchResrcInfo *resrcInfo, SchPucchFormatCfg *formatCfg)
287 fillPucchFormat0(ulSchedPucch, resrcInfo);
294 fillPucchFormat1(ulSchedPucch, resrcInfo);
298 ulSchedPucch->addDmrs = formatCfg->addDmrs;
299 ulSchedPucch->pi2BPSK = formatCfg->pi2BPSK;
302 }/* To Add support for more Pucch Format */
305 DU_LOG("\nERROR --> SCH : Invalid PUCCH format[%d] in fillUlSchedPucchFormatCfg()", pucchFormat);
313 * @brief Function to fill Pucch Dedicated Cfg for UL Sched Info
317 * Function : fillUlSchedPucchDedicatedCfg
319 * Function to fill Pucch Dedicated Cfg for UL Sched Info
321 * @param[in] pucchFormat to be filled
322 * @param[in] SchPucchFormatCfg pointer, SchPucchCfg pointer
326 uint8_t fillUlSchedPucchDedicatedCfg(SchCellCb *cell, SchPucchCfg *pucchDedCfg,\
327 SlotTimingInfo *slotInfo, SchPucchInfo *ulSchedPucch)
329 uint8_t ret, resrcSetIdx, resrcIdx, schedReqIdx, srPeriodicity = 0;
330 uint16_t srOffset = 0;
331 uint16_t numSlots = cell->numSlots;
332 bool isAllocated = false;
333 uint16_t pucchStartPrb;
335 if(pucchDedCfg->resrcSet && pucchDedCfg->resrc)
337 //Assuming one entry in the list
338 for(resrcSetIdx = 0; resrcSetIdx < pucchDedCfg->resrcSet->resrcSetToAddModListCount; resrcSetIdx++)
340 for(resrcIdx = 0; resrcIdx < pucchDedCfg->resrc->resrcToAddModListCount; resrcIdx++)
342 if(pucchDedCfg->resrcSet->resrcSetToAddModList[resrcSetIdx].resrcList[resrcSetIdx] ==\
343 pucchDedCfg->resrc->resrcToAddModList[resrcIdx].resrcId)
345 ulSchedPucch->intraFreqHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].intraFreqHop;
346 ulSchedPucch->secondPrbHop = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].secondPrbHop;
347 ulSchedPucch->fdAlloc.startPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
348 ulSchedPucch->pucchFormat = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].pucchFormat;
349 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch,\
350 &pucchDedCfg->resrc->resrcToAddModList[resrcIdx], NULLP);
354 pucchStartPrb = pucchDedCfg->resrc->resrcToAddModList[resrcIdx].startPrb;
355 ret = allocatePrbUl(cell, *slotInfo, ulSchedPucch->tdAlloc.startSymb, ulSchedPucch->tdAlloc.numSymb, &pucchStartPrb, PUCCH_NUM_PRB_FORMAT_0_1_4);
368 if(pucchDedCfg->format1)
370 ret = fillUlSchedPucchFormat(ulSchedPucch->pucchFormat, ulSchedPucch, NULLP, pucchDedCfg->format1);
380 /* setting SR and UCI flag */
381 if(pucchDedCfg->schedReq)
383 for(schedReqIdx = 0; schedReqIdx < pucchDedCfg->schedReq->schedAddModListCount; schedReqIdx++)
385 srPeriodicity = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].periodicity;
386 srOffset = pucchDedCfg->schedReq->schedAddModList[schedReqIdx].offset;
389 if(((numSlots * slotInfo->sfn + slotInfo->slot - srOffset) % srPeriodicity) == 0)
391 ulSchedPucch->srFlag = true;
398 * @brief Function to fill Pucch Resource Info
402 * Function : fillPucchResourceInfo
404 * Function to fill Pucch Resource Info
406 * @param[in] SchPucchInfo *schPucchInfo, Inst inst
407 * @return ROK/RFAILED
410 uint16_t fillPucchResourceInfo(SchCellCb *cell, uint8_t ueId, SchPucchInfo *schPucchInfo, SlotTimingInfo slotInfo,\
411 SchPdcchAllocInfo *pdcchAllocInfo)
413 uint8_t ret = RFAILED, ueIdx = 0, pucchIdx = 0;
414 uint8_t val_pri = 0, r_pucch = 0, cRSetIdx = 0;
415 uint16_t startPrb = 0, n_cce = 0, N_cce = 0;
416 SchPucchCfgCmn *pucchCfg = NULLP;
417 SchBwpDlCfg *initialDlBwp = NULLP;
418 SchBwpUlCfg *initialUlBwp = NULLP;
419 SchUeCb *ueCb = NULLP;
422 ueCb = &(cell->ueCb[ueIdx]);
424 if(ueCb->ueDrxInfoPres)
426 if(!ueCb->drxUeCb.drxUlUeActiveStatus)
430 if(cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellRecfg.initUlBwp.pucchCfgPres)
432 /* fill pucch dedicated cfg */
433 ret = fillUlSchedPucchDedicatedCfg(cell,\
434 &cell->ueCb[ueIdx].ueCfg.spCellCfg.servCellRecfg.initUlBwp.pucchCfg, &slotInfo, schPucchInfo);
437 memset(schPucchInfo, 0, sizeof(SchPucchInfo));
438 DU_LOG("\nERROR --> SCH : Filling PUCCH dedicated cfg failed at fillPucchResourceInfo()");
444 /* fill pucch common cfg */
445 pucchCfg = &cell->cellCfg.ulCfgCommon.schInitialUlBwp.pucchCommon;
446 pucchIdx = pucchCfg->pucchResourceCommon;
447 initialUlBwp = &cell->cellCfg.ulCfgCommon.schInitialUlBwp;
449 /*As per Spec 38.213, Sec 9.2.1, StartPrb is determined by by DCI and PDCCH CCE location
450 * N_cce = Num of CCEs in COreset used for PDCCH
451 * n_cce = first index of CCE used for PDCCH
452 * val_pri = PUCCH resource indicator field in DCI format 1_0/1_1*/
453 /* derive pucchResourceSet from schCellCfg */
454 if(pdcchAllocInfo != NULLP)
456 for(cRSetIdx = 0; cRSetIdx < MAX_NUM_CRSET; cRSetIdx++ )
458 if(ueCb->pdcchInfo[cRSetIdx].cRSetRef->cRSetId == pdcchAllocInfo->cRSetId)
460 N_cce = ueCb->pdcchInfo[cRSetIdx].totalCceCount;
464 n_cce = pdcchAllocInfo->cceIndex;
468 initialDlBwp = &cell->cellCfg.dlCfgCommon.schInitialDlBwp;
469 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
470 N_cce = coresetIdxTable[initialDlBwp->pdcchCommon.commonSearchSpace.coresetId][1] * \
471 coresetIdxTable[initialDlBwp->pdcchCommon.commonSearchSpace.coresetId][2];
472 n_cce = 4;/*As per current Implementation, default value of cceIndex for CORESET0 is 4*/
474 val_pri = PUCCH_RES_IND;
476 /*Following calculation are derived from Spec 38.213, Sec 9.2.1*/
477 r_pucch = (floor((2 * n_cce)/N_cce)) + (2 * val_pri);
479 if((floor(r_pucch/8)) == 0)
481 startPrb = pucchResourceSet[pucchIdx][3] + (floor(r_pucch/pucchResourceSet[pucchIdx][4]));
483 else if((floor(r_pucch/8)) == 1)
485 startPrb = initialUlBwp->bwp.freqAlloc.numPrb - 1 - pucchResourceSet[pucchIdx][3] - \
486 (floor((r_pucch - 8)/pucchResourceSet[pucchIdx][4]));
490 DU_LOG("\nERROR --> SCH: Invalid value of r_pucch:%d (greater than 15) ", r_pucch);
493 ret = allocatePrbUl(cell, slotInfo, pucchResourceSet[pucchIdx][1], pucchResourceSet[pucchIdx][2],\
494 &startPrb, PUCCH_NUM_PRB_FORMAT_0_1_4);
497 schPucchInfo->fdAlloc.startPrb = startPrb;
498 schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0_1_4;
499 schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
500 schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
501 schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
503 /* set SR and UCI flag to false */
504 schPucchInfo->srFlag = true;
511 * @brief resource allocation for UL
515 * Function : schUlResAlloc
517 * This function handles UL Resource allocation
519 * @param[in] SchCellCb *cell, cellCb
522 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
528 UlSchedInfo ulSchedInfo;
529 SchUlSlotInfo *schUlSlotInfo = NULLP;
530 SlotTimingInfo ulTimingInfo;
531 CmLList *node = NULLP;
532 TotalPrbUsage *ulTotalPrbUsage = NULLP;
534 memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
537 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA_UL+SCHED_DELTA, cell->numSlots);
539 ulSchedInfo.cellId = cell->cellId;
540 ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
541 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
542 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
544 /* Schedule resources for PRACH */
545 if(cell->firstSib1Transmitted)
546 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
548 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
549 if(schUlSlotInfo->schPuschInfo)
551 GET_CRNTI(ulSchedInfo.crnti, schUlSlotInfo->puschUe);
552 /* Check the ue drx status if the UE is active for uplink scheduling or not */
554 ueCb = schGetUeCb(cell, ulSchedInfo.crnti);
555 if(ueCb->ueDrxInfoPres)
557 if(!ueCb->drxUeCb.drxUlUeActiveStatus)
561 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
562 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
563 sizeof(SchPuschInfo));
564 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
565 schUlSlotInfo->schPuschInfo = NULL;
568 if(schUlSlotInfo->pucchPres)
570 GET_CRNTI(ulSchedInfo.crnti, schUlSlotInfo->pucchUe);
571 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
572 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
573 sizeof(SchPucchInfo));
574 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
577 /* Send msg to MAC */
578 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
581 DU_LOG("\nERROR --> SCH : Sending UL Sch info from SCH to MAC failed");
584 /* Update DL PRB Usage for all stats group which requested for DL Total PRB Usage */
585 node = cmLListFirst(&schCb[schInst].statistics.activeKpiList.ulTotPrbUseList);
588 ulTotalPrbUsage = (TotalPrbUsage *)node->node;
589 ulTotalPrbUsage->numPrbUsedForTx += schUlSlotInfo->prbAlloc.numPrbAlloc;
590 ulTotalPrbUsage->totalPrbAvailForTx += MAX_NUM_RB;
594 /* Re-initialize UL Slot */
595 schInitUlSlot(schUlSlotInfo);
599 /*******************************************************************
601 * @brief Fills pdcch and pdsch info for msg4
605 * Function : schDlRsrcAllocMsg4
608 * Fills pdcch and pdsch info for msg4
610 * @params[in] SchCellCb *cell, SlotTimingInfo msg4Time
611 * @params[in] uint8_t ueId, DlMsgSchInfo *dlMsgAlloc
612 * @params[in] uint8_t pdschStartSymbol, uint8_t pdschNumSymbols
613 * @params[in] bool isRetx, SchDlHqProcCb *hqP
614 * @return ROK - success
617 * ****************************************************************/
618 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgSchInfo *dlMsgAlloc,\
619 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP)
621 uint8_t coreset0Idx = 0;
622 uint8_t firstSymbol = 0;
623 uint8_t numSymbols = 0;
624 uint8_t mcs = DEFAULT_MCS; /* MCS fixed to 4 */
625 uint8_t dmrsStartSymbol = 0, startSymbol = 0, numSymbol = 0;
628 SchBwpDlCfg *initialBwp = NULLP;
629 PdcchCfg *pdcch = NULLP;
630 PdschCfg *pdsch = NULLP;
632 DlMsgSchInfo *msg4Alloc = NULLP;
636 DU_LOG("\nERROR --> SCH: schDlRsrcAllocMsg4() : Cell is NULL");
640 if(dlMsgAlloc == NULL)
642 DU_LOG("\nERROR --> SCH: schDlRsrcAllocMsg4() : dlMsgAlloc is NULL");
646 msg4Alloc = dlMsgAlloc;
647 initialBwp = &cell->cellCfg.dlCfgCommon.schInitialDlBwp;
648 SCH_ALLOC(msg4Alloc->dlMsgPdcchCfg, sizeof(PdcchCfg));
650 if(!msg4Alloc->dlMsgPdcchCfg)
652 DU_LOG("\nERROR --> SCH : Memory allocation failed in %s",__func__);
655 pdcch = msg4Alloc->dlMsgPdcchCfg;
656 bwp = &msg4Alloc->bwp;
657 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
659 fillDlMsgInfo(msg4Alloc, cell->raCb[ueId-1].tcrnti, isRetx, hqP);
660 msg4Alloc->dlMsgPduLen = cell->raCb[ueId-1].dlMsgPduLen;
662 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
663 numRbs = coresetIdxTable[coreset0Idx][1];
664 numSymbols = coresetIdxTable[coreset0Idx][2];
666 /* calculate time domain parameters */
667 uint16_t mask = 0x2000;
668 for(firstSymbol=0; firstSymbol<MAX_SYMB_PER_SLOT; firstSymbol++)
670 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
677 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
678 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
679 bwp->subcarrierSpacing = initialBwp->bwp.scs;
680 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
682 /* fill the PDCCH PDU */
683 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
684 pdcch->coresetCfg.durationSymbols = numSymbols;
685 memcpy(pdcch->coresetCfg.freqDomainResource, \
686 cell->cellCfg.dlCfgCommon.schInitialDlBwp.pdcchCommon.commonSearchSpace.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
688 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
689 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
690 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
691 pdcch->coresetCfg.coreSetType = 0;
692 pdcch->coresetCfg.coreSetSize = numRbs;
693 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
694 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
696 pdcch->dci[0].rnti = cell->raCb[ueId-1].tcrnti;
697 pdcch->dci[0].scramblingId = cell->cellCfg.phyCellId;
698 pdcch->dci[0].scramblingRnti = 0;
699 pdcch->dci[0].cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
700 pdcch->dci[0].aggregLevel = 4;
701 pdcch->dci[0].beamPdcchInfo.numPrgs = 1;
702 pdcch->dci[0].beamPdcchInfo.prgSize = 1;
703 pdcch->dci[0].beamPdcchInfo.digBfInterfaces = 0;
704 pdcch->dci[0].beamPdcchInfo.prg[0].pmIdx = 0;
705 pdcch->dci[0].beamPdcchInfo.prg[0].beamIdx[0] = 0;
706 pdcch->dci[0].txPdcchPower.beta_pdcch_1_0 = 0;
707 pdcch->dci[0].txPdcchPower.powerControlOffsetSS = 0;
708 pdsch = &pdcch->dci[0].pdschCfg;
710 /* fill the PDSCH PDU */
712 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
713 pdsch->rnti = cell->raCb[ueId-1].tcrnti;
715 pdsch->numCodewords = 1;
716 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
718 pdsch->codeword[cwCount].targetCodeRate = 308;
719 pdsch->codeword[cwCount].qamModOrder = 2;
720 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
721 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
724 tbSize = schCalcTbSize(msg4Alloc->dlMsgPduLen + TX_PAYLOAD_HDR_LEN); /* MSG4 size + FAPI header size*/
725 hqP->tbInfo[cwCount].tbSzReq = tbSize;
726 pdsch->codeword[cwCount].rvIndex = 0;
730 pdsch->codeword[cwCount].rvIndex = (pdsch->codeword[cwCount].rvIndex +1) & 0x03;
731 tbSize = hqP->tbInfo[cwCount].tbSzReq;
733 pdsch->codeword[cwCount].tbSize = tbSize;
735 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
736 pdsch->numLayers = 1;
737 pdsch->transmissionScheme = 0;
739 pdsch->dmrs.dlDmrsSymbPos = DL_DMRS_SYMBOL_POS;
740 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
741 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
742 pdsch->dmrs.scid = 0;
743 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
744 pdsch->dmrs.dmrsPorts = 0;
745 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
746 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
747 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
749 pdsch->pdschTimeAlloc.startSymb = pdschStartSymbol;
750 pdsch->pdschTimeAlloc.numSymb = pdschNumSymbols;
752 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
753 pdsch->pdschFreqAlloc.startPrb = MAX_NUM_RB;
754 pdsch->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, pdschNumSymbols);
755 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
757 /* Find total symbols occupied including DMRS */
758 dmrsStartSymbol = findDmrsStartSymbol(pdsch->dmrs.dlDmrsSymbPos);
759 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
760 * in that case only PDSCH symbols are marked as occupied */
761 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
763 startSymbol = pdsch->pdschTimeAlloc.startSymb;
764 numSymbol = pdsch->pdschTimeAlloc.numSymb;
766 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
769 startSymbol = dmrsStartSymbol;
770 numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.numSymb;
773 /* Allocate the number of PRBs required for RAR PDSCH */
774 if((allocatePrbDl(cell, msg4Time, startSymbol, numSymbol,\
775 &pdsch->pdschFreqAlloc.startPrb, pdsch->pdschFreqAlloc.numPrb)) != ROK)
777 DU_LOG("\nERROR --> SCH : Resource allocation failed for MSG4");
778 SCH_FREE(msg4Alloc->dlMsgPdcchCfg, sizeof(PdcchCfg));
782 pdsch->beamPdschInfo.numPrgs = 1;
783 pdsch->beamPdschInfo.prgSize = 1;
784 pdsch->beamPdschInfo.digBfInterfaces = 0;
785 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
786 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
787 pdsch->txPdschPower.powerControlOffset = 0;
788 pdsch->txPdschPower.powerControlOffsetSS = 0;
793 /*******************************************************************
795 * @brief Scheduling for Pucch Resource
799 * Function : schAllocPucchResource
802 * Scheduling for Pucch Resource
804 * @params[in] SchCellCb *cell, SlotTimingInfo pucchTime, crnti
805 * @params[in] SchUeCb *ueCb, SchDlHqProcCb *hqP, SchPdcchAllocInfo *pdcchAllocInfo
806 * @return ROK - success
809 *******************************************************************/
811 uint8_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, SchUeCb *ueCb,\
812 SchDlHqProcCb *hqP, SchPdcchAllocInfo *pdcchAllocInfo)
814 uint8_t ret = RFAILED;
815 uint16_t pucchSlot = 0;
816 SchUlSlotInfo *schUlSlotInfo = NULLP;
818 pucchSlot = pucchTime.slot;
819 schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
820 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
822 ret = fillPucchResourceInfo(cell, schUlSlotInfo->pucchUe, &schUlSlotInfo->schPucchInfo,\
823 pucchTime, pdcchAllocInfo);
829 schUlSlotInfo->pucchPres = true;
833 /* set HARQ flag to true */
834 schUlSlotInfo->schPucchInfo.harqInfo.harqBitLength = 1; /* 1 bit for HARQ */
835 ADD_DELTA_TO_TIME(pucchTime, pucchTime, 3, cell->numSlots); /* SLOT_DELAY=3 */
836 cmLListAdd2Tail(&(ueCb->hqDlmap[pucchTime.slot]->hqList), &hqP->dlSlotLnk);
841 /*******************************************************************
843 * @brief Fills pdcch and pdsch info for dedicated DL msg
847 * Function : schDlRsrcAllocDlMsg
850 * Fills pdcch and pdsch info for dl msg
852 * @params[in] SchCellCb *cell, SlotTimingInfo slotTime
853 * @params[in] uint16_t crnti, uint32_t tbSize
854 * @params[in] DlMsgSchInfo *dlMsgAlloc, uint16_t startPRB
855 * @params[in] uint8_t pdschStartSymbol, uint8_t pdschNumSymbols
856 * @params[in] bool isRetx, SchDlHqProcCb *hqP
857 * @return ROK - success
860 * ****************************************************************/
861 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
862 uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol,
863 uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP, SchPdcchAllocInfo pdcchAllocInfo)
865 uint8_t ueId=0, ssIdx = 0, cRSetIdx = 0;;
866 uint8_t cwCount = 0, rbgCount = 0, pdcchStartSymbol = 0;
867 PdcchCfg *pdcch = NULLP;
868 PdschCfg *pdsch = NULLP;
871 SchControlRsrcSet coreset1;
872 SchSearchSpace searchSpace;
873 SchPdschConfig pdschCfg;
874 uint8_t dmrsStartSymbol, startSymbol, numSymbol;
876 SCH_ALLOC(dlMsgAlloc->dlMsgPdcchCfg, sizeof(PdcchCfg));
877 if(!dlMsgAlloc->dlMsgPdcchCfg)
879 DU_LOG("\nERROR --> SCH : Memory allocation failed in schDlRsrcAllocDlMsg");
882 pdcch = dlMsgAlloc->dlMsgPdcchCfg;
883 bwp = &dlMsgAlloc->bwp;
885 GET_UE_ID(crnti, ueId);
886 ueCb = cell->ueCb[ueId-1];
888 for(cRSetIdx = 0; cRSetIdx < ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.numCRsetToAddMod; cRSetIdx++)
890 if(ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.cRSetToAddModList[cRSetIdx].cRSetId\
891 == pdcchAllocInfo.cRSetId)
893 coreset1 = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.cRSetToAddModList[cRSetIdx];
897 for(ssIdx = 0; ssIdx < ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.numSearchSpcToAddMod; ssIdx++)
899 if(ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.searchSpcToAddModList[ssIdx].searchSpaceId\
900 == pdcchAllocInfo.ssId)
902 searchSpace = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.searchSpcToAddModList[ssIdx];
906 pdschCfg = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdschCfg;
909 bwp->freqAlloc.numPrb = MAX_NUM_RB;
910 bwp->freqAlloc.startPrb = 0;
911 bwp->subcarrierSpacing = cell->sib1SchCfg.bwp.subcarrierSpacing;
912 bwp->cyclicPrefix = cell->sib1SchCfg.bwp.cyclicPrefix;
914 /* fill the PDCCH PDU */
915 /*StartSymbol of PDCCH*/
916 pdcchStartSymbol = findSsStartSymbol(searchSpace.mSymbolsWithinSlot);
917 if(pdcchStartSymbol < MAX_SYMB_PER_SLOT)
918 pdcch->coresetCfg.startSymbolIndex = pdcchStartSymbol;
921 DU_LOG("\nERROR --> SCH : Invalid SymbolIndex in schDlRsrcAllocDlMsg");
924 pdcch->coresetCfg.durationSymbols = coreset1.duration;
925 memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
926 pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
927 pdcch->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
928 pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
929 pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
931 /*Size of coreset: Number of PRBs in a coreset*/
932 rbgCount = countRBGFrmCoresetFreqRsrc(coreset1.freqDomainRsrc);
935 pdcch->coresetCfg.coreSetSize = ((rbgCount) * NUM_PRBS_PER_RBG);
939 DU_LOG("\nERROR --> SCH : CORESETSize is zero in schDlRsrcAllocDlMsg");
943 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
944 pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
945 if(pdcch->numDlDci >= MAX_NUM_PDCCH)
947 DU_LOG("\nERROR --> SCH: MAX number of PDCCH allocted for this slot.");
950 pdcch->dci[pdcch->numDlDci].rnti = ueCb.crnti;
951 pdcch->dci[pdcch->numDlDci].scramblingId = cell->cellCfg.phyCellId;
952 pdcch->dci[pdcch->numDlDci].scramblingRnti = 0;
954 /*TODO below assumptions of CCE Index is wrong:
955 * Range 0 to 135 as per ORAN.WG8.AAD Table 9-35 CORESET configuration and
956 * it has to be calculated using the formula given in 3GPP TS 38.213, Sec 10.1 */
957 pdcch->dci[pdcch->numDlDci].cceIndex = pdcchAllocInfo.cceIndex;
958 pdcch->dci[pdcch->numDlDci].aggregLevel = pdcchAllocInfo.aggLvl;
959 pdcch->dci[pdcch->numDlDci].beamPdcchInfo.numPrgs = 1;
960 pdcch->dci[pdcch->numDlDci].beamPdcchInfo.prgSize = 1;
961 pdcch->dci[pdcch->numDlDci].beamPdcchInfo.digBfInterfaces = 0;
962 pdcch->dci[pdcch->numDlDci].beamPdcchInfo.prg[0].pmIdx = 0;
963 pdcch->dci[pdcch->numDlDci].beamPdcchInfo.prg[0].beamIdx[0] = 0;
964 pdcch->dci[pdcch->numDlDci].txPdcchPower.beta_pdcch_1_0 = 0;
965 pdcch->dci[pdcch->numDlDci].txPdcchPower.powerControlOffsetSS = 0;
967 pdsch = &pdcch->dci[pdcch->numDlDci].pdschCfg;
970 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
971 pdsch->rnti = ueCb.crnti;
973 pdsch->numCodewords = 1;
974 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
976 pdsch->codeword[cwCount].targetCodeRate = 308;
977 pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
978 pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
979 pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
980 pdsch->codeword[cwCount].rvIndex = 0;
984 tbSize +=TX_PAYLOAD_HDR_LEN;
985 hqP->tbInfo[cwCount].tbSzReq = tbSize;
987 pdsch->codeword[cwCount].tbSize = tbSize;
989 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
990 pdsch->numLayers = 1;
991 pdsch->transmissionScheme = 0;
993 pdsch->dmrs.dlDmrsSymbPos = DL_DMRS_SYMBOL_POS;
994 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
995 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
996 pdsch->dmrs.scid = 0;
997 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
998 pdsch->dmrs.dmrsPorts = 0;
999 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
1000 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
1001 pdsch->dmrs.dmrsAddPos = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
1003 pdsch->pdschTimeAlloc.startSymb = pdschStartSymbol;
1004 pdsch->pdschTimeAlloc.numSymb = pdschNumSymbols;
1006 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
1007 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
1008 pdsch->pdschFreqAlloc.startPrb = startPRB; /*Start PRB will be already known*/
1009 pdsch->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, pdschNumSymbols);
1011 /* Find total symbols occupied including DMRS */
1012 dmrsStartSymbol = findDmrsStartSymbol(pdsch->dmrs.dlDmrsSymbPos);
1013 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
1014 * in that case only PDSCH symbols are marked as occupied */
1015 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
1017 startSymbol = pdsch->pdschTimeAlloc.startSymb;
1018 numSymbol = pdsch->pdschTimeAlloc.numSymb;
1020 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
1023 startSymbol = dmrsStartSymbol;
1024 numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.numSymb;
1027 /* Allocate the number of PRBs required for DL PDSCH */
1028 if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol,\
1029 &pdsch->pdschFreqAlloc.startPrb, pdsch->pdschFreqAlloc.numPrb)) != ROK)
1031 DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for DL MSG");
1032 SCH_FREE(dlMsgAlloc->dlMsgPdcchCfg, sizeof(PdcchCfg));
1036 pdsch->beamPdschInfo.numPrgs = 1;
1037 pdsch->beamPdschInfo.prgSize = 1;
1038 pdsch->beamPdschInfo.digBfInterfaces = 0;
1039 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
1040 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
1041 pdsch->txPdschPower.powerControlOffset = 0;
1042 pdsch->txPdschPower.powerControlOffsetSS = 0;
1047 /*******************************************************************
1049 * @brief Fills k0 and k1 information table for FDD
1053 * Function : BuildK0K1TableForFdd
1056 * Fills k0 and k1 information table for FDD
1058 * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool
1059 * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc
1060 * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc
1061 * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl
1062 * @return ROK - success
1065 * ****************************************************************/
1066 void BuildK0K1TableForFdd(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres,SchPdschCfgCmn pdschCmnCfg,\
1067 SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl)
1070 uint8_t k1TmpVal =0, cfgIdx=0;
1071 uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, numTimeDomAlloc=0;
1073 /* TODO Commented these below lines for resolving warnings. Presently these variable are not
1074 * required but this will require for harq processing */
1075 // uint8_t k0TmpVal = 0;
1076 // SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
1077 // SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
1079 /* Initialization the structure and storing the total slot values. */
1080 memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl));
1081 k0K1InfoTbl->tblSize = cell->numSlots;
1083 /* Storing time domain resource allocation list based on common or dedicated configuration. */
1084 if(pdschCfgCmnPres == true)
1086 numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc;
1087 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1089 /*TODO uncomment this line during harq processing */
1090 //cmnTimeDomRsrcAllocList[cfgIdx] = pdschCmnCfg.timeDomRsrcAllocList[cfgIdx];
1095 numTimeDomAlloc = pdschDedCfg.numTimeDomRsrcAlloc;
1096 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1098 /*TODO uncomment this line during harq processing */
1099 //dedTimeDomRsrcAllocList[cfgIdx] = pdschDedCfg.timeDomRsrcAllociList[cfgIdx];
1103 /* Checking all the slots for K0 and K1 values. */
1104 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1107 /* Storing the values of k0 based on time domain resource
1108 * allocation list. If the value is unavailable then fill default values,
1109 * As per 38.331 PDSCH-TimeDomainResourceAllocation field descriptions. */
1110 for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++)
1112 /* TODO These if 0 we will remove during harq processing */
1114 if(pdschCfgCmnPres == true)
1116 k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0;
1120 if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP)
1122 k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0);
1126 k0TmpVal = DEFAULT_K0_VALUE;
1130 /* Checking all the Ul Alloc values. If value is less than MIN_NUM_K1_IDX
1131 * then skip else continue storing the values. */
1133 for(k1Index = 0; k1Index < ulAckListCount; k1Index++)
1135 k1TmpVal = UlAckTbl[k1Index];
1136 if(k1TmpVal <= MIN_NUM_K1_IDX)
1141 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index;
1142 /* TODO Store K1 index where harq feedback will be received in harq table. */
1146 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1;
1147 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index;
1153 k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0;
1158 /*******************************************************************
1160 * @brief Fills k0 and k1 information table
1164 * Function : BuildK0K1Table
1167 * Fills K0 and k1 information table
1169 * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool
1170 * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc
1171 * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc
1172 * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl
1173 * @return ROK - success
1176 * ****************************************************************/
1177 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, SchPdschCfgCmn pdschCmnCfg,\
1178 SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl)
1183 bool ulSlotPresent = false;
1184 uint8_t k0TmpVal = 0, k1TmpVal =0, tmpSlot=0, startSymbol=0, endSymbol=0, checkSymbol=0;
1185 uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, cfgIdx=0, numTimeDomAlloc =0, totalCfgSlot =0;
1186 SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
1187 SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC];
1190 if(cell->cellCfg.dupMode == DUPLEX_MODE_FDD)
1192 BuildK0K1TableForFdd(cell, k0K1InfoTbl, pdschCfgCmnPres, pdschCmnCfg, pdschDedCfg, ulAckListCount, UlAckTbl);
1198 /* Initialization the K0K1 structure, total num of slot and calculating the slot pattern length. */
1199 memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl));
1200 k0K1InfoTbl->tblSize = cell->numSlots;
1201 totalCfgSlot = calculateSlotPatternLength(cell->cellCfg.ssbScs, cell->cellCfg.tddCfg.tddPeriod);
1203 /* Storing time domain resource allocation list based on common or
1204 * dedicated configuration availability. */
1205 if(pdschCfgCmnPres == true)
1207 numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc;
1208 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1210 cmnTimeDomRsrcAllocList[cfgIdx] = pdschCmnCfg.timeDomRsrcAllocList[cfgIdx];
1215 numTimeDomAlloc = pdschDedCfg.numTimeDomRsrcAlloc;
1216 for(cfgIdx = 0; cfgIdx<numTimeDomAlloc; cfgIdx++)
1218 dedTimeDomRsrcAllocList[cfgIdx] = pdschDedCfg.timeDomRsrcAllociList[cfgIdx];
1222 /* Checking all possible indexes for K0 and K1 values. */
1223 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1225 /* If current slot is UL or FLEXI then Skip because PDCCH is sent only in DL slots. */
1226 slotCfg = schGetSlotSymbFrmt(slotIdx%totalCfgSlot, cell->slotFrmtBitMap);
1227 if(slotCfg == UL_SLOT || slotCfg == FLEXI_SLOT)
1232 ulSlotPresent = false;
1233 /* Storing K0 , start symbol and length symbol for further processing.
1234 * If K0 value is not available then we can fill the default values
1235 * given in spec 38.331. */
1237 for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++)
1239 if(pdschCfgCmnPres == true)
1241 k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0;
1242 startSymbol = cmnTimeDomRsrcAllocList[k0Index].startSymbol;
1243 endSymbol = startSymbol + cmnTimeDomRsrcAllocList[k0Index].lengthSymbol;
1247 if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP)
1249 k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0);
1253 k0TmpVal = DEFAULT_K0_VALUE;
1255 startSymbol = dedTimeDomRsrcAllocList[k0Index].startSymbol;
1256 endSymbol = startSymbol + dedTimeDomRsrcAllocList[k0Index].symbolLength;
1259 /* If current slot + k0 is UL then skip the slot
1260 * else if it is DL slot then continue the next steps
1261 * else if it is a FLEXI slot then check symbols of slot, It should not
1262 * contain any UL slot. */
1263 tmpSlot = (slotIdx+k0TmpVal) % totalCfgSlot;
1264 slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap);
1265 if(slotCfg == UL_SLOT)
1269 if(slotCfg == FLEXI_SLOT)
1271 for(checkSymbol = startSymbol; checkSymbol<endSymbol; checkSymbol ++)
1273 slotCfg = cell->slotCfg[tmpSlot][checkSymbol];
1274 if(slotCfg == UL_SLOT)
1276 ulSlotPresent = true;
1280 if(ulSlotPresent == true)
1286 ulSlotPresent = false; //Re-initializing
1288 /* If current slot + k0 + k1 is a DL slot then skip the slot
1289 * else if it is UL slot then store the information
1290 * else if it is FLEXI slot then check the symbols, it must have
1291 * at least one UL symbol. */
1293 for(k1Index = 0; k1Index < ulAckListCount; k1Index++)
1295 k1TmpVal = UlAckTbl[k1Index];
1296 if(k1TmpVal > MIN_NUM_K1_IDX)
1298 tmpSlot = (slotIdx+k0TmpVal+k1TmpVal) % totalCfgSlot;
1299 slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap);
1300 if(slotCfg == DL_SLOT)
1304 if(slotCfg == FLEXI_SLOT)
1306 for(checkSymbol = 0; checkSymbol< MAX_SYMB_PER_SLOT;checkSymbol++)
1308 if(cell->slotCfg[tmpSlot][checkSymbol] == UL_SYMBOL)
1310 ulSlotPresent = true;
1315 if(ulSlotPresent == true || slotCfg == UL_SLOT)
1317 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index;
1318 /* TODO Store K1 index where harq feedback will be received
1324 /* Store all the values if all condition satisfies. */
1327 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1;
1328 k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index;
1334 k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0;
1341 /*******************************************************************
1343 * @brief Fills K2 information table for FDD
1347 * Function : BuildK2InfoTableForFdd
1350 * Fills K2 information table for FDD
1352 * @params[in] SchCellCb *cell,SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[],
1353 * uint16_t puschSymTblSize,SchK2TimingInfoTbl *k2InfoTbl
1354 * @return ROK - success
1357 * ****************************************************************/
1358 void BuildK2InfoTableForFdd(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], uint16_t puschSymTblSize,\
1359 SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl)
1361 uint16_t slotIdx=0, k2Index=0, k2TmpIdx=0, msg3K2TmpIdx=0;
1363 /* Initialization the structure and storing the total slot values. */
1364 memset(k2InfoTbl, 0, sizeof(SchK2TimingInfoTbl));
1365 k2InfoTbl->tblSize = cell->numSlots;
1367 msg3K2InfoTbl->tblSize = cell->numSlots;
1369 /* Checking all possible indexes for K2. */
1370 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1372 /* Storing K2 values. */
1373 for(k2Index = 0; ((k2Index < puschSymTblSize) && (k2Index < MAX_NUM_K2_IDX)); k2Index++)
1375 k2TmpIdx= k2InfoTbl->k2TimingInfo[slotIdx].numK2;
1376 k2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[k2TmpIdx] = k2Index;
1377 k2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1379 /* Updating K2 values for MSG3 */
1382 msg3K2TmpIdx = msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2;
1383 msg3K2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[msg3K2TmpIdx] = k2Index;
1384 msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1390 /*******************************************************************
1392 * @brief Fills K2 information table
1396 * Function : BuildK2InfoTable
1399 * Fills K2 information table
1401 * @params[in] SchCellCb *cell,SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[],
1402 * uint16_t puschSymTblSize, SchK2TimingInfoTbl *k2InfoTbl
1403 * @return ROK - success
1406 * ****************************************************************/
1407 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], uint16_t puschSymTblSize,\
1408 SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl)
1412 bool dlSymbolPresent = false;
1413 uint8_t slotIdx=0, k2Index=0, k2Val=0, k2TmpVal=0, msg3K2TmpVal=0, msg3Delta=0, numK2 =0, currentSymbol =0;
1414 uint8_t startSymbol =0, endSymbol =0, checkSymbol=0, totalCfgSlot=0, slotCfg=0;
1415 SlotConfig currentSlot;
1418 if(cell->cellCfg.dupMode == DUPLEX_MODE_FDD)
1420 BuildK2InfoTableForFdd(cell, timeDomRsrcAllocList, puschSymTblSize, msg3K2InfoTbl, k2InfoTbl);
1426 /* Initialization the structure and storing the total slot values. */
1427 memset(k2InfoTbl, 0, sizeof(SchK2TimingInfoTbl));
1428 k2InfoTbl->tblSize = cell->numSlots;
1430 msg3K2InfoTbl->tblSize = cell->numSlots;
1431 totalCfgSlot = calculateSlotPatternLength(cell->cellCfg.ssbScs, cell->cellCfg.tddCfg.tddPeriod);
1433 /* Checking all possible indexes for K2. */
1434 for(slotIdx = 0; slotIdx < cell->numSlots; slotIdx++)
1436 currentSlot = schGetSlotSymbFrmt(slotIdx % totalCfgSlot, cell->slotFrmtBitMap);
1438 /* If current slot is UL then skip because PDCCH is sent only in DL slots */
1439 if(currentSlot != UL_SLOT)
1441 for(k2Index = 0; ((k2Index < puschSymTblSize) && (k2Index < MAX_NUM_K2_IDX)); k2Index++)
1443 /* Storing k2, startSymbol, endSymbol information for further processing.
1444 * If k2 is absent then fill the default values given in spec 38.331
1445 * PUSCH-TimeDomainResourceAllocationList field descriptions */
1446 k2Val = timeDomRsrcAllocList[k2Index].k2;
1449 switch(cell->cellCfg.ssbScs)
1452 k2Val = DEFAULT_K2_VALUE_FOR_SCS15;
1455 k2Val = DEFAULT_K2_VALUE_FOR_SCS30;
1458 k2Val = DEFAULT_K2_VALUE_FOR_SCS60;
1461 k2Val = DEFAULT_K2_VALUE_FOR_SCS120;
1466 /* Current slot + k2 should be either UL or FLEXI slot.
1467 * If slot is FLEXI then check all the symbols of that slot,
1468 * it should not contain any DL or FLEXI slot */
1469 k2TmpVal = (slotIdx + k2Val) % totalCfgSlot;
1470 slotCfg = schGetSlotSymbFrmt(k2TmpVal, cell->slotFrmtBitMap);
1471 if(slotCfg != DL_SLOT)
1473 if(slotCfg == FLEXI_SLOT)
1475 startSymbol = timeDomRsrcAllocList[k2Index].startSymbol;
1476 endSymbol = startSymbol+ timeDomRsrcAllocList[k2Index].symbolLength;
1477 dlSymbolPresent = false;
1478 for(checkSymbol= startSymbol; checkSymbol<endSymbol; checkSymbol++)
1480 currentSymbol = cell->slotCfg[k2TmpVal][checkSymbol];
1481 if(currentSymbol == DL_SLOT || currentSymbol == FLEXI_SLOT)
1483 dlSymbolPresent = true;
1488 /* Store all the values if all condition satisfies. */
1489 if(dlSymbolPresent != true || slotCfg == UL_SLOT)
1491 numK2 = k2InfoTbl->k2TimingInfo[slotIdx].numK2;
1492 k2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[numK2] = k2Index;
1493 k2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1499 msg3Delta = puschDeltaTable[cell->numerology];
1501 /* Check for K2 for MSG3 */
1502 /* Current slot + k2 should be either UL or FLEXI slot.
1503 * If slot is FLEXI then check all the symbols of that slot,
1504 * it should not contain any DL or FLEXI slot */
1505 msg3K2TmpVal = (slotIdx + k2Val + msg3Delta) % totalCfgSlot;
1506 slotCfg = schGetSlotSymbFrmt(msg3K2TmpVal, cell->slotFrmtBitMap);
1507 if(slotCfg != DL_SLOT)
1509 if(slotCfg == FLEXI_SLOT)
1511 startSymbol = timeDomRsrcAllocList[k2Index].startSymbol;
1512 endSymbol = startSymbol+ timeDomRsrcAllocList[k2Index].symbolLength;
1513 dlSymbolPresent = false;
1514 for(checkSymbol= startSymbol; checkSymbol<endSymbol; checkSymbol++)
1516 currentSymbol = cell->slotCfg[msg3K2TmpVal][checkSymbol];
1517 if(currentSymbol == DL_SLOT || currentSymbol == FLEXI_SLOT)
1519 dlSymbolPresent = true;
1524 /* Store all the values if all condition satisfies. */
1525 if(dlSymbolPresent != true || slotCfg == UL_SLOT)
1527 numK2 = msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2;
1528 msg3K2InfoTbl->k2TimingInfo[slotIdx].k2Indexes[numK2] = k2Index;
1529 msg3K2InfoTbl->k2TimingInfo[slotIdx].numK2++;
1540 /*******************************************************************************************
1542 * @brief Allocate the PRB using RRM policy
1546 * Function : prbAllocUsingRRMPolicy
1549 * [Step1]: Traverse each Node in the LC list
1550 * [Step2]: Check whether the LC has ZERO requirement then clean this LC
1551 * [Step3]: Calcualte the maxPRB for this LC.
1552 * a. For Dedicated LC, maxPRB = sum of remainingReservedPRB and
1554 * b. For Default, just SharedPRB count
1555 * [Step4]: If the LC is the First one to be allocated for this UE then add
1556 * TX_PAYLODN_LEN to reqBO
1557 * [Step5]: Calculate the estimate PRB and estimate BO to be allocated
1558 * based on reqBO and maxPRB left.
1559 * [Step6]: Based on calculated PRB, Update Reserved PRB and Shared PRB counts
1560 * [Step7]: Deduce the reqBO based on allocBO and move the LC node to last.
1561 * [Step8]: Continue the next loop from List->head
1564 * [Exit1]: If all the LCs are allocated in list
1565 * [Exit2]: If PRBs are exhausted
1567 * @params[in] I/P > lcLinkList pointer (LcInfo list)
1568 * I/P > IsDedicatedPRB (Flag to indicate that RESERVED PRB to use
1569 * I/P > mcsIdx and PDSCH symbols count
1570 * I/P & O/P > Shared PRB , reserved PRB Count
1571 * I/P & O/P > Total TBS size accumulated
1572 * I/P & O/P > isTxPayloadLenAdded[For DL] : Decision flag to add the TX_PAYLOAD_HDR_LEN
1573 * I/P & O/P > srRcvd Flag[For UL] : Decision flag to add UL_GRANT_SIZE
1577 * *******************************************************************************************/
1578 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool isDedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
1579 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd)
1581 CmLList *node = NULLP;
1582 LcInfo *lcNode = NULLP;
1583 uint16_t remReservedPRB = 0, estPrb = 0, maxPRB = 0;
1587 DU_LOG("\nERROR --> SCH: LcList not present");
1592 /*Only for Dedicated LcList, Valid value will be assigned to remReservedPRB
1593 * For Other LcList, remReservedPRB = 0*/
1594 if(reservedPRB != NULLP && isDedicatedPRB == TRUE)
1596 remReservedPRB = *reservedPRB;
1603 /*For Debugging purpose*/
1606 lcNode = (LcInfo *)node->node;
1608 /* [Step2]: Below condition will hit in rare case as it has been taken care during the cleaning
1609 * process of LCID which was fully allocated. Check is just for safety purpose*/
1610 if(lcNode->reqBO == 0 && lcNode->allocBO == 0)
1612 DU_LOG("\nERROR --> SCH: LCID:%d has no requirement, clearing this node",\
1614 deleteNodeFromLList(lcLL, node);
1615 SCH_FREE(lcNode, sizeof(LcInfo));
1620 /*[Exit1]: All LCs are allocated(allocBO = 0 for fully unallocated LC)*/
1621 if(lcNode->allocBO != 0)
1623 DU_LOG("\nDEBUG --> SCH: All LC are allocated [SharedPRB:%d]",*sharedPRB);
1627 /*[Exit2]: If PRBs are exhausted*/
1630 /*Loop Exit: All resources exhausted*/
1631 if(remReservedPRB == 0 && *sharedPRB == 0)
1633 DU_LOG("\nDEBUG --> SCH: Dedicated resources exhausted for LC:%d",lcNode->lcId);
1639 /*Loop Exit: All resources exhausted*/
1642 DU_LOG("\nDEBUG --> SCH: Default resources exhausted for LC:%d",lcNode->lcId);
1648 maxPRB = remReservedPRB + *sharedPRB;
1651 if((isTxPayloadLenAdded != NULLP) && (*isTxPayloadLenAdded == FALSE))
1653 DU_LOG("\nDEBUG --> SCH: LC:%d is the First node to be allocated which includes TX_PAYLOAD_HDR_LEN",\
1655 *isTxPayloadLenAdded = TRUE;
1656 lcNode->allocBO = calculateEstimateTBSize((lcNode->reqBO + TX_PAYLOAD_HDR_LEN),\
1657 mcsIdx, numSymbols, maxPRB, &estPrb);
1658 lcNode->allocBO -=TX_PAYLOAD_HDR_LEN;
1660 else if((srRcvd != NULLP) && (*srRcvd == TRUE))
1662 DU_LOG("\nDEBUG --> SCH: LC:%d is the First node to be allocated which includes UL_GRANT_SIZE",\
1665 lcNode->reqBO += UL_GRANT_SIZE;
1666 lcNode->allocBO = calculateEstimateTBSize(lcNode->reqBO, mcsIdx, numSymbols, maxPRB, &estPrb);
1671 lcNode->allocBO = calculateEstimateTBSize(lcNode->reqBO,\
1672 mcsIdx, numSymbols, maxPRB, &estPrb);
1675 /*[Step6]:Re-adjust the reservedPRB pool count and *SharedPRB Count based on
1676 * estimated PRB allocated*/
1677 if((isDedicatedPRB == TRUE) && (estPrb <= remReservedPRB))
1679 remReservedPRB = remReservedPRB - estPrb;
1681 else /*LC requirement need PRB share from SharedPRB*/
1683 if(*sharedPRB <= (estPrb - remReservedPRB))
1685 DU_LOG("\nDEBUG --> SCH: SharedPRB is less");
1690 *sharedPRB = *sharedPRB - (estPrb - remReservedPRB);
1696 lcNode->reqBO -= lcNode->allocBO; /*Update the reqBO with remaining bytes unallocated*/
1697 lcNode->allocPRB = estPrb;
1698 cmLListAdd2Tail(lcLL, cmLListDelFrm(lcLL, node));
1700 /*[Step8]:Next loop: First LC to be picked from the list
1701 * because Allocated Nodes are moved to the last*/
1708 /*******************************************************************************************
1710 * @brief Check the LC List and fill the LC and GrantSize to be sent to MAC as
1715 * Function : updateGrantSizeForBoRpt
1718 * Check the LC List and fill the LC and GrantSize to be sent to MAC as
1719 * BO Report in dlMsgAlloc Pointer
1721 * @params[in] I/P > lcLinkList pointer (LcInfo list)
1722 * I/P & O/P > dlMsgAlloc[for DL](Pending LC to be added in this context)
1723 * I/P & O/P > BsrInfo (applicable for UL)
1724 * I/P & O/P > accumalatedBOSize
1727 * *******************************************************************************************/
1728 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgSchInfo *dlMsgAlloc,\
1729 BsrInfo *bsrInfo, uint32_t *accumalatedBOSize)
1731 CmLList *node = NULLP, *next = NULLP;
1732 LcInfo *lcNode = NULLP;
1736 DU_LOG("\nERROR --> SCH: LcList not present");
1754 lcNode = (LcInfo *)node->node;
1757 DU_LOG("\nINFO --> SCH : LcID:%d, [reqBO, allocBO, allocPRB]:[%d,%d,%d]",\
1758 lcNode->lcId, lcNode->reqBO, lcNode->allocBO, lcNode->allocPRB);
1759 if(dlMsgAlloc != NULLP)
1762 /*Add this LC to dlMsgAlloc so that if this LC gets allocated, BO
1763 * report for allocation can be sent to MAC*/
1764 dlMsgAlloc->numOfTbs = 1;
1765 dlMsgAlloc->transportBlock[0].lcSchInfo[dlMsgAlloc->transportBlock[0].numLc].lcId = lcNode->lcId;
1766 dlMsgAlloc->transportBlock[0].lcSchInfo[dlMsgAlloc->transportBlock[0].numLc].schBytes = lcNode->allocBO;
1768 /*Calculate the Total Payload/BO size allocated*/
1769 *accumalatedBOSize += dlMsgAlloc->transportBlock[0].lcSchInfo[dlMsgAlloc->transportBlock[0].numLc].schBytes;
1771 DU_LOG("\nINFO --> SCH: Added in MAC BO report: LCID:%d,reqBO:%d,Idx:%d, TotalBO Size:%d",\
1772 lcNode->lcId,lcNode->reqBO, dlMsgAlloc->transportBlock[0].numLc, *accumalatedBOSize);
1774 dlMsgAlloc->transportBlock[0].numLc++;
1775 handleLcLList(lcLL, lcNode->lcId, DELETE);
1777 else if(bsrInfo != NULLP)
1779 *accumalatedBOSize += lcNode->allocBO;
1780 DU_LOG("\nINFO --> SCH: UL : LCID:%d,reqBO:%d, TotalBO Size:%d",\
1781 lcNode->lcId,lcNode->reqBO, *accumalatedBOSize);
1789 /*******************************************************************
1791 * @brief fill DL message information for MSG4 and Dedicated DL Msg
1795 * Function : fillDlMsgInfo
1798 * fill DL message information for MSG4 and Dedicated DL Msg
1800 * @params[in] DlMsgInfo *dlMsgInfo, uint16_t crnti
1801 * @params[in] bool isRetx, SchDlHqProcCb *hqP
1804 *******************************************************************/
1805 void fillDlMsgInfo(DlMsgSchInfo *dlMsgSchInfo, uint16_t crnti, bool isRetx, SchDlHqProcCb *hqP)
1807 hqP->tbInfo[0].isEnabled = TRUE;
1808 hqP->tbInfo[0].state = HQ_TB_WAITING;
1809 hqP->tbInfo[0].txCntr++;
1810 hqP->tbInfo[1].isEnabled = TRUE;
1811 hqP->tbInfo[1].state = HQ_TB_WAITING;
1812 hqP->tbInfo[1].txCntr++;
1813 dlMsgSchInfo->crnti = crnti;
1814 dlMsgSchInfo->transportBlock[0].ndi = hqP->tbInfo[0].ndi; /*How to handle two tb case?TBD*/
1815 dlMsgSchInfo->harqProcNum = hqP->procId;
1816 dlMsgSchInfo->dlAssignIdx = 0;
1817 dlMsgSchInfo->pucchTpc = 0;
1818 dlMsgSchInfo->pucchResInd = PUCCH_RES_IND;
1819 dlMsgSchInfo->harqFeedbackInd = hqP->k1;
1820 dlMsgSchInfo->dciFormatId = 1;
1823 /*******************************************************************
1825 * @brief sch Process pending Msg4 Req
1829 * Function : schProcessMsg4Req
1832 * sch Process pending Msg4 Req
1834 * @params[in] SchCellCb *cell, cell cb struct pointer
1835 * @params[in] SlotTimingInfo currTime, current timing info
1836 * @params[in] uint8_t ueId, ue ID
1837 * @params[in] bool isRetxMsg4, indicator to MSG4 retransmission
1838 * @params[in] SchDlHqProcCb **msg4HqProc, address of MSG4 HARQ proc pointer
1839 * @return ROK - success
1842 *******************************************************************/
1844 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetxMsg4, SchDlHqProcCb **msg4HqProc)
1846 uint8_t pdschStartSymbol = 0, pdschNumSymbols = 0;
1847 SlotTimingInfo pdcchTime, pdschTime, pucchTime;
1848 DlMsgSchInfo *dciSlotAlloc = NULLP; /* Stores info for transmission of PDCCH for Msg4 */
1849 DlMsgSchInfo *msg4SlotAlloc = NULLP; /* Stores info for transmission of PDSCH for Msg4 */
1853 DU_LOG("\nERROR --> SCH: schProcessMsg4Req() : Cell is NULL");
1857 if (isRetxMsg4 == FALSE)
1859 if (RFAILED == schDlGetAvlHqProcess(cell, &cell->ueCb[ueId - 1], msg4HqProc))
1861 DU_LOG("\nERROR --> SCH: schProcessMsg4Req() : No process");
1866 if(findValidK0K1Value(cell, currTime, ueId, false, &pdschStartSymbol, &pdschNumSymbols, &pdcchTime, &pdschTime,\
1867 &pucchTime, isRetxMsg4, *msg4HqProc, NULLP) != true )
1869 DU_LOG("\nERROR --> SCH: schProcessMsg4Req() : k0 k1 not found");
1873 if(cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] == NULL)
1875 SCH_ALLOC(dciSlotAlloc, sizeof(DlMsgSchInfo));
1876 if(dciSlotAlloc == NULLP)
1878 DU_LOG("\nERROR --> SCH : Memory Allocation failed for dciSlotAlloc");
1881 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = dciSlotAlloc;
1882 memset(dciSlotAlloc, 0, sizeof(DlMsgSchInfo));
1885 dciSlotAlloc = cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1];
1887 /* Fill PDCCH and PDSCH scheduling information for Msg4 */
1888 if((schDlRsrcAllocMsg4(cell, pdschTime, ueId, dciSlotAlloc, pdschStartSymbol, pdschNumSymbols, isRetxMsg4, *msg4HqProc)) != ROK)
1890 DU_LOG("\nERROR --> SCH: Scheduling of Msg4 failed in slot [%d]", pdschTime.slot);
1891 if(!dciSlotAlloc->dlMsgPdschCfg)
1893 SCH_FREE(dciSlotAlloc, sizeof(DlMsgSchInfo));
1894 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP;
1899 /* Check if both DCI and RAR are sent in the same slot.
1900 * If not, allocate memory RAR PDSCH slot to store RAR info
1902 if(pdcchTime.slot == pdschTime.slot)
1904 SCH_ALLOC(dciSlotAlloc->dlMsgPdschCfg, sizeof(PdschCfg));
1905 if(!dciSlotAlloc->dlMsgPdschCfg)
1907 DU_LOG("\nERROR --> SCH : Memory Allocation failed for dciSlotAlloc->dlMsgPdschCfg");
1908 SCH_FREE(dciSlotAlloc->dlMsgPdcchCfg, sizeof(PdcchCfg));
1909 SCH_FREE(dciSlotAlloc, sizeof(DlMsgSchInfo));
1910 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP;
1913 memcpy(dciSlotAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci[0].pdschCfg, sizeof(PdschCfg));
1917 /* Allocate memory to schedule rarSlot to send RAR, pointer will be checked at schProcessSlotInd() */
1918 if(cell->schDlSlotInfo[pdschTime.slot]->dlMsgAlloc[ueId-1] == NULL)
1920 SCH_ALLOC(msg4SlotAlloc, sizeof(DlMsgSchInfo));
1921 if(msg4SlotAlloc == NULLP)
1923 DU_LOG("\nERROR --> SCH : Memory Allocation failed for msg4SlotAlloc");
1924 SCH_FREE(dciSlotAlloc->dlMsgPdcchCfg, sizeof(PdcchCfg));
1925 if(!dciSlotAlloc->dlMsgPdschCfg)
1927 SCH_FREE(dciSlotAlloc, sizeof(DlMsgSchInfo));
1928 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP;
1932 cell->schDlSlotInfo[pdschTime.slot]->dlMsgAlloc[ueId-1] = msg4SlotAlloc;
1933 memset(msg4SlotAlloc, 0, sizeof(DlMsgSchInfo));
1936 msg4SlotAlloc = cell->schDlSlotInfo[pdschTime.slot]->dlMsgAlloc[ueId-1];
1938 /* Copy all msg4 pdschcfg info */
1939 msg4SlotAlloc->crnti =dciSlotAlloc->crnti;
1940 msg4SlotAlloc->bwp = dciSlotAlloc->bwp;
1941 SCH_ALLOC(msg4SlotAlloc->dlMsgPdschCfg, sizeof(PdschCfg));
1942 if(msg4SlotAlloc->dlMsgPdschCfg)
1944 memcpy(msg4SlotAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci[0].pdschCfg, sizeof(PdschCfg));
1948 SCH_FREE(dciSlotAlloc->dlMsgPdcchCfg, sizeof(PdcchCfg));
1949 if(dciSlotAlloc->dlMsgPdschCfg == NULLP)
1951 SCH_FREE(dciSlotAlloc, sizeof(DlMsgSchInfo));
1952 cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP;
1955 SCH_FREE(msg4SlotAlloc, sizeof(DlMsgSchInfo));
1956 cell->schDlSlotInfo[pdschTime.slot]->dlMsgAlloc[ueId-1] = NULLP;
1957 DU_LOG("\nERROR --> SCH : Memory Allocation failed for msg4SlotAlloc->dlMsgPdschCfg");
1962 cell->schDlSlotInfo[pdcchTime.slot]->pdcchUe = ueId;
1963 cell->schUlSlotInfo[pucchTime.slot]->pucchUe = ueId;
1965 cell->raCb[ueId-1].msg4recvd = FALSE;
1968 cell->ueCb[ueId-1].retxMsg4HqProc= NULLP;
1973 /*******************************************************************
1975 * @brief sch Process pending Sr or Bsr Req
1979 * Function : updateBsrAndLcList
1982 * Updating the BSRInfo in UECB and Lclist
1984 * @params[in] SchCellCb *cell, SlotTimingInfo currTime
1985 * @return ROK - success
1988 *******************************************************************/
1989 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status)
1991 CmLList *node = NULLP, *next = NULLP;
1992 LcInfo *lcNode = NULLP;
1996 DU_LOG("\nERROR --> SCH: LcList not present");
2013 lcNode = (LcInfo *)node->node;
2016 /*Only when Status is OK then allocation is marked as ZERO and reqBO
2017 * is updated in UE's DB. If Failure, then allocation is added to reqBO
2018 * and same is updated in Ue's DB inside BSR Info structure*/
2021 lcNode->allocBO = 0;
2024 lcNode->reqBO += lcNode->allocBO;
2025 bsrInfo[lcNode->lcId].dataVol = lcNode->reqBO;
2026 if(lcNode->reqBO == 0)
2028 handleLcLList(lcLL, lcNode->lcId, DELETE);
2035 /*******************************************************************
2037 * @brief sch Process pending Sr or Bsr Req
2041 * Function : schProcessSrOrBsrReq
2044 * sch Process pending Sr or Bsr Req
2046 * @params[in] SchCellCb *cell, SlotTimingInfo currTime
2047 * @params[in] uint8_t ueId, Bool isRetx, SchUlHqProcCb **hqP
2048 * @return true - success
2051 *******************************************************************/
2052 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP)
2054 bool k2Found = FALSE;
2055 uint8_t startSymb = 0, symbLen = 0;
2056 uint8_t k2TblIdx = 0, k2Index = 0, k2Val = 0;
2058 SchK2TimingInfoTbl *k2InfoTbl=NULLP;
2059 SlotTimingInfo dciTime, puschTime;
2063 DU_LOG("\nERROR --> SCH: schProcessSrOrBsrReq() : Cell is NULL");
2067 ueCb = &cell->ueCb[ueId-1];
2071 DU_LOG("\nERROR --> SCH: schProcessSrOrBsrReq() : UE is NULL");
2075 if (isRetx == FALSE)
2077 if (schUlGetAvlHqProcess(cell, ueCb, hqP) != ROK)
2083 /* Calculating time frame to send DCI for SR */
2084 ADD_DELTA_TO_TIME(currTime, dciTime, PHY_DELTA_DL + SCHED_DELTA, cell->numSlots);
2086 if(schGetSlotSymbFrmt(dciTime.slot, cell->slotFrmtBitMap) == DL_SLOT)
2089 if(ueCb->k2TblPrsnt)
2090 k2InfoTbl = &ueCb->k2InfoTbl;
2092 k2InfoTbl = &cell->k2InfoTbl;
2094 for(k2TblIdx = 0; k2TblIdx < k2InfoTbl->k2TimingInfo[dciTime.slot].numK2; k2TblIdx++)
2096 k2Index = k2InfoTbl->k2TimingInfo[dciTime.slot].k2Indexes[k2TblIdx];
2098 if(!ueCb->k2TblPrsnt)
2100 k2Val = cell->cellCfg.ulCfgCommon.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].k2;
2101 startSymb = cell->cellCfg.ulCfgCommon.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].startSymbol;
2102 symbLen = cell->cellCfg.ulCfgCommon.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].symbolLength;
2106 k2Val = ueCb->ueCfg.spCellCfg.servCellRecfg.initUlBwp.puschCfg.timeDomRsrcAllocList[k2Index].k2;
2107 startSymb = ueCb->ueCfg.spCellCfg.servCellRecfg.initUlBwp.puschCfg.timeDomRsrcAllocList[k2Index].startSymbol;
2108 symbLen = ueCb->ueCfg.spCellCfg.servCellRecfg.initUlBwp.puschCfg.timeDomRsrcAllocList[k2Index].symbolLength;
2110 /* Check for number of Symbol of PUSCH should be same as original in case of transmisson*/
2111 /* Calculating time frame to send PUSCH for SR */
2112 ADD_DELTA_TO_TIME(dciTime, puschTime, k2Val, cell->numSlots);
2114 if(schGetSlotSymbFrmt(puschTime.slot, cell->slotFrmtBitMap) == DL_SLOT)
2117 if(cell->schUlSlotInfo[puschTime.slot]->puschUe != 0)
2124 ADD_DELTA_TO_TIME(puschTime, (*hqP)->puschTime, 0, cell->numSlots);
2132 if(cell->api->SchScheduleUlLc(dciTime, puschTime, startSymb, symbLen, isRetx, hqP) != ROK)
2137 DU_LOG("\nDEBUG --> SCH : schProcessSrOrBsrReq(): K2 value is not found");
2143 /********************************************************************************
2145 * @brief Increment the Slot by a input factor
2149 * Function : schIncrSlot
2152 * Increment the slot by a input factor till num of Slots configured in a
2153 * Radio Frame. If it exceeds, move to next sfn.
2155 * @params[in/out] SlotTimingInfo timingInfo
2156 * [in] uint8_t incr [Increment factor]
2157 * [in] numSlotsPerRF [Number of Slots configured per RF as per
2159 * @return ROK - success
2162 *******************************************************************/
2163 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF)
2165 timingInfo->slot += incr;
2166 if(timingInfo->slot >= numSlotsPerRF)
2168 timingInfo->sfn += timingInfo->slot/numSlotsPerRF;
2169 timingInfo->slot %= numSlotsPerRF;
2170 if(timingInfo->sfn > MAX_SFN)
2172 timingInfo->sfn %= MAX_SFN;
2177 /*******************************************************************
2179 * @brief Fill PDSCH info in Page Alloc
2183 * Function : schFillPagePdschCfg
2185 * Functionality: Fill PDSCH info in Page Alloc
2187 * @params[in] SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingInfo slotTime,
2188 * uint16_t tbsSize, uint8_t mcs, uint16_t startPrb
2190 * @return pointer to return Value(ROK, RFAILED)
2192 * ****************************************************************/
2193 uint8_t schFillPagePdschCfg(SchCellCb *cell, PageDlSch *pageDlSch, SlotTimingInfo slotTime, uint16_t tbSize, uint8_t mcs, uint16_t startPrb)
2195 uint8_t dmrsStartSymbol, startSymbol, numSymbol;
2197 /* fill the PDSCH PDU */
2199 pageDlSch->tbInfo.mcs = mcs;
2200 tbSize = tbSize + TX_PAYLOAD_HDR_LEN;
2201 pageDlSch->tbInfo.tbSize = tbSize;
2202 pageDlSch->dmrs.dmrsType = 0; /* type-1 */
2203 pageDlSch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
2204 pageDlSch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
2206 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
2207 pageDlSch->freqAlloc.startPrb = startPrb;
2208 pageDlSch->freqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, NUM_PDSCH_SYMBOL);
2209 pageDlSch->vrbPrbMapping = 0; /* non-interleaved */
2210 /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */
2211 pageDlSch->timeAlloc.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
2212 pageDlSch->timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
2213 pageDlSch->timeAlloc.numSymb = NUM_PDSCH_SYMBOL;
2215 /* Find total symbols occupied including DMRS */
2216 dmrsStartSymbol = findDmrsStartSymbol(4);
2217 /* If there are no DRMS symbols, findDmrsStartSymbol() returns MAX_SYMB_PER_SLOT,
2218 * in that case only PDSCH symbols are marked as occupied */
2219 if(dmrsStartSymbol == MAX_SYMB_PER_SLOT)
2221 startSymbol = pageDlSch->timeAlloc.startSymb;
2222 numSymbol = pageDlSch->timeAlloc.numSymb;
2224 /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */
2227 startSymbol = dmrsStartSymbol;
2228 numSymbol = pageDlSch->dmrs.nrOfDmrsSymbols + pageDlSch->timeAlloc.numSymb;
2231 /* Allocate the number of PRBs required for DL PDSCH */
2232 if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol,\
2233 &pageDlSch->freqAlloc.startPrb, pageDlSch->freqAlloc.numPrb)) != ROK)
2235 DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for DL MSG");
2242 * @brief Handles retransmission for MSG3
2246 * Function : schMsg3RetxSchedulingForUe
2248 * This function handles retransmission for MSG3
2250 * @param[in] SchRaCb *raCb, RA cb pointer
2255 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb)
2257 bool k2Found = false;
2258 uint16_t dciSlot = 0;
2259 SlotTimingInfo dciTime, msg3Time;
2260 SchCellCb *cell = NULLP;
2261 SlotTimingInfo currTime;
2262 DciInfo *dciInfo = NULLP;
2264 currTime = cell->slotInfo;
2266 /* Calculating time frame to send DCI for MSG3 Retx*/
2267 ADD_DELTA_TO_TIME(currTime, dciTime, PHY_DELTA_DL + SCHED_DELTA, cell->numSlots);
2269 /* Consider this slot for sending DCI, only if it is a DL slot */
2270 if(schGetSlotSymbFrmt(dciSlot, raCb->cell->slotFrmtBitMap) == DL_SLOT)
2273 /* If PDCCH is already scheduled on this slot, cannot schedule PDSCH for another UE here. */
2274 if(cell->schDlSlotInfo[dciSlot]->pdcchUe != 0)
2277 k2Found = schGetMsg3K2(cell, &raCb->msg3HqProc, dciTime.slot, &msg3Time, TRUE);
2283 SCH_ALLOC(dciInfo, sizeof(DciInfo));
2286 DU_LOG("\nERROR --> SCH : Memory Allocation failed for dciInfo alloc");
2289 cell->schDlSlotInfo[msg3Time.slot]->ulGrant = dciInfo;
2290 SCH_ALLOC(cell->schUlSlotInfo[msg3Time.slot]->schPuschInfo, sizeof(SchPuschInfo));
2291 memset(dciInfo,0,sizeof(DciInfo));
2292 schFillUlDciForMsg3Retx(raCb, cell->schUlSlotInfo[msg3Time.slot]->schPuschInfo, dciInfo);
2294 raCb->retxMsg3HqProc = NULLP;
2299 * @brief Get K2 value for MSG3
2303 * Function : schGetMsg3K2
2305 * This function gets K2 for MSG3
2307 * @param[in] SchCellCb *cell, Cell cb struc pointer
2308 * @param[in] SchUlHqProcCb* msg3HqProc, msg3 harq proc pointer
2309 * @param[in] uint16_t dlTime, DL time of scheduling
2310 * @param[in] SlotTimingInfo *msg3Time, MSG3 timing info
2311 * @param[in] bool isRetx, indicates MSG3 retransmission
2316 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx)
2318 bool k2Found = false;
2319 uint8_t k2TblIdx = 0;
2320 uint8_t k2Index = 0;
2323 uint8_t puschMu = 0;
2324 uint8_t msg3Delta = 0, msg3MinSchTime = 0;
2326 uint8_t totalCfgSlot = 0;
2328 SchK2TimingInfoTbl *msg3K2InfoTbl=NULLP;
2329 SlotTimingInfo currTime, msg3TempTime;
2330 currTime = cell->slotInfo;
2331 puschMu = cell->numerology;
2338 numK2 = cell->k2InfoTbl.k2TimingInfo[dlTime].numK2;
2339 msg3K2InfoTbl = &cell->msg3K2InfoTbl;
2345 numK2 = cell->msg3K2InfoTbl.k2TimingInfo[dlTime].numK2;
2346 msg3K2InfoTbl = &cell->k2InfoTbl;
2347 msg3MinSchTime = minMsg3SchTime[cell->numerology];
2348 msg3Delta = puschDeltaTable[puschMu];
2351 for(k2TblIdx = 0; k2TblIdx < numK2; k2TblIdx++)
2353 k2Index = msg3K2InfoTbl->k2TimingInfo[dlTime].k2Indexes[k2TblIdx];
2355 k2 = cell->cellCfg.ulCfgCommon.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].k2;
2358 if ((msg3HqProc->strtSymbl != cell->cellCfg.ulCfgCommon.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].startSymbol) ||
2359 (msg3HqProc->numSymbl != cell->cellCfg.ulCfgCommon.schInitialUlBwp.puschCommon.timeDomRsrcAllocList[k2Index].symbolLength))
2364 /* Delta is added to the slot allocation for msg3 based on 38.214 section 6.1.2.1 */
2365 k2 = k2 + msg3Delta;
2366 if(k2 >= msg3MinSchTime)
2368 ADD_DELTA_TO_TIME(currTime, msg3TempTime, k2, cell->numSlots);
2370 if(schGetSlotSymbFrmt(msg3TempTime.slot % totalCfgSlot, cell->slotFrmtBitMap) == DL_SLOT)
2373 /* If PUSCH is already scheduled on this slot, another PUSCH
2374 * pdu cannot be scheduled here */
2375 if(cell->schUlSlotInfo[msg3TempTime.slot]->puschUe != 0)
2381 if (k2Found == true)
2383 msg3Time->slot = msg3TempTime.slot;
2384 msg3Time->sfn = msg3TempTime.sfn;
2385 msg3Time->slot = msg3TempTime.slot;
2391 * * @brief : This Function fills the Coreset and SS info based on PDCCH Cfg received for a UE
2393 * Function : fillUeCoresetAndSsInfo
2395 * For a Coreset, capture the following details which will be used during pdcch allocation
2396 * [Step 1]: Count number of RBG and calculate TotalPRBs which can be used
2397 * [Step 2]: Get the reference pointer for Coreset and Its SearchSpace.
2398 * [Step 3]: A CCE will have 6 RBs in TOTAL. If duration increases, CCE will
2399 * occupy less number of PRBs(1RB x 1 OFDM Symbol). Eg. If duration = 2, then
2400 * instead of 6 PRBs, CCE will only occupy 3 PRBs and 2 OFDM symbols.
2401 * [Step 4]: Based on CoresetSize, fill AggLvl-CQI mapping by calculating the dciSize.
2402 * [Step 5]: Calculate Y value for this coreset and UE
2404 * @Params[in]: UeCb,
2405 * [return]: ROK, RFAILED : Memory allocation failure.
2407 uint8_t fillUeCoresetAndSsInfo(SchUeCb *ue)
2409 uint8_t cRSetIdx = 0,ssIdx = 0;
2410 uint16_t rbgCount = 0;
2411 SchPdcchConfig *pdcchCfg = NULLP;
2413 pdcchCfg = &ue->ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg;
2414 if(pdcchCfg == NULLP)
2416 DU_LOG("\nERROR --> SCH: PDCCH Cfg is not received thus skip filling of Coreset & SS info");
2419 for(cRSetIdx = 0; cRSetIdx < pdcchCfg->numCRsetToAddMod; cRSetIdx++ )
2421 /*[Step 1]: *//*Size of coreset: Number of PRBs in a coreset*/
2422 rbgCount = countRBGFrmCoresetFreqRsrc(pdcchCfg->cRSetToAddModList[cRSetIdx].freqDomainRsrc);
2425 ue->pdcchInfo[cRSetIdx].totalPrbs = ((rbgCount) * NUM_PRBS_PER_RBG);
2429 DU_LOG("\nERROR --> SCH : CORESETSize is zero in fillCoresetAndSsConfg");
2433 ue->pdcchInfo[cRSetIdx].cRSetRef = &pdcchCfg->cRSetToAddModList[cRSetIdx];
2434 for(ssIdx = 0; ssIdx < pdcchCfg->numSearchSpcToAddMod; ssIdx++)
2436 if(pdcchCfg->searchSpcToAddModList[ssIdx].cRSetId == pdcchCfg->cRSetToAddModList[cRSetIdx].cRSetId)
2438 ue->pdcchInfo[cRSetIdx].ssRef = &pdcchCfg->searchSpcToAddModList[ssIdx];
2444 /*nrOfPRBPerCce is Number of PRBs occupied by a CCE based on Duration*/
2445 ue->pdcchInfo[cRSetIdx].nrOfPRBPerCce = NUM_PRBS_PER_RBG/pdcchCfg->cRSetToAddModList[cRSetIdx].duration;
2446 ue->pdcchInfo[cRSetIdx].totalCceCount = rbgCount * pdcchCfg->cRSetToAddModList[cRSetIdx].duration;
2449 fillCqiAggLvlMapping(&ue->pdcchInfo[cRSetIdx]);
2452 if(RFAILED == schUpdValY(ue, &ue->pdcchInfo[cRSetIdx]))
2461 * @brief: Function will validate a slot for PDCCH allocation
2463 * Function: schPdcchSlotValidation
2465 * As per 3gpp Spec 38.331, SearchSpace parameter, Every SearchSpace will have
2466 * details of which slot and after how many slot the UE will monitor for PDCCH.
2467 * Thus, while PDCCH allocation we need to ensure the above validation passes.
2469 * @param [IN]: PDCCH time, SearchSpace Info, numSlots in Cell
2470 * [RETURN]: Flag depicting the slot validation
2472 bool schPdcchSlotValidation(SlotTimingInfo pdcchTime, SchSearchSpace *searchSpace, uint16_t numSlots)
2474 bool isSlotValid = false;
2475 uint16_t slotNum = 0, mSlotPeriodicityVal = 0;
2477 /*Converting the timing info in units of Slots*/
2478 slotNum = (pdcchTime.sfn * numSlots)+pdcchTime.slot;
2480 mSlotPeriodicityVal = \
2481 schConvertSlotPeriodicityEnumToValue(searchSpace->mSlotPeriodicityAndOffset.mSlotPeriodicity);
2483 if(!mSlotPeriodicityVal)
2485 DU_LOG("\nERROR --> SCH: Slot Periodicity is ZERO thus cant proceed with this SearchSpace");
2488 /*The Monitoring slot begins from offset thus skip the slots which are less
2489 * than offset value*/
2490 if((slotNum >= searchSpace->mSlotPeriodicityAndOffset.mSlotOffset))
2492 /*A pdcch Slot will start after Slotoffset and will get repeated after every
2494 if(((slotNum - searchSpace->mSlotPeriodicityAndOffset.mSlotOffset) % mSlotPeriodicityVal) == 0)
2496 DU_LOG("\nINFO --> SCH: SFN:%d/Slot:%d, is a Valid PDCCH slot",pdcchTime.sfn, pdcchTime.slot);
2501 DU_LOG("\nINFO --> SCH: SFN:%d/Slot:%d, is InValid PDCCH slot",pdcchTime.sfn, pdcchTime.slot);
2504 return (isSlotValid);
2508 * @brief: Function to check if PDCCH is available for a cceIndex
2510 * Function: schCheckPdcchAvail
2512 * This function checks if the PRBs available for a particular CCE during
2514 * [Step 1]: Calculate the rbgIndex from cceIndex which depends on Coreset symbol duration
2515 * i.e. a) If symbolDuration = 1; numPrbs in RBG (6) = numPrbPerCCE thus one on
2516 * one mapping between rbgIndex and cceIndex
2517 * b) if SymbolDuration =2; NumPrbs in RBG(6) = numPrbPerCCE * duration
2518 * as CCE needs 6 REG thus in 3 PRBs whole CCE can contain
2521 * [Step 2]: Again StartPRB for a rbgIndex may not be same for CCE Index which
2522 * depends on duration. If duration=2, then two CCE can be occupied
2523 * in one RBGIndex thus StarPrb for secondCCE will be
2524 * numPrbsPerCCE(3) away.
2526 * @params[in]: CellCb, SlotTime, cceIndex, PDcchInfo, aggLvl
2528 bool schCheckPdcchAvail(SchCellCb *cellCb, SlotTimingInfo slotTime, uint8_t cceIndex,\
2529 SchPdcchInfo *pdcchInfo, uint8_t aggLvl )
2531 uint8_t rbgIndex = 0, ret = 0, startSymbol = 0;
2532 uint16_t startPrb = MAX_NUM_RB, numPrb = 0;
2534 /*[Step 1]: rbgIndex to locate in FreqDomainResource parmaeter in
2536 rbgIndex = cceIndex / (pdcchInfo->cRSetRef->duration);
2538 /*Extract StartPRB for that RBGIndex*/
2539 startPrb = extractStartPrbForRBG(pdcchInfo->cRSetRef->freqDomainRsrc, rbgIndex);
2540 if(startPrb == MAX_NUM_RB)
2542 DU_LOG("\nERROR --> SCH: No RBG is allocated for PDCCH in this Coreset");
2545 /*[Step 2]: Adjust StartPrb based on CCEIndex and duration*/
2546 startPrb = startPrb + ((cceIndex % pdcchInfo->cRSetRef->duration) * (pdcchInfo->nrOfPRBPerCce));
2547 startSymbol = findSsStartSymbol(pdcchInfo->ssRef->mSymbolsWithinSlot);
2549 /*numPrb will also get adjusted with duration*/
2550 numPrb = (NUM_PRBS_PER_RBG * aggLvl) / pdcchInfo->cRSetRef->duration;
2551 DU_LOG("\nDEBUG --> SCH: RBG found for cceIndex:%d, AggLvl:%d and SymbolDuration%d with StartPrb:%d, numPrb:%d",\
2552 cceIndex, aggLvl, pdcchInfo->cRSetRef->duration, startPrb, numPrb);
2554 ret = allocatePrbDl(cellCb, slotTime, startSymbol,\
2555 pdcchInfo->cRSetRef->duration, &startPrb, numPrb);
2559 DU_LOG("\nERROR --> SCH: PRBs can't be allocated as they are unavailable");
2567 * @brief: Function to select particular UE based on validation of PDCCH allocation
2570 * This function will have multiple layers of validation for PDCCH allocation
2571 * based on CORESET and SearchSpace configuration and availability.
2573 * [Step 1]: Check if the slot is pdcch Slot or not based on SearchSpace's
2574 * monitoringSlotInfo.
2575 * [Step 2]: Check the CQI for this UE and decide upon which Agg Level has to
2576 * be used for this PDCCH transmission
2577 * [Step 3]: find the AggLevel for this CQI = base aggregation level
2578 * [Step 4]: NextLowerAggLvl will be the next lower aggLevel when PDCCH
2579 * allocation fails for base agg Level.
2580 * [Step 5]: For each candidate , calculate the CCE Index as per TS
2581 * 38.213v15, Sec 10.1 and also check PRBs falling in that CCEIndex is free.
2582 * [Step 6]: If Step 5 fails, move to next candidate and if Candidate gets
2583 * exhausted then fallback to nextAggLevel. Because as we decrease aggLevel,
2584 * numberOfCCEReq decreases so chances of PDCCH allocation increases even
2585 * though lowerAggLevel will not guarantee transmission of PDCCH as per CQI
2586 * reported.(CQI less, AggiLvlRequried is More)
2588 * @params[IN]: SchUeCb and PdcchTime
2589 * [RETURN]: isPDCCHAllocted flag(true = UE can be selected as a
2592 bool schDlCandidateSelection(SchUeCb *ueCb, SlotTimingInfo pdcchTime, SchPdcchAllocInfo *pdcchAllocInfo)
2594 uint8_t cRSetIdx = 0, cceIndex = 0;
2595 uint8_t cqi = 0, candIdx = 0;
2596 uint8_t baseAggLvl = 0, nextLowerAggLvl = 0, numCandidates = 0;
2597 SchPdcchInfo *pdcchInfo = NULLP;
2598 uint32_t a = 0, b = 0;
2600 for(cRSetIdx = 0; cRSetIdx < MAX_NUM_CRSET; cRSetIdx++)
2602 pdcchInfo = &ueCb->pdcchInfo[cRSetIdx];
2603 if(pdcchInfo->cRSetRef == NULLP)
2605 DU_LOG("\nINFO --> SCH: Coreset is not availabe at Index:%d",cRSetIdx);
2609 if(false == schPdcchSlotValidation(pdcchTime, pdcchInfo->ssRef, ueCb->cellCb->numSlots))
2611 DU_LOG("\nINFO --> SCH: This slot is not valid for PDCCH in this CORESET:%d.",pdcchInfo->cRSetRef->cRSetId);
2615 /*TODO: CQI is reported in DL_CQI_IND which has to be processed and
2616 * report has to be stored in ueCb.For now, HardCoding the value*/
2620 baseAggLvl = pdcchInfo->cqiIndxAggLvlMap[cqi];
2623 nextLowerAggLvl = baseAggLvl;
2625 /*Loop to traverse through each AggLvl from higher value of aggLevel to
2629 /*Configured num of candidates for each Agg Level in search space */
2630 numCandidates = extractNumOfCandForAggLvl(pdcchInfo->ssRef, nextLowerAggLvl);
2633 DU_LOG("\nINFO --> SCH: Num Of Candidates configured for this AggLvel:%d is ZERO",baseAggLvl);
2637 for(candIdx= 0; candIdx < numCandidates; candIdx++)
2639 /*Formula reference 3GPP TS 38.213v15, Sec 10.1, Variable 'a' and
2640 * 'b' is used for segmenting the formulat for readability purpose
2642 a = pdcchInfo->y[pdcchTime.slot] + \
2643 ceil((candIdx * pdcchInfo->totalCceCount)/(baseAggLvl * numCandidates));
2644 b = ceil(pdcchInfo->totalCceCount * baseAggLvl);
2645 cceIndex = baseAggLvl * (a % b);
2646 if(schCheckPdcchAvail(ueCb->cellCb, pdcchTime, cceIndex, pdcchInfo,nextLowerAggLvl) == true)
2648 DU_LOG("\nINFO --> SCH: PDCCH allocation is successful at cceIndex:%d",cceIndex);
2649 pdcchAllocInfo->cRSetId = pdcchInfo->cRSetRef->cRSetId;
2650 pdcchAllocInfo->aggLvl = nextLowerAggLvl;
2651 pdcchAllocInfo->cceIndex = cceIndex;
2652 pdcchAllocInfo->ssId = pdcchInfo->ssRef->searchSpaceId;
2656 nextLowerAggLvl = nextLowerAggLvl >> 1;
2657 }while(nextLowerAggLvl > 0 && nextLowerAggLvl <= 16);
2661 /**********************************************************************
2663 **********************************************************************/