1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
35 #include "envopt.h" /* environment options */
36 #include "envdep.h" /* environment dependent */
37 #include "envind.h" /* environment independent */
38 #include "gen.h" /* general layer */
39 #include "ssi.h" /* system service interface */
40 #include "cm_tkns.h" /* Common Token Defines */
41 #include "cm_llist.h" /* Common Link List Defines */
42 #include "cm_hash.h" /* Common Hash List Defines */
43 #include "cm_mblk.h" /* common memory link list library */
44 #include "cm_lte.h" /* Common LTE Defines */
48 #include "gen.x" /* general layer typedefs */
49 #include "ssi.x" /* system services typedefs */
50 #include "cm5.x" /* system services */
51 #include "cm_tkns.x" /* Common Token Definitions */
52 #include "cm_llist.x" /* Common Link List Definitions */
53 #include "cm_lib.x" /* Common Library Definitions */
54 #include "cm_hash.x" /* Common Hash List Definitions */
55 #include "cm_mblk.x" /* common memory link list library */
56 #include "cm_lte.x" /* Common LTE Defines */
60 #include "du_app_mac_inf.h"
61 #include "mac_sch_interface.h"
63 #include "sch_utils.h"
64 #include "common_def.h"
66 extern SchCb schCb[SCH_MAX_INST];
67 extern uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
68 extern uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
70 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
78 * @brief common resource allocation for SSB
82 * Function : schBroadcastAlloc
84 * This function handles common scheduling for DL
86 * @param[in] SchCellCb *cell, cell cb
87 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
90 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
94 uint8_t ssbStartPrb, ssbStartSymb, idx;
95 SchDlSlotInfo *schDlSlotInfo;
98 schDlSlotInfo = cell->schDlSlotInfo[slot];
99 if(dlBrdcstAlloc->ssbTrans)
101 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
102 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
103 supporting only 1 ssb beam */
105 /* Assign interface structure */
106 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
108 ssbInfo.ssbIdx = idx;
109 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
110 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
111 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
112 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
113 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
114 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
117 schDlSlotInfo->ssbPres = true;
118 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
119 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
121 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
125 /* SIB1 allocation */
126 if(dlBrdcstAlloc->sib1Trans)
128 schDlSlotInfo->sib1Pres = true;
129 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
131 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + 10; /* 10 PRBs for sib1 */
133 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
134 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
135 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
140 /*******************************************************************
142 * @brief Handles sending UL scheduler info to MAC
146 * Function : sendUlSchInfoToMac
149 * Sends UL Sch info to MAC from SCH
152 * @return ROK - success
155 * ****************************************************************/
156 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
160 memset(&pst, 0, sizeof(Pst));
161 SCH_FILL_RSP_PST(pst, inst);
162 pst.event = EVENT_UL_SCH_INFO;
164 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
167 * @brief resource allocation for PRACH
171 * Function : schPrachResAlloc
173 * This function handles PRACH allocation
175 * @param[in] SchCellCb *cell, cell cb
176 * @param[in] UlSchedInfo *ulSchedInfo, UL scheduling info
179 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
182 uint8_t numPrachRb = 0;
184 uint8_t freqStart = 0;
185 uint8_t prachCfgIdx = 0;
186 uint8_t prachFormat = 0;
189 uint16_t prachSubframe = 0;
190 uint8_t prachStartSymbol = 0;
191 uint8_t prachOcas = 0;
192 uint8_t dataType = 0;
194 SchUlSlotInfo *schUlSlotInfo = NULLP;
196 puschScs = cell->cellCfg.schInitialUlBwp.bwp.scs;
197 schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
198 prachCfgIdx = cell->cellCfg.schRachCfg.prachCfgIdx;
200 /* derive the prachCfgIdx table paramters */
201 x = prachCfgIdxTable[prachCfgIdx][1];
202 y = prachCfgIdxTable[prachCfgIdx][2];
203 prachSubframe = prachCfgIdxTable[prachCfgIdx][3];
205 if((prachOccasionTimingInfo.sfn%x) == y)
207 /* check for subFrame number */
208 if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
210 /* prach ocassion present in this subframe */
212 prachFormat = prachCfgIdxTable[prachCfgIdx][0];
213 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
214 prachOcas = prachCfgIdxTable[prachCfgIdx][6];
216 /* freq domain resource determination for RACH*/
217 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
218 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
219 * where M is given by msg1Fdm */
220 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
221 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
223 if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
225 if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
227 if(numRbForPrachTable[idx][2] == puschScs)
234 numPrachRb = numRbForPrachTable[idx][3];
235 dataType |= SCH_DATATYPE_PRACH;
236 /* Considering first slot in the frame for PRACH */
238 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
240 ulSchedInfo->dataType = dataType;
242 ulSchedInfo->prachSchInfo.numPrachOcas = prachOcas;
243 ulSchedInfo->prachSchInfo.prachFormat = prachFormat;
244 ulSchedInfo->prachSchInfo.numRa = numRa;
245 ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
250 * @brief resource allocation for UL
254 * Function : schUlResAlloc
256 * This function handles UL Resource allocation
258 * @param[in] SchCellCb *cell, cellCb
261 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
264 UlSchedInfo ulSchedInfo;
265 SchUlSlotInfo *schUlSlotInfo;
266 SlotIndInfo ulTimingInfo;
269 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA+SCHED_DELTA);
271 ulSchedInfo.cellId = cell->cellId;
272 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
273 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
275 /* Schedule resources for PRACH */
276 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
278 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
280 if(schUlSlotInfo->schPuschInfo)
282 ulSchedInfo.crnti = cell->raCb[0].tcrnti;
283 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
284 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
285 sizeof(SchPuschInfo));
286 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
287 schUlSlotInfo->schPuschInfo = NULL;
291 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
294 DU_LOG("\nSending UL Sch info from SCH to MAC failed");
297 memset(cell->schUlSlotInfo[ulTimingInfo.slot], 0, sizeof(SchUlSlotInfo));
302 /*******************************************************************
304 * @brief Fills pdcch and pdsch info for msg4
308 * Function : schDlRsrcAllocMsg4
311 * Fills pdcch and pdsch info for msg4
314 * @return ROK - success
317 * ****************************************************************/
318 uint8_t schDlRsrcAllocMsg4(Msg4Alloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
320 uint8_t coreset0Idx = 0;
322 uint8_t firstSymbol = 0;
323 uint8_t numSymbols = 0;
325 uint8_t offsetPointA;
326 uint8_t FreqDomainResource[6] = {0};
328 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
329 uint8_t mcs = 4; /* MCS fixed to 4 */
330 SchBwpDlCfg *initialBwp;
332 PdcchCfg *pdcch = &msg4Alloc->msg4PdcchCfg;
333 PdschCfg *pdsch = &msg4Alloc->msg4PdschCfg;
334 BwpCfg *bwp = &msg4Alloc->bwp;
336 initialBwp = &cell->cellCfg.schInitialDlBwp;
337 offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
338 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
340 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
341 numRbs = coresetIdxTable[coreset0Idx][1];
342 numSymbols = coresetIdxTable[coreset0Idx][2];
343 offset = coresetIdxTable[coreset0Idx][3];
345 /* calculate time domain parameters */
346 uint16_t mask = 0x2000;
347 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
349 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
355 /* calculate the PRBs */
356 schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
359 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
360 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
361 bwp->subcarrierSpacing = initialBwp->bwp.scs;
362 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
364 /* fill the PDCCH PDU */
365 pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
366 pdcch->coreset0Cfg.durationSymbols = numSymbols;
367 memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
368 pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
369 pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
370 pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
371 pdcch->coreset0Cfg.coreSetType = 0;
372 pdcch->coreset0Cfg.coreSet0Size = numRbs;
373 pdcch->coreset0Cfg.shiftIndex = cell->cellCfg.phyCellId;
374 pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
376 pdcch->dci.rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
377 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
378 pdcch->dci.scramblingRnti = 0;
379 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
380 pdcch->dci.aggregLevel = 4;
381 pdcch->dci.beamPdcchInfo.numPrgs = 1;
382 pdcch->dci.beamPdcchInfo.prgSize = 1;
383 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
384 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
385 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
386 pdcch->dci.txPdcchPower.powerValue = 0;
387 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
389 /* fill the PDSCH PDU */
391 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
392 pdsch->rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
394 pdsch->numCodewords = 1;
395 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
397 pdsch->codeword[cwCount].targetCodeRate = 308;
398 pdsch->codeword[cwCount].qamModOrder = 2;
399 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
400 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
401 pdsch->codeword[cwCount].rvIndex = 0;
402 /* 38.214: Table 5.1.3.2-1, divided by 8 to get the value in bytes */
403 /* TODO : Calculate tbSize based of DL CCCH msg size */
404 tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
405 pdsch->codeword[cwCount].tbSize = tbSize;
407 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
408 pdsch->numLayers = 1;
409 pdsch->transmissionScheme = 0;
411 pdsch->dmrs.dlDmrsSymbPos = 2;
412 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
413 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
414 pdsch->dmrs.scid = 0;
415 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
416 pdsch->dmrs.dmrsPorts = 0;
417 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
418 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
419 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
420 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
421 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
422 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
423 pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
424 pdsch->beamPdschInfo.numPrgs = 1;
425 pdsch->beamPdschInfo.prgSize = 1;
426 pdsch->beamPdschInfo.digBfInterfaces = 0;
427 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
428 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
429 pdsch->txPdschPower.powerControlOffset = 0;
430 pdsch->txPdschPower.powerControlOffsetSS = 0;
432 pdcch->dci.pdschCfg = pdsch;
436 /**********************************************************************
438 **********************************************************************/