1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
35 #include "envopt.h" /* environment options */
36 #include "envdep.h" /* environment dependent */
37 #include "envind.h" /* environment independent */
38 #include "gen.h" /* general layer */
39 #include "ssi.h" /* system service interface */
40 #include "cm_tkns.h" /* Common Token Defines */
41 #include "cm_llist.h" /* Common Link List Defines */
42 #include "cm_hash.h" /* Common Hash List Defines */
43 #include "cm_mblk.h" /* common memory link list library */
44 #include "cm_lte.h" /* Common LTE Defines */
48 #include "gen.x" /* general layer typedefs */
49 #include "ssi.x" /* system services typedefs */
50 #include "cm5.x" /* system services */
51 #include "cm_tkns.x" /* Common Token Definitions */
52 #include "cm_llist.x" /* Common Link List Definitions */
53 #include "cm_lib.x" /* Common Library Definitions */
54 #include "cm_hash.x" /* Common Hash List Definitions */
55 #include "cm_mblk.x" /* common memory link list library */
56 #include "cm_lte.x" /* Common LTE Defines */
60 #include "du_app_mac_inf.h"
61 #include "mac_sch_interface.h"
63 #include "sch_utils.h"
64 #include "common_def.h"
66 extern SchCb schCb[SCH_MAX_INST];
67 extern uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
68 extern uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
69 extern uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
71 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
79 * @brief common resource allocation for SSB
83 * Function : schBroadcastAlloc
85 * This function handles common scheduling for DL
87 * @param[in] SchCellCb *cell, cell cb
88 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
91 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
95 uint8_t ssbStartPrb, ssbStartSymb, idx;
96 SchDlSlotInfo *schDlSlotInfo;
99 schDlSlotInfo = cell->schDlSlotInfo[slot];
100 if(dlBrdcstAlloc->ssbTrans)
102 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
103 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
104 supporting only 1 ssb beam */
106 /* Assign interface structure */
107 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
109 ssbInfo.ssbIdx = idx;
110 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
111 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
112 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
113 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
114 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
115 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
118 schDlSlotInfo->ssbPres = true;
119 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
120 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
122 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
126 /* SIB1 allocation */
127 if(dlBrdcstAlloc->sib1Trans)
129 schDlSlotInfo->sib1Pres = true;
130 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
132 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + 10; /* 10 PRBs for sib1 */
134 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
135 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
136 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
141 /*******************************************************************
143 * @brief Handles sending UL scheduler info to MAC
147 * Function : sendUlSchInfoToMac
150 * Sends UL Sch info to MAC from SCH
153 * @return ROK - success
156 * ****************************************************************/
157 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
161 memset(&pst, 0, sizeof(Pst));
162 SCH_FILL_RSP_PST(pst, inst);
163 pst.event = EVENT_UL_SCH_INFO;
165 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
168 * @brief resource allocation for PRACH
172 * Function : schPrachResAlloc
174 * This function handles PRACH allocation
176 * @param[in] SchCellCb *cell, cell cb
177 * @param[in] UlSchedInfo *ulSchedInfo, UL scheduling info
180 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
183 uint8_t numPrachRb = 0;
185 uint8_t freqStart = 0;
186 uint8_t prachCfgIdx = 0;
187 uint8_t prachFormat = 0;
190 uint16_t prachSubframe = 0;
191 uint8_t prachStartSymbol = 0;
192 uint8_t prachOcas = 0;
193 uint8_t dataType = 0;
195 SchUlSlotInfo *schUlSlotInfo = NULLP;
197 puschScs = cell->cellCfg.schInitialUlBwp.bwp.scs;
198 schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
199 prachCfgIdx = cell->cellCfg.schRachCfg.prachCfgIdx;
201 /* derive the prachCfgIdx table paramters */
202 x = prachCfgIdxTable[prachCfgIdx][1];
203 y = prachCfgIdxTable[prachCfgIdx][2];
204 prachSubframe = prachCfgIdxTable[prachCfgIdx][3];
206 if((prachOccasionTimingInfo.sfn%x) == y)
208 /* check for subFrame number */
209 if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
211 /* prach ocassion present in this subframe */
213 prachFormat = prachCfgIdxTable[prachCfgIdx][0];
214 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
215 prachOcas = prachCfgIdxTable[prachCfgIdx][6];
217 /* freq domain resource determination for RACH*/
218 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
219 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
220 * where M is given by msg1Fdm */
221 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
222 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
224 if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
226 if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
228 if(numRbForPrachTable[idx][2] == puschScs)
235 numPrachRb = numRbForPrachTable[idx][3];
236 dataType |= SCH_DATATYPE_PRACH;
237 /* Considering first slot in the frame for PRACH */
239 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
241 ulSchedInfo->dataType = dataType;
243 ulSchedInfo->prachSchInfo.numPrachOcas = prachOcas;
244 ulSchedInfo->prachSchInfo.prachFormat = prachFormat;
245 ulSchedInfo->prachSchInfo.numRa = numRa;
246 ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
250 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
252 /* derive pucchResourceSet from schCellCfg */
253 SchCellCb *cell = schCb[inst].cells[inst];
254 SchPucchCfgCmn *pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
255 uint8_t pucchIdx = pucchCfg->pucchResourceCommon;
256 SchBwpParams *ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
258 schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
259 schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0;
260 schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
261 schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
262 schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
264 /* set HARQ flag to true */
265 schPucchInfo->harqFlag = true;
266 schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
268 /* set SR and UCI flag to false */
269 schPucchInfo->srFlag = false;
270 schPucchInfo->uciFlag = false;
276 * @brief resource allocation for UL
280 * Function : schUlResAlloc
282 * This function handles UL Resource allocation
284 * @param[in] SchCellCb *cell, cellCb
287 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
290 UlSchedInfo ulSchedInfo;
291 SchUlSlotInfo *schUlSlotInfo = NULLP;
292 SlotIndInfo ulTimingInfo;
293 memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
296 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA+SCHED_DELTA);
298 ulSchedInfo.cellId = cell->cellId;
299 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
300 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
302 /* Schedule resources for PRACH */
303 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
305 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
306 if(schUlSlotInfo->schPuschInfo)
308 ulSchedInfo.crnti = cell->raCb[0].tcrnti;
309 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
310 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
311 sizeof(SchPuschInfo));
312 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
313 schUlSlotInfo->schPuschInfo = NULL;
316 if(schUlSlotInfo->pucchPres)
318 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
319 fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
320 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
321 sizeof(SchPucchInfo));
322 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
326 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
329 DU_LOG("\nSending UL Sch info from SCH to MAC failed");
331 memset(cell->schUlSlotInfo[ulTimingInfo.slot], 0, sizeof(SchUlSlotInfo));
336 /*******************************************************************
338 * @brief Fills pdcch and pdsch info for msg4
342 * Function : schDlRsrcAllocMsg4
345 * Fills pdcch and pdsch info for msg4
348 * @return ROK - success
351 * ****************************************************************/
352 uint8_t schDlRsrcAllocMsg4(Msg4Alloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
354 uint8_t coreset0Idx = 0;
356 uint8_t firstSymbol = 0;
357 uint8_t numSymbols = 0;
359 uint8_t offsetPointA;
360 uint8_t FreqDomainResource[6] = {0};
362 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
363 uint8_t mcs = 4; /* MCS fixed to 4 */
364 SchBwpDlCfg *initialBwp;
366 PdcchCfg *pdcch = &msg4Alloc->msg4PdcchCfg;
367 PdschCfg *pdsch = &msg4Alloc->msg4PdschCfg;
368 BwpCfg *bwp = &msg4Alloc->bwp;
370 initialBwp = &cell->cellCfg.schInitialDlBwp;
371 offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
372 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
374 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
375 numRbs = coresetIdxTable[coreset0Idx][1];
376 numSymbols = coresetIdxTable[coreset0Idx][2];
377 offset = coresetIdxTable[coreset0Idx][3];
379 /* calculate time domain parameters */
380 uint16_t mask = 0x2000;
381 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
383 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
389 /* calculate the PRBs */
390 schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
393 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
394 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
395 bwp->subcarrierSpacing = initialBwp->bwp.scs;
396 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
398 /* fill the PDCCH PDU */
399 pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
400 pdcch->coreset0Cfg.durationSymbols = numSymbols;
401 memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
402 pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
403 pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
404 pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
405 pdcch->coreset0Cfg.coreSetType = 0;
406 pdcch->coreset0Cfg.coreSet0Size = numRbs;
407 pdcch->coreset0Cfg.shiftIndex = cell->cellCfg.phyCellId;
408 pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
410 pdcch->dci.rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
411 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
412 pdcch->dci.scramblingRnti = 0;
413 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
414 pdcch->dci.aggregLevel = 4;
415 pdcch->dci.beamPdcchInfo.numPrgs = 1;
416 pdcch->dci.beamPdcchInfo.prgSize = 1;
417 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
418 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
419 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
420 pdcch->dci.txPdcchPower.powerValue = 0;
421 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
423 /* fill the PDSCH PDU */
425 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
426 pdsch->rnti = cell->schDlSlotInfo[slot]->msg4Info->crnti;
428 pdsch->numCodewords = 1;
429 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
431 pdsch->codeword[cwCount].targetCodeRate = 308;
432 pdsch->codeword[cwCount].qamModOrder = 2;
433 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
434 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
435 pdsch->codeword[cwCount].rvIndex = 0;
436 /* 38.214: Table 5.1.3.2-1, divided by 8 to get the value in bytes */
437 /* TODO : Calculate tbSize based of DL CCCH msg size */
438 tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
439 pdsch->codeword[cwCount].tbSize = tbSize;
441 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
442 pdsch->numLayers = 1;
443 pdsch->transmissionScheme = 0;
445 pdsch->dmrs.dlDmrsSymbPos = 2;
446 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
447 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
448 pdsch->dmrs.scid = 0;
449 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
450 pdsch->dmrs.dmrsPorts = 0;
451 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
452 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
453 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
454 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
455 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
456 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
457 pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
458 pdsch->beamPdschInfo.numPrgs = 1;
459 pdsch->beamPdschInfo.prgSize = 1;
460 pdsch->beamPdschInfo.digBfInterfaces = 0;
461 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
462 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
463 pdsch->txPdschPower.powerControlOffset = 0;
464 pdsch->txPdschPower.powerControlOffsetSS = 0;
466 pdcch->dci.pdschCfg = pdsch;
470 uint16_t schAllocPucchResource(SchCellCb *cell,uint16_t crnti, uint16_t slot)
472 uint8_t k1 = 1; /* dl-DataToUL-ACK RRC parameter will received from DU-APP msg4-pucch config */
473 uint16_t pucchSlot = (slot + k1) % SCH_NUM_SLOTS;
474 SchUlSlotInfo *schUlSlotInfo = NULLP;
476 schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
477 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
479 schUlSlotInfo->pucchPres = true;
480 schUlSlotInfo->schPucchInfo.rnti = crnti;
485 /**********************************************************************
487 **********************************************************************/