1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 typedef struct schCellCb SchCellCb;
63 typedef struct schUeCb SchUeCb;
76 SCH_UE_STATE_INACTIVE,
82 SCH_LC_STATE_INACTIVE,
101 * Structure holding LTE MAC's General Configuration information.
103 typedef struct schGenCb
105 uint8_t tmrRes; /*!< Timer resolution */
106 uint8_t startCellId; /*!< Starting Cell Id */
108 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
109 of RLC control BO and SRB BO on
110 PCell. val 0 means don't force*/
111 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
115 typedef struct freePrbBlock
124 * PRB allocations for a symbol within a slot
126 typedef struct schPrbAlloc
128 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
129 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
134 * scheduler allocationsfor DL per cell.
136 typedef struct schDlSlotInfo
138 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
139 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
140 uint8_t ssbIdxSupported; /*!< Max SSB index */
141 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
142 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
143 RarAlloc *rarAlloc; /*!< RAR allocation */
144 DlMsgAlloc *dlMsgAlloc; /*!< Dl msg allocation */
147 typedef struct schRaCb
156 * scheduler allocationsfor UL per cell.
158 typedef struct schUlSlotInfo
160 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
161 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
162 bool puschPres; /*!< PUSCH presence field */
163 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
164 bool pucchPres; /*!< PUCCH presence field */
165 SchPucchInfo schPucchInfo; /*!< PUCCH info */
170 * BSR info per slot per UE.
172 typedef struct bsrInfo
174 uint8_t priority; /* CG priority */
175 uint32_t dataVol; /* Data volume requested in bytes */
178 typedef struct schLcCtxt
180 uint8_t lcId; // logical Channel ID
181 uint8_t lcp; // logical Channel Prioritization
184 uint16_t pduSessionId; /*Pdu Session Id*/
185 Snssai *snssai; /*S-NSSAI assoc with LCID*/
186 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
189 typedef struct schDlCb
191 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
194 typedef struct schUlLcCtxt
201 uint8_t pbr; // prioritisedBitRate
202 uint8_t bsd; // bucketSizeDuration
203 uint16_t pduSessionId; /*Pdu Session Id*/
204 Snssai *snssai; /*S-NSSAI assoc with LCID*/
205 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
208 typedef struct schUlCb
210 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
213 typedef struct schUeCfgCb
217 bool macCellGrpCfgPres;
218 SchMacCellGrpCfg macCellGrpCfg;
219 bool phyCellGrpCfgPres;
220 SchPhyCellGrpCfg phyCellGrpCfg;
222 SchSpCellCfg spCellCfg;
224 SchModulationInfo dlModInfo;
225 SchModulationInfo ulModInfo;
228 /*Following structures to keep record and estimations of PRB allocated for each
229 * LC taking into consideration the RRM policies*/
230 typedef struct lcInfo
232 uint8_t lcId; /*LCID for which BO are getting recorded*/
233 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
234 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
235 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
238 typedef struct dedicatedLCInfo
240 CmLListCp dedLcList; /*Linklist of LC assoc with RRMPolicyMemberList*/
241 uint16_t rsvdDedicatedPRB; /*Number of PRB reserved for this Dedicated S-NSSAI*/
244 typedef struct schLcPrbEstimate
246 /* TODO: For Multiple RRMPolicies, Make DedicatedLcInfo as array/Double Pointer
247 * and have separate DedLCInfo for each RRMPolcyMemberList*/
248 /* Dedicated LC List will be allocated, if any available*/
249 DedicatedLCInfo *dedLcInfo; /*Contain LCInfo per RRMPolicy*/
251 CmLListCp defLcList; /*Linklist of LC assoc with Default S-NSSAI(s)*/
253 /* SharedPRB number can be used by any LC.
254 * Need to calculate in every Slot based on PRB availability*/
255 uint16_t sharedNumPrb;
262 typedef struct schUeCb
270 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
273 SchLcPrbEstimate dlLcPrbEst; /*DL PRB Alloc Estimate among different LC*/
274 SchLcPrbEstimate ulLcPrbEst; /*UL PRB Alloc Estimate among different LC*/
281 typedef struct schRaReq
284 RachIndInfo *rachInd;
285 SlotTimingInfo winStartTime;
286 SlotTimingInfo winEndTime;
291 * Cell Control block per cell.
293 typedef struct schCellCb
295 uint16_t cellId; /*!< Cell ID */
296 Inst instIdx; /*!< Index of the scheduler instance */
297 Inst macInst; /*!< Index of the MAC instance */
298 uint8_t numSlots; /*!< Number of slots in current frame */
299 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
300 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
301 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
302 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
303 bool firstSsbTransmitted;
304 bool firstSib1Transmitted;
305 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
306 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
307 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
308 uint16_t numActvUe; /*!<Number of active UEs */
309 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
310 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
311 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
313 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
314 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
315 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
321 * Control block for sch
325 TskInit schInit; /*!< Task Init info */
326 SchGenCb genCfg; /*!< General Config info */
327 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
328 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
329 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
332 /* Declaration for scheduler control blocks */
333 SchCb schCb[SCH_MAX_INST];
335 /* function declarations */
336 short int schActvTmr(Ent ent,Inst inst);
338 /* Configuration related function declarations */
339 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
340 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
341 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
342 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
343 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
344 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
345 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
346 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
348 /* Incoming message handler function declarations */
349 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
350 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
352 /* DL scheduling related function declarations */
353 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
354 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
355 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
356 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
357 void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
358 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime);
359 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueIdx, RarAlloc *rarAlloc, uint8_t k0Index);
360 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,\
361 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB);
362 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueIdx, DlMsgAlloc *msg4Alloc, uint8_t k0Idx);
363 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
364 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
365 uint16_t *startPrb, uint16_t numPrb);
366 uint16_t searchLargestFreeBlockDL(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb);
367 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, uint32_t *accumalatedBOSize);
369 /* UL scheduling related function declarations */
370 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
371 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
372 uint8_t schCalcPrachNumRb(SchCellCb *cell);
373 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
374 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti);
375 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
376 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo pdcchSlotTime, uint32_t dataVol, SchPuschInfo *puschInfo);
377 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
378 uint16_t *startPrb, uint16_t numPrb);
380 /*Generic Functions*/
381 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLcLL action);
382 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
383 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded);
385 /**********************************************************************
387 **********************************************************************/