1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 #define SCH_MAX_NUM_UL_HQ_PROC 16
63 #define SCH_MAX_NUM_DL_HQ_PROC 16
64 #define SCH_MAX_NUM_MSG3_TX 2
65 #define SCH_MAX_NUM_DL_HQ_TX 3
66 #define SCH_MAX_NUM_UL_HQ_TX 3
67 #define SCH_MAX_NUM_MSG4_TX 2
73 /* As per 38.331 the largest offset which can be used in of size 10240.
74 * But using this much size of array can cause memory related issue so thats why
75 * taking this size which are a multiple of the larger size */
76 #define MAX_DRX_SIZE 512
79 #define NUM_SCH_TYPE 1 /*Supported number of Scheduler Algorithm types*/
81 typedef struct schDlHqProcCb SchDlHqProcCb;
82 typedef struct schUlHqEnt SchUlHqEnt;
83 typedef struct schRaReq SchRaReq;
84 typedef struct schDlHqEnt SchDlHqEnt;
85 typedef struct schCellCb SchCellCb;
86 typedef struct schUeCb SchUeCb;
104 SCH_UE_STATE_INACTIVE,
106 SCH_UE_HANDIN_IN_PROGRESS
111 SCH_RA_STATE_MSG2_HANDLE,
112 SCH_RA_STATE_MSG3_PENDING,
113 SCH_RA_STATE_MSG4_PENDING,
114 SCH_RA_STATE_MSG4_DONE
119 SCH_LC_STATE_INACTIVE,
137 /*Following structures to keep record and estimations of PRB allocated for each
138 * LC taking into consideration the RRM policies*/
139 typedef struct lcInfo
141 uint8_t lcId; /*LCID for which BO are getting recorded*/
142 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
143 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
144 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
147 typedef struct schUlHqTbCb
155 SchMcsTable mcsTable;
161 uint8_t cntrRetxAllocFail;
165 typedef struct schDlHqTbCb
178 uint8_t isAckNackDtx;
179 uint8_t cntrRetxAllocFail;
180 //InfUeTbInfo tbCompInfo;
185 typedef struct schDrxHarqCb
187 uint32_t rttExpIndex;
189 uint32_t retxStrtIndex;
190 CmLList *retxStrtNode;
191 uint32_t retxExpIndex;
192 CmLList *retxExpNode;
196 typedef struct schUlHqProcCb
198 uint8_t procId; /*!< HARQ Process ID */
200 uint8_t maxHqTxPerHqP;
206 void *schSpcUlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
207 CmLList ulHqProcLink;
208 uint8_t puschResType; /*!< Resource allocation type */
209 uint16_t puschStartPrb;
210 uint16_t puschNumPrb;
211 uint8_t dmrsMappingType;
212 uint8_t nrOfDmrsSymbols;
214 SlotTimingInfo puschTime;
216 SchDrxHarqCb ulDrxHarqCb;
222 uint8_t procId; /*!< HARQ Process ID */
224 uint8_t maxHqTxPerHqP;
227 SchDlHqTbCb tbInfo[2];
229 void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
230 CmLList dlHqProcLink;
231 SlotTimingInfo pucchTime;
233 SchDrxHarqCb dlDrxHarqCb;
238 SchCellCb *cell; /*!< Contains the pointer to cell*/
239 SchUeCb *ue; /*!< Contains the pointer to ue*/
240 CmLListCp free; /*!< List of free HARQ processes */
241 CmLListCp inUse; /*!< List of in-use HARQ processes */
242 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
243 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
244 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
248 SchCellCb *cell; /*!< Contains the pointer to cell */
249 SchUeCb *ue; /*!< Contains the pointer to UE */
250 CmLListCp free; /*!< List of free HARQ processes */
251 CmLListCp inUse; /*!< List of in-use HARQ processes */
252 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
253 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
254 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
259 * Structure holding LTE MAC's General Configuration information.
261 typedef struct schGenCb
263 uint8_t tmrRes; /*!< Timer resolution */
264 uint8_t startCellId; /*!< Starting Cell Id */
266 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
267 of RLC control BO and SRB BO on
268 PCell. val 0 means don't force*/
269 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
273 typedef struct freePrbBlock
282 * PRB allocations for a symbol within a slot
284 typedef struct schPrbAlloc
286 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
287 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
292 * scheduler allocationsfor DL per cell.
294 typedef struct schDlSlotInfo
296 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
297 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
298 uint8_t ssbIdxSupported; /*!< Max SSB index */
299 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
300 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
301 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
302 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
303 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
305 DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
308 typedef struct schRaCb
313 uint16_t dlMsgPduLen;
314 SchUlHqProcCb msg3HqProc;
315 SchUlHqProcCb *retxMsg3HqProc;
323 * scheduler allocationsfor UL per cell.
325 typedef struct schUlSlotInfo
327 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
328 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
329 bool puschPres; /*!< PUSCH presence field */
330 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
331 bool pucchPres; /*!< PUCCH presence field */
332 SchPucchInfo schPucchInfo; /*!< PUCCH info */
333 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
334 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
339 * BSR info per slot per UE.
341 typedef struct bsrInfo
343 uint8_t priority; /* CG priority */
344 uint32_t dataVol; /* Data volume requested in bytes */
347 typedef struct schLcCtxt
349 uint8_t lcId; // logical Channel ID
350 uint8_t lcp; // logical Channel Prioritization
353 uint16_t pduSessionId; /*Pdu Session Id*/
354 Snssai *snssai; /*S-NSSAI assoc with LCID*/
355 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
356 uint16_t rsvdDedicatedPRB;
359 typedef struct schDlCb
361 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
364 typedef struct schUlLcCtxt
371 uint8_t pbr; // prioritisedBitRate
372 uint8_t bsd; // bucketSizeDuration
373 uint16_t pduSessionId; /*Pdu Session Id*/
374 Snssai *snssai; /*S-NSSAI assoc with LCID*/
375 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
376 uint16_t rsvdDedicatedPRB;
379 typedef struct schUlCb
381 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
384 typedef struct schUeCfgCb
389 bool macCellGrpCfgPres;
390 SchMacCellGrpCfg macCellGrpCfg;
391 bool phyCellGrpCfgPres;
392 SchPhyCellGrpCfg phyCellGrpCfg;
394 SchSpCellRecfg spCellCfg;
396 SchModulationInfo dlModInfo;
397 SchModulationInfo ulModInfo;
398 SchDataTransmission dataTransmissionAction;
401 typedef struct schHqDlMap
406 typedef struct schHqUlMap
412 typedef struct schDrxUeCb
414 bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */
415 bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */
416 uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/
417 uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/
418 uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/
419 uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */
420 uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */
421 uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */
422 uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */
423 uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/
424 uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/
425 uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/
426 uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/
427 bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */
428 uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/
429 bool shortCyclePresent; /* set this value if shortCycle is Present */
430 uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/
431 uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/
432 uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/
433 uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */
434 uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */
435 uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */
436 uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */
437 int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */
438 int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */
439 int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */
440 int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */
441 CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/
442 CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/
443 CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/
444 CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
451 typedef struct schUeCb
458 SchCfraResource cfraResource;
461 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
466 SchDlHqProcCb *msg4HqProc;
467 SchDlHqProcCb *retxMsg4HqProc;
468 SchHqDlMap **hqDlmap;
469 SchHqUlMap **hqUlmap;
481 typedef struct schRaReq
484 RachIndInfo *rachInd;
486 SchUeCb *ueCb; /* Filled only if isCFRA = true */
487 SlotTimingInfo winStartTime;
488 SlotTimingInfo winEndTime;
491 typedef struct schPageInfo
493 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
494 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
495 SlotTimingInfo pageTxTime; /*Start Paging window*/
496 uint8_t mcs; /*MCS index*/
497 uint16_t msgLen; /*Pdu length */
498 uint8_t *pagePdu; /*RRC Page PDU bit string*/
501 typedef struct schPagingOcc
504 uint8_t pagingOccSlot;
507 typedef struct schPageCb
509 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
510 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
514 typedef struct schDrxCb
516 CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */
517 CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */
518 CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */
519 CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */
520 CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */
521 CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */
522 CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */
523 CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */
524 CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */
525 CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */
529 typedef struct schAllApis
531 uint8_t (* SchCellCfgReq)(SchCellCb *cellCb);
532 void (* SchCellDeleteReq)(SchCellCb *cellCb);
533 uint8_t (* SchAddUeConfigReq)(SchUeCb *ueCb);
534 void (* SchModUeConfigReq)(SchUeCb *ueCb);
535 void (* SchUeDeleteReq)(SchUeCb *ueCb);
536 void (* SchDlHarqInd)();
537 void (* SchPagingInd)();
538 void (* SchRachRsrcReq)();
539 void (* SchRachRsrcRel)();
540 void (* SchCrcInd)(SchCellCb *cellCb, uint16_t ueId);
541 void (* SchRachInd)(SchCellCb *cellCb, uint16_t ueId);
542 void (* SchDlRlcBoInfo)(SchCellCb *cellCb, uint16_t ueId);
543 void (* SchSrUciInd)(SchCellCb *cellCb, uint16_t ueId);
544 void (* SchBsr)(SchCellCb *cellCb, uint16_t ueId);
545 void (* SchHandleLcList)(void *ptr, CmLList *node, ActionTypeLL action);
546 void (* SchAddToDlHqRetxList)(SchDlHqProcCb *hqP);
547 void (* SchAddToUlHqRetxList)(SchUlHqProcCb *hqP);
548 void (* SchRemoveFrmDlHqRetxList)(SchUeCb *ueCb, CmLList *node);
549 void (* SchRemoveFrmUlHqRetxList)(SchUeCb *ueCb, CmLList *node);
550 uint8_t (* SchAddUeToSchedule)(SchCellCb *cellCb, uint16_t ueId);
551 void (* SchRemoveUeFrmScheduleLst)(SchCellCb *cell, CmLList *node);
552 uint8_t (* SchInitDlHqProcCb)(SchDlHqProcCb *hqP);
553 uint8_t (* SchInitUlHqProcCb)(SchUlHqProcCb *hqP);
554 void (* SchFreeDlHqProcCb)(SchDlHqProcCb *hqP);
555 void (* SchFreeUlHqProcCb)(SchUlHqProcCb *hqP);
556 void (* SchDeleteDlHqProcCb)(SchDlHqProcCb *hqP);
557 void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP);
558 void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst);
559 uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \
560 bool isRetx, SchDlHqProcCb **hqP);
561 uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \
562 uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP);
566 * Cell Control block per cell.
568 typedef struct schCellCb
570 uint16_t cellId; /*!< Cell ID */
571 Inst instIdx; /*!< Index of the scheduler instance */
572 Inst macInst; /*!< Index of the MAC instance */
573 uint16_t numSlots; /*!< Number of slots in current frame */
574 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
575 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
576 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
577 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
578 bool firstSsbTransmitted;
579 bool firstSib1Transmitted;
580 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
581 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
582 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
583 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
584 uint16_t numActvUe; /*!< Number of active UEs */
585 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
586 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
587 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
588 SchPageCb pageCb; /*!< Page Record at Schedular*/
590 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
591 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
592 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
595 SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
597 SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/
598 SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/
599 void *schSpcCell; /*Ref of Scheduler specific structure*/
603 typedef struct schSliceCfg
605 uint8_t numOfSliceConfigured;
606 SchRrmPolicyOfSlice **listOfConfirguration;
611 * Control block for sch
615 TskInit schInit; /*!< Task Init info */
616 SchGenCb genCfg; /*!< General Config info */
617 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
618 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
619 SchAllApis allApis[NUM_SCH_TYPE]; /*!<List of All Scheduler Type dependent Function pointers*/
620 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
621 SchSliceCfg sliceCfg;
624 /* Declaration for scheduler control blocks */
625 SchCb schCb[SCH_MAX_INST];
627 /* function declarations */
628 short int schActvTmr(Ent ent,Inst inst);
629 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
631 /* Configuration related function declarations */
632 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
633 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
634 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
635 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
636 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
637 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
638 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
639 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
640 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
642 /* Incoming message handler function declarations */
643 uint8_t SchProcCellCfgReq(Pst *pst, SchCellCfg *schCellCfg);
644 uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd);
645 uint8_t SchProcRachInd(Pst *pst, RachIndInfo *rachInd);
646 uint8_t SchProcCrcInd(Pst *pst, CrcIndInfo *crcInd);
647 uint8_t SchProcDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo);
648 uint8_t SchAddUeConfigReq(Pst *pst, SchUeCfgReq *ueCfgToSch);
649 uint8_t SchProcBsr(Pst *pst, UlBufferStatusRptInd *bsrInd);
650 uint8_t SchProcSrUciInd(Pst *pst, SrUciIndInfo *uciInd);
651 uint8_t SchModUeConfigReq(Pst *pst, SchUeRecfgReq *ueRecfgToSch);
652 uint8_t SchProcUeDeleteReq(Pst *pst, SchUeDelete *ueDelete);
653 uint8_t SchProcCellDeleteReq(Pst *pst, SchCellDeleteReq *schCellDelete);
654 uint8_t SchProcSliceCfgReq(Pst *pst, SchSliceCfgReq *schSliceCfgReq);
655 uint8_t SchProcSliceRecfgReq(Pst *pst, SchSliceRecfgReq *schSliceRecfgReq);
656 uint8_t SchProcRachRsrcReq(Pst *pst, SchRachRsrcReq *schRachRsrcReq);
657 uint8_t SchProcRachRsrcRel(Pst *pst, SchRachRsrcRel *schRachRsrcRel);
658 uint8_t SchProcPagingInd(Pst *pst, SchPageInd *pageInd);
659 uint8_t SchProcDlHarqInd(Pst *pst, DlHarqInd *dlHarqInd);
661 /* DL scheduling related function declarations */
662 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
663 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
664 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
665 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
666 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
667 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
668 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
669 bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchDlHqProcCb **hqP);
670 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
671 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP);
672 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgAlloc *msg4Alloc,\
673 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
674 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
675 uint16_t *startPrb, uint16_t numPrb);
676 void fillDlMsgInfo(DlMsgInfo *dlMsgInfo, uint8_t crnti, bool isRetx, SchDlHqProcCb* hqP);
677 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
678 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP);
679 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
681 /* UL scheduling related function declarations */
682 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
683 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
684 uint8_t schCalcPrachNumRb(SchCellCb *cell);
685 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
686 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP);
687 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
688 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
689 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
690 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
691 uint16_t *startPrb, uint16_t numPrb);
692 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
694 /*Generic Functions*/
695 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
696 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
697 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
698 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
699 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
700 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
703 void schProcPagingCfg(SchCellCb *cell);
704 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
705 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
706 uint8_t schFillPagePdschCfg(SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingInfo slotTime, \
707 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
708 /*DL HARQ Functions*/
709 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
710 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
711 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
712 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
713 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
714 void schDlHqEntDelete(SchUeCb *ueCb);
716 /*UL HARQ Functions*/
717 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
718 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
719 void schUlHqProcessNack(SchUlHqProcCb *hqP);
720 void schUlHqProcessAck(SchUlHqProcCb *hqP);
721 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
722 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
723 void schUlHqEntDelete(SchUeCb *ueCb);
725 /* UE Manager HARQ Fun*/
726 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
728 /* Round Robbin Scheduler funtions*/
729 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
730 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
731 void schMsg4Complete(SchUeCb *ueCb);
732 /**********************************************************************
734 **********************************************************************/