1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 typedef struct schCellCb SchCellCb;
63 typedef struct schUeCb SchUeCb;
76 SCH_UE_STATE_INACTIVE,
82 SCH_LC_STATE_INACTIVE,
95 * Structure holding LTE MAC's General Configuration information.
97 typedef struct schGenCb
99 uint8_t tmrRes; /*!< Timer resolution */
100 uint8_t startCellId; /*!< Starting Cell Id */
102 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
103 of RLC control BO and SRB BO on
104 PCell. val 0 means don't force*/
105 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
109 typedef struct freePrbBlock
118 * PRB allocations for a symbol within a slot
120 typedef struct schPrbAlloc
122 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
123 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
128 * scheduler allocationsfor DL per cell.
130 typedef struct schDlSlotInfo
132 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
133 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
134 uint8_t ssbIdxSupported; /*!< Max SSB index */
135 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
136 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
137 RarAlloc *rarAlloc; /*!< RAR allocation */
138 DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
141 typedef struct schRaCb
148 * scheduler allocationsfor UL per cell.
150 typedef struct schUlSlotInfo
152 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
153 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
154 bool puschPres; /*!< PUSCH presence field */
155 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
156 bool pucchPres; /*!< PUCCH presence field */
157 SchPucchInfo schPucchInfo; /*!< PUCCH info */
162 * BSR info per slot per UE.
164 typedef struct bsrInfo
166 uint8_t priority; /* CG priority */
167 uint32_t dataVol; /* Data volume requested in bytes */
170 typedef struct schLcCtxt
172 uint8_t lcId; // logical Channel ID
173 uint8_t lcp; // logical Channel Prioritization
176 uint16_t pduSessionId; /*Pdu Session Id*/
177 Snssai *snssai; /*S-NSSAI assoc with LCID*/
180 typedef struct schDlCb
183 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
186 typedef struct schUlLcCtxt
193 uint8_t pbr; // prioritisedBitRate
194 uint8_t bsd; // bucketSizeDuration
195 uint16_t pduSessionId; /*Pdu Session Id*/
196 Snssai *snssai; /*S-NSSAI assoc with LCID*/
199 typedef struct schUlCb
202 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
205 typedef struct schUeCfgCb
209 bool macCellGrpCfgPres;
210 SchMacCellGrpCfg macCellGrpCfg;
211 bool phyCellGrpCfgPres;
212 SchPhyCellGrpCfg phyCellGrpCfg;
214 SchSpCellCfg spCellCfg;
216 SchModulationInfo dlModInfo;
217 SchModulationInfo ulModInfo;
224 typedef struct schUeCb
232 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
241 typedef struct schRaReq
244 RachIndInfo *rachInd;
245 SlotTimingInfo winStartTime;
246 SlotTimingInfo winEndTime;
251 * Cell Control block per cell.
253 typedef struct schCellCb
255 uint16_t cellId; /*!< Cell ID */
256 Inst instIdx; /*!< Index of the scheduler instance */
257 Inst macInst; /*!< Index of the MAC instance */
258 uint8_t numSlots; /*!< Number of slots in current frame */
259 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
260 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
261 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
262 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
263 bool firstSsbTransmitted;
264 bool firstSib1Transmitted;
265 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
266 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
267 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
268 uint16_t numActvUe; /*!<Number of active UEs */
269 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
270 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
271 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
273 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
274 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
275 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
281 * Control block for sch
285 TskInit schInit; /*!< Task Init info */
286 SchGenCb genCfg; /*!< General Config info */
287 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
288 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
289 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
292 /* Declaration for scheduler control blocks */
293 SchCb schCb[SCH_MAX_INST];
295 /* function declarations */
296 short int schActvTmr(Ent ent,Inst inst);
298 /* Configuration related function declarations */
299 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
300 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
301 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
302 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
303 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
304 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
305 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
306 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
308 /* Incoming message handler function declarations */
309 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
310 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
312 /* DL scheduling related function declarations */
313 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
314 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
315 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
316 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
317 void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
318 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueIdx, RarAlloc *rarAlloc, uint8_t k0Index);
319 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo slotTime, DlMsgAlloc *msg4Alloc);
320 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
321 uint32_t *accumalatedSize, DlMsgAlloc *dlMsgAlloc);
322 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
323 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
324 uint16_t *startPrb, uint16_t numPrb);
326 /* UL scheduling related function declarations */
327 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
328 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
329 uint8_t schCalcPrachNumRb(SchCellCb *cell);
330 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
331 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
332 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
333 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo pdcchSlotTime, uint32_t dataVol, SchPuschInfo *puschInfo);
334 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
335 uint16_t *startPrb, uint16_t numPrb);
337 /**********************************************************************
339 **********************************************************************/