1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
29 #define MAX_NUM_RB 275 /* value for numerology 1, 100 MHz */
31 #define MAX_NUM_RB 106 /* value for numerology 0, 20 MHz */
33 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
34 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
35 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
36 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
37 #define SCH_SYMBOL_PER_SLOT 14
38 #define SCH_SSB_NUM_SYMB 4
39 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
44 #define PDSCH_START_RB 10
45 /* Considering pdsch region from 3 to 13, DMRS exclued.
46 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
47 #define NUM_PDSCH_SYMBOL 11
48 #define PUSCH_START_RB 15
49 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
50 #define SI_RNTI 0xFFFF
52 #define DMRS_MAP_TYPE_A 1
53 #define NUM_DMRS_SYMBOLS 1
54 #define DMRS_ADDITIONAL_POS 0
55 #define SCH_DEFAULT_K1 1
56 #define SCH_TQ_SIZE 10
57 #define SSB_IDX_SUPPORTED 1
62 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
63 #define UL_GRANT_SIZE 224
65 #define PRB_BITMAP_IDX_LEN 64
66 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
68 typedef struct schCellCb SchCellCb;
69 typedef struct schUeCb SchUeCb;
82 SCH_UE_STATE_INACTIVE,
88 SCH_LC_STATE_INACTIVE,
101 * Structure holding LTE MAC's General Configuration information.
103 typedef struct schGenCb
105 uint8_t tmrRes; /*!< Timer resolution */
106 uint8_t startCellId; /*!< Starting Cell Id */
108 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
109 of RLC control BO and SRB BO on
110 PCell. val 0 means don't force*/
111 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
115 typedef struct freePrbBlock
124 * PRB allocations for a symbol within a slot
126 typedef struct schPrbAlloc
128 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
129 uint64_t prbBitMap[SCH_SYMBOL_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
134 * scheduler allocationsfor DL per cell.
136 typedef struct schDlSlotInfo
138 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
139 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
140 uint8_t ssbIdxSupported; /*!< Max SSB index */
141 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
142 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
143 RarAlloc *rarAlloc; /*!< RAR allocation */
144 DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
147 typedef struct schRaCb
154 * scheduler allocationsfor UL per cell.
156 typedef struct schUlSlotInfo
158 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
159 uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */
160 bool puschPres; /*!< PUSCH presence field */
161 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
162 bool pucchPres; /*!< PUCCH presence field */
163 SchPucchInfo schPucchInfo; /*!< PUCCH info */
168 * BSR info per slot per UE.
170 typedef struct bsrInfo
172 uint8_t priority; /* CG priority */
173 uint32_t dataVol; /* Data volume requested in bytes */
176 typedef struct schLcCtxt
178 uint8_t lcId; // logical Channel ID
179 uint8_t lcp; // logical Channel Prioritization
182 uint16_t pduSessionId; /*Pdu Session Id*/
183 Snssai *snssai; /*S-NSSAI assoc with LCID*/
186 typedef struct schDlCb
189 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
192 typedef struct schUlLcCtxt
199 uint8_t pbr; // prioritisedBitRate
200 uint8_t bsd; // bucketSizeDuration
201 uint16_t pduSessionId; /*Pdu Session Id*/
202 Snssai *snssai; /*S-NSSAI assoc with LCID*/
205 typedef struct schUlCb
208 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
211 typedef struct schUeCfgCb
215 bool macCellGrpCfgPres;
216 SchMacCellGrpCfg macCellGrpCfg;
217 bool phyCellGrpCfgPres;
218 SchPhyCellGrpCfg phyCellGrpCfg;
220 SchSpCellCfg spCellCfg;
222 SchModulationInfo dlModInfo;
223 SchModulationInfo ulModInfo;
230 typedef struct schUeCb
238 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
247 typedef struct schRaReq
250 RachIndInfo *rachInd;
251 SlotTimingInfo winStartTime;
252 SlotTimingInfo winEndTime;
257 * Cell Control block per cell.
259 typedef struct schCellCb
261 uint16_t cellId; /*!< Cell ID */
262 Inst instIdx; /*!< Index of the scheduler instance */
263 Inst macInst; /*!< Index of the MAC instance */
264 uint8_t numSlots; /*!< Number of slots in current frame */
265 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
266 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
267 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
268 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
269 bool firstSsbTransmitted;
270 bool firstSib1Transmitted;
271 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
272 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
273 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
274 uint16_t numActvUe; /*!<Number of active UEs */
275 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
276 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
277 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
279 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
280 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
281 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
287 * Control block for sch
291 TskInit schInit; /*!< Task Init info */
292 SchGenCb genCfg; /*!< General Config info */
293 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
294 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
295 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
298 /* Declaration for scheduler control blocks */
299 SchCb schCb[SCH_MAX_INST];
301 /* function declarations */
302 short int schActvTmr(Ent ent,Inst inst);
304 /* Configuration related function declarations */
305 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
306 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
307 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
308 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
309 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
310 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
311 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
312 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
314 /* Incoming message handler function declarations */
315 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
316 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
318 /* DL scheduling related function declarations */
319 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
320 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
321 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
322 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
323 void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
324 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueIdx, RarAlloc *rarAlloc, uint8_t k0Index);
325 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo slotTime, DlMsgAlloc *msg4Alloc);
326 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
327 uint32_t *accumalatedSize, DlMsgAlloc *dlMsgAlloc);
328 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
330 /* UL scheduling related function declarations */
331 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
332 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
333 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
334 uint8_t schFillPuschAlloc(SchUeCb *ueCb, uint16_t pdcchSlot, uint32_t dataVol, SchPuschInfo *puschInfo);
335 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
336 uint16_t *startPrb, uint16_t numPrb);
338 /**********************************************************************
340 **********************************************************************/