1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 #define SCH_MAX_NUM_UL_HQ_PROC 16
63 #define SCH_MAX_NUM_DL_HQ_PROC 16
64 #define SCH_MAX_NUM_MSG3_TX 2
65 #define SCH_MAX_NUM_DL_HQ_TX 3
66 #define SCH_MAX_NUM_UL_HQ_TX 3
67 #define SCH_MAX_NUM_MSG4_TX 2
73 /* As per 38.331 the largest offset which can be used in of size 10240.
74 * But using this much size of array can cause memory related issue so thats why
75 * taking this size which are a multiple of the larger size */
76 #define MAX_DRX_SIZE 512
79 typedef struct schDlHqProcCb SchDlHqProcCb;
80 typedef struct schUlHqEnt SchUlHqEnt;
81 typedef struct schRaReq SchRaReq;
82 typedef struct schDlHqEnt SchDlHqEnt;
83 typedef struct schCellCb SchCellCb;
84 typedef struct schUeCb SchUeCb;
97 SCH_UE_STATE_INACTIVE,
99 SCH_UE_HANDIN_IN_PROGRESS
104 SCH_RA_STATE_MSG2_HANDLE,
105 SCH_RA_STATE_MSG3_PENDING,
106 SCH_RA_STATE_MSG4_PENDING,
107 SCH_RA_STATE_MSG4_DONE
112 SCH_LC_STATE_INACTIVE,
130 /*Following structures to keep record and estimations of PRB allocated for each
131 * LC taking into consideration the RRM policies*/
132 typedef struct lcInfo
134 uint8_t lcId; /*LCID for which BO are getting recorded*/
135 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
136 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
137 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
140 typedef struct schLcPrbEstimate
142 /* TODO: For Multiple RRMPolicies, Make DedicatedLcInfo as array/Double Pointer
143 * and have separate DedLCInfo for each RRMPolcyMemberList*/
144 /* Dedicated LC List will be allocated, if any available*/
145 CmLListCp dedLcList; /*Contain LCInfo per RRMPolicy*/
146 CmLListCp defLcList; /*Linklist of LC assoc with Default S-NSSAI(s)*/
147 /* SharedPRB number can be used by any LC.
148 * Need to calculate in every Slot based on PRB availability*/
149 uint16_t sharedNumPrb;
151 typedef struct schUlHqTbCb
159 SchMcsTable mcsTable;
165 uint8_t cntrRetxAllocFail;
169 typedef struct schDlHqTbCb
182 uint8_t isAckNackDtx;
183 uint8_t cntrRetxAllocFail;
184 //InfUeTbInfo tbCompInfo;
189 typedef struct schDrxHarqCb
191 uint32_t rttExpIndex;
193 uint32_t retxStrtIndex;
194 CmLList *retxStrtNode;
195 uint32_t retxExpIndex;
196 CmLList *retxExpNode;
200 typedef struct schUlHqProcCb
202 uint8_t procId; /*!< HARQ Process ID */
204 uint8_t maxHqTxPerHqP;
210 SchLcPrbEstimate ulLcPrbEst; /*UL PRB Alloc Estimate among different LC*/
211 CmLList ulHqProcLink;
212 uint8_t puschResType; /* Resource allocation type */
213 uint16_t puschStartPrb;
214 uint16_t puschNumPrb;
215 uint8_t dmrsMappingType;
216 uint8_t nrOfDmrsSymbols;
218 SlotTimingInfo puschTime;
220 SchDrxHarqCb ulDrxHarqCb;
226 uint8_t procId; /*!< HARQ Process ID */
228 uint8_t maxHqTxPerHqP;
231 SchDlHqTbCb tbInfo[2];
233 SchLcPrbEstimate dlLcPrbEst; /*DL PRB Alloc Estimate among different LC*/
234 CmLList dlHqProcLink;
235 SlotTimingInfo pucchTime;
237 SchDrxHarqCb dlDrxHarqCb;
242 SchCellCb *cell; /*!< Contains the pointer to cell*/
243 SchUeCb *ue; /*!< Contains the pointer to ue*/
244 CmLListCp free; /*!< List of free HARQ processes */
245 CmLListCp inUse; /*!< List of in-use HARQ processes */
246 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
247 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
248 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
252 SchCellCb *cell; /*!< Contains the pointer to cell */
253 SchUeCb *ue; /*!< Contains the pointer to UE */
254 CmLListCp free; /*!< List of free HARQ processes */
255 CmLListCp inUse; /*!< List of in-use HARQ processes */
256 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
257 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
258 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
263 * Structure holding LTE MAC's General Configuration information.
265 typedef struct schGenCb
267 uint8_t tmrRes; /*!< Timer resolution */
268 uint8_t startCellId; /*!< Starting Cell Id */
270 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
271 of RLC control BO and SRB BO on
272 PCell. val 0 means don't force*/
273 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
277 typedef struct freePrbBlock
286 * PRB allocations for a symbol within a slot
288 typedef struct schPrbAlloc
290 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
291 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
296 * scheduler allocationsfor DL per cell.
298 typedef struct schDlSlotInfo
300 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
301 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
302 uint8_t ssbIdxSupported; /*!< Max SSB index */
303 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
304 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
305 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
306 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
307 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
309 DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
312 typedef struct schRaCb
317 uint16_t dlMsgPduLen;
318 SchUlHqProcCb msg3HqProc;
319 SchUlHqProcCb *retxMsg3HqProc;
327 * scheduler allocationsfor UL per cell.
329 typedef struct schUlSlotInfo
331 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
332 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
333 bool puschPres; /*!< PUSCH presence field */
334 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
335 bool pucchPres; /*!< PUCCH presence field */
336 SchPucchInfo schPucchInfo; /*!< PUCCH info */
337 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
338 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
343 * BSR info per slot per UE.
345 typedef struct bsrInfo
347 uint8_t priority; /* CG priority */
348 uint32_t dataVol; /* Data volume requested in bytes */
351 typedef struct schLcCtxt
353 uint8_t lcId; // logical Channel ID
354 uint8_t lcp; // logical Channel Prioritization
357 uint16_t pduSessionId; /*Pdu Session Id*/
358 Snssai *snssai; /*S-NSSAI assoc with LCID*/
359 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
360 uint16_t rsvdDedicatedPRB;
363 typedef struct schDlCb
365 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
368 typedef struct schUlLcCtxt
375 uint8_t pbr; // prioritisedBitRate
376 uint8_t bsd; // bucketSizeDuration
377 uint16_t pduSessionId; /*Pdu Session Id*/
378 Snssai *snssai; /*S-NSSAI assoc with LCID*/
379 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
380 uint16_t rsvdDedicatedPRB;
383 typedef struct schUlCb
385 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
388 typedef struct schUeCfgCb
393 bool macCellGrpCfgPres;
394 SchMacCellGrpCfg macCellGrpCfg;
395 bool phyCellGrpCfgPres;
396 SchPhyCellGrpCfg phyCellGrpCfg;
398 SchSpCellRecfg spCellCfg;
400 SchModulationInfo dlModInfo;
401 SchModulationInfo ulModInfo;
402 SchDataTransmission dataTransmissionAction;
405 typedef struct schHqDlMap
410 typedef struct schHqUlMap
416 typedef struct schDrxUeCb
418 bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */
419 bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */
420 uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/
421 uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/
422 uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/
423 uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */
424 uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */
425 uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */
426 uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */
427 uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/
428 uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/
429 uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/
430 uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/
431 bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */
432 uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/
433 bool shortCyclePresent; /* set this value if shortCycle is Present */
434 uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/
435 uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/
436 uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/
437 uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */
438 uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */
439 uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */
440 uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */
441 int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */
442 int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */
443 int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */
444 int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */
445 CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/
446 CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/
447 CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/
448 CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
455 typedef struct schUeCb
462 SchCfraResource cfraResource;
465 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
470 SchDlHqProcCb *msg4Proc;
471 SchDlHqProcCb *retxMsg4HqProc;
472 SchHqDlMap **hqDlmap;
473 SchHqUlMap **hqUlmap;
474 CmLListCp ulRetxHqList;
475 CmLListCp dlRetxHqList;
486 typedef struct schRaReq
489 RachIndInfo *rachInd;
491 SchUeCb *ueCb; /* Filled only if isCFRA = true */
492 SlotTimingInfo winStartTime;
493 SlotTimingInfo winEndTime;
496 typedef struct schPageInfo
498 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
499 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
500 SlotTimingInfo pageTxTime; /*Start Paging window*/
501 uint8_t mcs; /*MCS index*/
502 uint16_t msgLen; /*Pdu length */
503 uint8_t *pagePdu; /*RRC Page PDU bit string*/
506 typedef struct schPagingOcc
509 uint8_t pagingOccSlot;
512 typedef struct schPageCb
514 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
515 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
519 typedef struct schDrxCb
521 CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */
522 CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */
523 CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */
524 CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */
525 CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */
526 CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */
527 CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */
528 CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */
529 CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */
530 CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */
536 * Cell Control block per cell.
538 typedef struct schCellCb
540 uint16_t cellId; /*!< Cell ID */
541 Inst instIdx; /*!< Index of the scheduler instance */
542 Inst macInst; /*!< Index of the MAC instance */
543 uint16_t numSlots; /*!< Number of slots in current frame */
544 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
545 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
546 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
547 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
548 bool firstSsbTransmitted;
549 bool firstSib1Transmitted;
550 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
551 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
552 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
553 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
554 uint16_t numActvUe; /*!< Number of active UEs */
555 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
556 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
557 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
558 CmLListCp ueToBeScheduled; /*!< Linked list to store UEs pending to be scheduled, */
559 SchPageCb pageCb; /*!< Page Record at Schedular*/
561 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
562 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
563 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
566 SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
571 typedef struct schSliceCfg
573 uint8_t numOfSliceConfigured;
574 SchRrmPolicyOfSlice **listOfConfirguration;
579 * Control block for sch
583 TskInit schInit; /*!< Task Init info */
584 SchGenCb genCfg; /*!< General Config info */
585 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
586 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
587 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
588 SchSliceCfg sliceCfg;
591 /* Declaration for scheduler control blocks */
592 SchCb schCb[SCH_MAX_INST];
594 /* function declarations */
595 short int schActvTmr(Ent ent,Inst inst);
596 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
598 /* Configuration related function declarations */
599 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
600 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
601 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
602 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
603 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
604 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
605 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
606 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
607 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
609 /* Incoming message handler function declarations */
610 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
611 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
612 uint8_t schProcessCrcInd(CrcIndInfo *crcInd, Inst schInst);
614 /* DL scheduling related function declarations */
615 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
616 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
617 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
618 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
619 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
620 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
621 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
622 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
623 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP);
624 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgAlloc *msg4Alloc,\
625 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
626 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
627 uint16_t *startPrb, uint16_t numPrb);
628 void fillDlMsgInfo(DlMsgInfo *dlMsgInfo, uint8_t crnti, bool isRetx, SchDlHqProcCb* hqP);
629 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
630 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP);
631 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
632 /* UL scheduling related function declarations */
633 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
634 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
635 uint8_t schCalcPrachNumRb(SchCellCb *cell);
636 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
637 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP);
638 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
639 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
640 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
641 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
642 uint16_t *startPrb, uint16_t numPrb);
643 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
644 uint8_t schCalculateUlTbs(SchUeCb *ueCb, SlotTimingInfo puschTime, uint8_t symbLen,\
645 uint16_t *startPrb, uint32_t *totTBS, bool isRetx, SchUlHqProcCb *hqP);
647 /*Generic Functions*/
648 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
649 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
650 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
651 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
652 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
653 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
656 void schProcPagingCfg(SchCellCb *cell);
657 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
658 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
659 uint8_t schFillPagePdschCfg(SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingInfo slotTime, \
660 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
661 /*DL HARQ Functions*/
662 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
663 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
664 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
665 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
666 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
668 /*UL HARQ Functions*/
669 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
670 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
671 void schUlHqProcessNack(SchUlHqProcCb *hqP);
672 void schUlHqProcessAck(SchUlHqProcCb *hqP);
673 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
674 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
676 /* UE Manager HARQ Fun*/
677 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
679 /* Round Robbin Scheduler funtions*/
680 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
681 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
682 void schMsg4Complete(SchUeCb *ueCb);
683 /**********************************************************************
685 **********************************************************************/