1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
29 #define MAX_NUM_RB 275 /* value for numerology 1, 100 MHz */
31 #define MAX_NUM_RB 106 /* value for numerology 0, 20 MHz */
33 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
34 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
35 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
36 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
37 #define SCH_SYMBOL_PER_SLOT 14
38 #define SCH_SSB_NUM_SYMB 4
39 #define SCH_SSB_NUM_PRB 20
44 #define PUSCH_START_RB 15
45 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
46 #define SI_RNTI 0xFFFF
48 #define DMRS_MAP_TYPE_A 1
49 #define NUM_DMRS_SYMBOLS 1
50 #define DMRS_ADDITIONAL_POS 0
51 #define SCH_DEFAULT_K1 1
52 #define SCH_TQ_SIZE 10
57 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
58 #define UL_GRANT_SIZE 224
60 typedef struct schCellCb SchCellCb;
61 typedef struct schUeCb SchUeCb;
74 SCH_UE_STATE_INACTIVE,
80 SCH_LC_STATE_INACTIVE,
86 * Structure holding LTE MAC's General Configuration information.
88 typedef struct schGenCb
90 uint8_t tmrRes; /*!< Timer resolution */
91 uint8_t startCellId; /*!< Starting Cell Id */
93 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
94 of RLC control BO and SRB BO on
95 PCell. val 0 means don't force*/
96 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
102 * scheduler allocationsfor DL per cell.
104 typedef struct schDlSlotInfo
106 uint16_t totalPrb; /*!< Number of RBs in the cell */
107 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
108 uint16_t resAllocBitMap; /*!< Resource allocation bitmap */
109 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
110 uint8_t ssbIdxSupported; /*!< Max SSB index */
111 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
112 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
113 RarInfo *rarInfo; /*!< RAR info */
114 DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
117 typedef struct schRaCb
124 * scheduler allocationsfor UL per cell.
126 typedef struct schUlSlotInfo
128 uint16_t totalPrb; /*!< Number of RBs in the cell */
129 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
130 uint16_t resAllocBitMap; /*!< Resource allocation bitmap */
131 uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */
132 bool puschPres; /*!< PUSCH presence field */
133 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
134 bool pucchPres; /*!< PUCCH presence field */
135 SchPucchInfo schPucchInfo; /*!< PUCCH info */
140 * BSR info per slot per UE.
142 typedef struct bsrInfo
144 uint8_t priority; /* CG priority */
145 uint32_t dataVol; /* Data volume requested in bytes */
148 typedef struct schLcCtxt
150 uint8_t lcId; // logical Channel ID
151 uint8_t lcp; // logical Channel Prioritization
156 typedef struct schDlCb
159 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
162 typedef struct schUlLcCtxt
169 uint8_t pbr; // prioritisedBitRate
170 uint8_t bsd; // bucketSizeDuration
173 typedef struct schUlCb
176 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
179 typedef struct schUeCfgCb
183 bool macCellGrpCfgPres;
184 SchMacCellGrpCfg macCellGrpCfg;
185 bool phyCellGrpCfgPres;
186 SchPhyCellGrpCfg phyCellGrpCfg;
188 SchSpCellCfg spCellCfg;
190 SchModulationInfo dlModInfo;
191 SchModulationInfo ulModInfo;
198 typedef struct schUeCb
206 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
213 * Cell Control block per cell.
215 typedef struct schCellCb
217 uint16_t cellId; /*!< Cell ID */
218 Inst instIdx; /*!< Index of the scheduler instance */
219 Inst macInst; /*!< Index of the MAC instance */
220 uint8_t numSlots; /*!< Number of slots in current frame */
221 SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/
222 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
223 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
224 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
225 bool firstSsbTransmitted;
226 bool firstSib1Transmitted;
227 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
228 SchRaCb raCb[MAX_NUM_UE]; /*!< Rach Cb */
229 uint16_t numActvUe; /*!<Number of active UEs */
230 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
231 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
232 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
234 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
235 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
236 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
242 * Control block for sch
246 TskInit schInit; /*!< Task Init info */
247 SchGenCb genCfg; /*!< General Config info */
248 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
249 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
250 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
253 /* Declaration for scheduler control blocks */
254 SchCb schCb[SCH_MAX_INST];
256 /* function declarations */
257 short int schActvTmr(Ent ent,Inst inst);
258 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,uint16_t slot);
259 uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst inst);
260 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
261 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot);
262 uint16_t schCalcTbSize(uint32_t payLoadSize);
263 uint16_t schCalcNumPrb(uint16_t tbSize, uint16_t mcs, uint8_t numSymbols);
264 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
265 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
266 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
267 uint8_t schFillPuschAlloc(SchUeCb *ueCb, uint16_t pdcchSlot, uint32_t dataVol, SchPuschInfo *puschInfo);
268 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
269 uint32_t *accumalatedSize, uint16_t slot);
270 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
272 /**********************************************************************
274 **********************************************************************/