1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 typedef struct schCellCb SchCellCb;
63 typedef struct schUeCb SchUeCb;
76 SCH_UE_STATE_INACTIVE,
82 SCH_LC_STATE_INACTIVE,
108 * Structure holding LTE MAC's General Configuration information.
110 typedef struct schGenCb
112 uint8_t tmrRes; /*!< Timer resolution */
113 uint8_t startCellId; /*!< Starting Cell Id */
115 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
116 of RLC control BO and SRB BO on
117 PCell. val 0 means don't force*/
118 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
122 typedef struct freePrbBlock
131 * PRB allocations for a symbol within a slot
133 typedef struct schPrbAlloc
135 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
136 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
141 * scheduler allocationsfor DL per cell.
143 typedef struct schDlSlotInfo
145 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
146 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
147 uint8_t ssbIdxSupported; /*!< Max SSB index */
148 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
149 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
150 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
151 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
152 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
154 DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
157 typedef struct schRaCb
161 uint16_t dlMsgPduLen;
166 * scheduler allocationsfor UL per cell.
168 typedef struct schUlSlotInfo
170 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
171 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
172 bool puschPres; /*!< PUSCH presence field */
173 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
174 bool pucchPres; /*!< PUCCH presence field */
175 SchPucchInfo schPucchInfo; /*!< PUCCH info */
176 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
177 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
182 * BSR info per slot per UE.
184 typedef struct bsrInfo
186 uint8_t priority; /* CG priority */
187 uint32_t dataVol; /* Data volume requested in bytes */
190 typedef struct schLcCtxt
192 uint8_t lcId; // logical Channel ID
193 uint8_t lcp; // logical Channel Prioritization
196 uint16_t pduSessionId; /*Pdu Session Id*/
197 Snssai *snssai; /*S-NSSAI assoc with LCID*/
198 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
201 typedef struct schDlCb
203 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
206 typedef struct schUlLcCtxt
213 uint8_t pbr; // prioritisedBitRate
214 uint8_t bsd; // bucketSizeDuration
215 uint16_t pduSessionId; /*Pdu Session Id*/
216 Snssai *snssai; /*S-NSSAI assoc with LCID*/
217 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
220 typedef struct schUlCb
222 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
225 typedef struct schUeCfgCb
229 bool macCellGrpCfgPres;
230 SchMacCellGrpCfg macCellGrpCfg;
231 bool phyCellGrpCfgPres;
232 SchPhyCellGrpCfg phyCellGrpCfg;
234 SchSpCellCfg spCellCfg;
236 SchModulationInfo dlModInfo;
237 SchModulationInfo ulModInfo;
240 /*Following structures to keep record and estimations of PRB allocated for each
241 * LC taking into consideration the RRM policies*/
242 typedef struct lcInfo
244 uint8_t lcId; /*LCID for which BO are getting recorded*/
245 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
246 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
247 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
250 typedef struct dedicatedLCInfo
252 CmLListCp dedLcList; /*Linklist of LC assoc with RRMPolicyMemberList*/
253 uint16_t rsvdDedicatedPRB; /*Number of PRB reserved for this Dedicated S-NSSAI*/
256 typedef struct schLcPrbEstimate
258 /* TODO: For Multiple RRMPolicies, Make DedicatedLcInfo as array/Double Pointer
259 * and have separate DedLCInfo for each RRMPolcyMemberList*/
260 /* Dedicated LC List will be allocated, if any available*/
261 DedicatedLCInfo *dedLcInfo; /*Contain LCInfo per RRMPolicy*/
263 CmLListCp defLcList; /*Linklist of LC assoc with Default S-NSSAI(s)*/
265 /* SharedPRB number can be used by any LC.
266 * Need to calculate in every Slot based on PRB availability*/
267 uint16_t sharedNumPrb;
274 typedef struct schUeCb
283 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
286 SchLcPrbEstimate dlLcPrbEst; /*DL PRB Alloc Estimate among different LC*/
287 SchLcPrbEstimate ulLcPrbEst; /*UL PRB Alloc Estimate among different LC*/
294 typedef struct schRaReq
297 RachIndInfo *rachInd;
298 SlotTimingInfo winStartTime;
299 SlotTimingInfo winEndTime;
304 * Cell Control block per cell.
306 typedef struct schCellCb
308 uint16_t cellId; /*!< Cell ID */
309 Inst instIdx; /*!< Index of the scheduler instance */
310 Inst macInst; /*!< Index of the MAC instance */
311 uint8_t numSlots; /*!< Number of slots in current frame */
312 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
313 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
314 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
315 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
316 bool firstSsbTransmitted;
317 bool firstSib1Transmitted;
318 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
319 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
320 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
321 uint16_t numActvUe; /*!<Number of active UEs */
322 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
323 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
324 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
325 CmLListCp ueToBeScheduled; /*!<Linked list to store UEs pending to be scheduled, */
327 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
328 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
329 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
334 typedef struct schSliceCfg
336 uint8_t numOfSliceConfigured;
337 SchRrmPolicyOfSlice **listOfConfirguration;
342 * Control block for sch
346 TskInit schInit; /*!< Task Init info */
347 SchGenCb genCfg; /*!< General Config info */
348 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
349 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
350 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
351 SchSliceCfg sliceCfg;
354 /* Declaration for scheduler control blocks */
355 SchCb schCb[SCH_MAX_INST];
357 /* function declarations */
358 short int schActvTmr(Ent ent,Inst inst);
360 /* Configuration related function declarations */
361 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
362 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
363 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
364 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
365 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
366 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
367 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
368 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
369 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
371 /* Incoming message handler function declarations */
372 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
373 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
375 /* DL scheduling related function declarations */
376 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
377 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
378 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
379 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
380 bool schProcessRaReq(SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
381 bool schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId);
382 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueIdx, RarAlloc *rarAlloc, uint8_t k0Index);
383 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
384 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols);
385 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgAlloc *msg4Alloc,\
386 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols);
387 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
388 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
389 uint16_t *startPrb, uint16_t numPrb);
390 void fillDlMsgInfo(DlMsgInfo *dlMsgInfo, uint8_t crnti);
391 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
392 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime);
394 /* UL scheduling related function declarations */
395 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
396 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
397 uint8_t schCalcPrachNumRb(SchCellCb *cell);
398 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
399 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti);
400 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
401 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbsSize, \
402 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb);
403 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
404 uint16_t *startPrb, uint16_t numPrb);
405 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId);
406 bool schCalculateUlTbs(SchUeCb *ueCb, SlotTimingInfo puschTime, uint8_t symbLen,\
407 uint16_t *startPrb, uint32_t *totTBS);
409 /*Generic Functions*/
410 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
411 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
412 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLcLL action);
413 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
414 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
415 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
417 /**********************************************************************
419 **********************************************************************/