1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 #define SCH_MAX_NUM_UL_HQ_PROC 16
63 #define SCH_MAX_NUM_DL_HQ_PROC 16
64 #define SCH_MAX_NUM_MSG3_TX 2
65 #define SCH_MAX_NUM_DL_HQ_TX 3
66 #define SCH_MAX_NUM_UL_HQ_TX 3
67 #define SCH_MAX_NUM_MSG4_TX 2
71 #define ROOT_SEQ_LEN_1 139
72 #define ROOT_SEQ_LEN_2 839
75 /* As per 38.331 the largest offset which can be used in of size 10240.
76 * But using this much size of array can cause memory related issue so thats why
77 * taking this size which are a multiple of the larger size */
78 #define MAX_DRX_SIZE 512
81 #define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/
83 typedef struct schDlHqProcCb SchDlHqProcCb;
84 typedef struct schUlHqEnt SchUlHqEnt;
85 typedef struct schRaReq SchRaReq;
86 typedef struct schDlHqEnt SchDlHqEnt;
87 typedef struct schCellCb SchCellCb;
88 typedef struct schUeCb SchUeCb;
107 SCH_UE_STATE_INACTIVE,
109 SCH_UE_HANDIN_IN_PROGRESS
114 SCH_RA_STATE_MSG2_HANDLE,
115 SCH_RA_STATE_MSG3_PENDING,
116 SCH_RA_STATE_MSG4_PENDING,
117 SCH_RA_STATE_MSG4_DONE
122 SCH_LC_STATE_INACTIVE,
156 /*Following structures to keep record and estimations of PRB allocated for each
157 * LC taking into consideration the RRM policies*/
158 typedef struct lcInfo
160 uint8_t lcId; /*LCID for which BO are getting recorded*/
161 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
162 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
163 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
166 typedef struct schUlHqTbCb
174 SchMcsTable mcsTable;
180 uint8_t cntrRetxAllocFail;
184 typedef struct schDlHqTbCb
197 uint8_t isAckNackDtx;
198 uint8_t cntrRetxAllocFail;
199 //InfUeTbInfo tbCompInfo;
204 typedef struct schDrxHarqCb
206 uint32_t rttExpIndex;
208 uint32_t retxStrtIndex;
209 CmLList *retxStrtNode;
210 uint32_t retxExpIndex;
211 CmLList *retxExpNode;
215 typedef struct schUlHqProcCb
217 uint8_t procId; /*!< HARQ Process ID */
219 uint8_t maxHqTxPerHqP;
225 void *schSpcUlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
226 CmLList ulHqProcLink;
227 uint8_t puschResType; /*!< Resource allocation type */
228 uint16_t puschStartPrb;
229 uint16_t puschNumPrb;
230 uint8_t dmrsMappingType;
231 uint8_t nrOfDmrsSymbols;
233 SlotTimingInfo puschTime;
235 SchDrxHarqCb ulDrxHarqCb;
241 uint8_t procId; /*!< HARQ Process ID */
243 uint8_t maxHqTxPerHqP;
246 SchDlHqTbCb tbInfo[2];
248 void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
249 CmLList dlHqProcLink;
250 SlotTimingInfo pucchTime;
252 SchDrxHarqCb dlDrxHarqCb;
257 SchCellCb *cell; /*!< Contains the pointer to cell*/
258 SchUeCb *ue; /*!< Contains the pointer to ue*/
259 CmLListCp free; /*!< List of free HARQ processes */
260 CmLListCp inUse; /*!< List of in-use HARQ processes */
261 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
262 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
263 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
267 SchCellCb *cell; /*!< Contains the pointer to cell */
268 SchUeCb *ue; /*!< Contains the pointer to UE */
269 CmLListCp free; /*!< List of free HARQ processes */
270 CmLListCp inUse; /*!< List of in-use HARQ processes */
271 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
272 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
273 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
278 * Structure holding LTE MAC's General Configuration information.
280 typedef struct schGenCb
282 uint8_t tmrRes; /*!< Timer resolution */
283 uint8_t startCellId; /*!< Starting Cell Id */
285 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
286 of RLC control BO and SRB BO on
287 PCell. val 0 means don't force*/
288 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
292 typedef struct freePrbBlock
301 * PRB allocations for a symbol within a slot
303 typedef struct schPrbAlloc
305 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
306 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
311 * scheduler allocationsfor DL per cell.
313 typedef struct schDlSlotInfo
315 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
316 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
317 uint8_t ssbIdxSupported; /*!< Max SSB index */
318 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
319 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
320 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
321 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
322 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
324 DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
327 typedef struct schRaCb
332 uint16_t dlMsgPduLen;
333 SchUlHqProcCb msg3HqProc;
334 SchUlHqProcCb *retxMsg3HqProc;
342 * scheduler allocationsfor UL per cell.
344 typedef struct schUlSlotInfo
346 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
347 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
348 bool puschPres; /*!< PUSCH presence field */
349 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
350 bool pucchPres; /*!< PUCCH presence field */
351 SchPucchInfo schPucchInfo; /*!< PUCCH info */
352 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
353 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
358 * BSR info per slot per UE.
360 typedef struct bsrInfo
362 uint8_t priority; /* CG priority */
363 uint32_t dataVol; /* Data volume requested in bytes */
366 typedef struct schLcCtxt
368 uint8_t lcId; // logical Channel ID
369 uint8_t lcp; // logical Channel Prioritization
372 uint16_t pduSessionId; /*Pdu Session Id*/
373 Snssai *snssai; /*S-NSSAI assoc with LCID*/
374 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
375 uint16_t rsvdDedicatedPRB;
378 typedef struct schDlCb
380 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
383 typedef struct schUlLcCtxt
390 uint8_t pbr; // prioritisedBitRate
391 uint8_t bsd; // bucketSizeDuration
392 uint16_t pduSessionId; /*Pdu Session Id*/
393 Snssai *snssai; /*S-NSSAI assoc with LCID*/
394 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
395 uint16_t rsvdDedicatedPRB;
398 typedef struct schUlCb
400 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
403 typedef struct schUeCfgCb
408 bool macCellGrpCfgPres;
409 SchMacCellGrpCfg macCellGrpCfg;
410 bool phyCellGrpCfgPres;
411 SchPhyCellGrpCfg phyCellGrpCfg;
413 SchSpCellRecfg spCellCfg;
415 SchModulationInfo dlModInfo;
416 SchModulationInfo ulModInfo;
417 SchDataTransmission dataTransmissionAction;
420 typedef struct schHqDlMap
425 typedef struct schHqUlMap
431 typedef struct schDrxUeCb
433 bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */
434 bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */
435 uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/
436 uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/
437 uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/
438 uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */
439 uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */
440 uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */
441 uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */
442 uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/
443 uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/
444 uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/
445 uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/
446 bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */
447 uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/
448 bool shortCyclePresent; /* set this value if shortCycle is Present */
449 uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/
450 uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/
451 uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/
452 uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */
453 uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */
454 uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */
455 uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */
456 int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */
457 int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */
458 int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */
459 int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */
460 CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/
461 CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/
462 CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/
463 CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
470 typedef struct schUeCb
477 SchCfraResource cfraResource;
480 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
485 SchDlHqProcCb *msg4HqProc;
486 SchDlHqProcCb *retxMsg4HqProc;
487 SchHqDlMap **hqDlmap;
488 SchHqUlMap **hqUlmap;
495 SchK0K1TimingInfoTbl k0K1InfoTbl;
497 SchK2TimingInfoTbl k2InfoTbl;
504 typedef struct schRaReq
507 RachIndInfo *rachInd;
509 SchUeCb *ueCb; /* Filled only if isCFRA = true */
510 SlotTimingInfo winStartTime;
511 SlotTimingInfo winEndTime;
514 typedef struct schPageInfo
516 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
517 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
518 SlotTimingInfo pageTxTime; /*Start Paging window*/
519 uint8_t mcs; /*MCS index*/
520 uint16_t msgLen; /*Pdu length */
521 uint8_t *pagePdu; /*RRC Page PDU bit string*/
524 typedef struct schPagingOcc
527 uint8_t pagingOccSlot;
530 typedef struct schPageCb
532 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
533 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
537 typedef struct schDrxCb
539 CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */
540 CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */
541 CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */
542 CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */
543 CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */
544 CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */
545 CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */
546 CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */
547 CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */
548 CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */
552 typedef struct schAllApis
554 uint8_t (* SchCellCfgReq)(SchCellCb *cellCb);
555 void (* SchCellDeleteReq)(SchCellCb *cellCb);
556 uint8_t (* SchAddUeConfigReq)(SchUeCb *ueCb);
557 void (* SchModUeConfigReq)(SchUeCb *ueCb);
558 void (* SchUeDeleteReq)(SchUeCb *ueCb);
559 void (* SchDlHarqInd)();
560 void (* SchPagingInd)();
561 void (* SchRachRsrcReq)();
562 void (* SchRachRsrcRel)();
563 void (* SchCrcInd)(SchCellCb *cellCb, uint16_t ueId);
564 void (* SchRachInd)(SchCellCb *cellCb, uint16_t ueId);
565 void (* SchDlRlcBoInfo)(SchCellCb *cellCb, uint16_t ueId);
566 void (* SchSrUciInd)(SchCellCb *cellCb, uint16_t ueId);
567 void (* SchBsr)(SchCellCb *cellCb, uint16_t ueId);
568 void (* SchHandleLcList)(void *ptr, CmLList *node, ActionTypeLL action);
569 void (* SchAddToDlHqRetxList)(SchDlHqProcCb *hqP);
570 void (* SchAddToUlHqRetxList)(SchUlHqProcCb *hqP);
571 void (* SchRemoveFrmDlHqRetxList)(SchUeCb *ueCb, CmLList *node);
572 void (* SchRemoveFrmUlHqRetxList)(SchUeCb *ueCb, CmLList *node);
573 uint8_t (* SchAddUeToSchedule)(SchCellCb *cellCb, uint16_t ueId);
574 void (* SchRemoveUeFrmScheduleLst)(SchCellCb *cell, CmLList *node);
575 uint8_t (* SchInitDlHqProcCb)(SchDlHqProcCb *hqP);
576 uint8_t (* SchInitUlHqProcCb)(SchUlHqProcCb *hqP);
577 void (* SchFreeDlHqProcCb)(SchDlHqProcCb *hqP);
578 void (* SchFreeUlHqProcCb)(SchUlHqProcCb *hqP);
579 void (* SchDeleteDlHqProcCb)(SchDlHqProcCb *hqP);
580 void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP);
581 void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst);
582 uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \
583 uint16_t *startPrb, bool isRetx, SchDlHqProcCb **hqP);
584 uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \
585 uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP);
588 typedef struct schHqCfgParam
590 uint8_t maxDlDataHqTx;
592 uint8_t maxUlDataHqTx;
597 /* parameters derived in scheduler */
600 PdcchCfg sib1PdcchCfg;
601 PdschCfg sib1PdschCfg;
606 * Cell Control block per cell.
608 typedef struct schCellCb
610 uint16_t cellId; /*!< Cell ID */
611 Inst instIdx; /*!< Index of the scheduler instance */
612 Inst macInst; /*!< Index of the MAC instance */
613 uint16_t numSlots; /*!< Number of slots in current frame */
614 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
615 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
616 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
617 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
618 bool firstSsbTransmitted;
619 bool firstSib1Transmitted;
620 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
621 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
622 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
623 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
624 uint16_t numActvUe; /*!< Number of active UEs */
625 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
626 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
627 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
628 SchPageCb pageCb; /*!< Page Record at Schedular*/
630 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
631 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
632 SchSymbolConfig slotCfg[MAX_TDD_PERIODICITY_SLOTS][MAX_SYMB_PER_SLOT];
635 SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
637 SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/
638 SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/
639 void *schSpcCell; /*Ref of Scheduler specific structure*/
641 SchK0K1TimingInfoTbl k0K1InfoTbl;
642 SchK2TimingInfoTbl msg3K2InfoTbl;
643 SchK2TimingInfoTbl k2InfoTbl;
644 SchSib1Cfg sib1SchCfg; /* SIB1 config */
645 uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/
651 * Control block for sch
655 TskInit schInit; /*!< Task Init info */
656 SchGenCb genCfg; /*!< General Config info */
657 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
658 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
659 SchAllApis allApis[NUM_SCH_TYPE]; /*!<List of All Scheduler Type dependent Function pointers*/
660 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
661 CmLListCp sliceCfg; /* Linklist to Store Slice configuration */
664 /* Declaration for scheduler control blocks */
665 SchCb schCb[SCH_MAX_INST];
667 /* function declarations */
668 short int schActvTmr(Ent ent,Inst inst);
669 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
671 /* Configuration related function declarations */
672 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
673 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
674 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
675 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
676 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
677 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
678 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
679 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
680 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
682 /* Incoming message handler function declarations */
683 uint8_t SchProcCellCfgReq(Pst *pst, SchCellCfg *schCellCfg);
684 uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd);
685 uint8_t SchProcRachInd(Pst *pst, RachIndInfo *rachInd);
686 uint8_t SchProcCrcInd(Pst *pst, CrcIndInfo *crcInd);
687 uint8_t SchProcUlCqiInd(Pst *pst, SchUlCqiInd *ulCqiInd);
688 uint8_t SchProcDlCqiInd(Pst *pst, SchDlCqiInd *dlCqiInd);
689 uint8_t SchProcPhrInd(Pst *pst, SchPwrHeadroomInd *schPhrInd);
690 uint8_t SchProcDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo);
691 uint8_t SchAddUeConfigReq(Pst *pst, SchUeCfgReq *ueCfgToSch);
692 uint8_t SchProcBsr(Pst *pst, UlBufferStatusRptInd *bsrInd);
693 uint8_t SchProcSrUciInd(Pst *pst, SrUciIndInfo *uciInd);
694 uint8_t SchModUeConfigReq(Pst *pst, SchUeRecfgReq *ueRecfgToSch);
695 uint8_t SchProcUeDeleteReq(Pst *pst, SchUeDelete *ueDelete);
696 uint8_t SchProcCellDeleteReq(Pst *pst, SchCellDeleteReq *schCellDelete);
697 uint8_t SchProcSliceCfgReq(Pst *pst, SchSliceCfgReq *schSliceCfgReq);
698 uint8_t SchProcSliceRecfgReq(Pst *pst, SchSliceRecfgReq *schSliceRecfgReq);
699 uint8_t SchProcRachRsrcReq(Pst *pst, SchRachRsrcReq *schRachRsrcReq);
700 uint8_t SchProcRachRsrcRel(Pst *pst, SchRachRsrcRel *schRachRsrcRel);
701 uint8_t SchProcPagingInd(Pst *pst, SchPageInd *pageInd);
702 uint8_t SchProcDlHarqInd(Pst *pst, DlHarqInd *dlHarqInd);
704 /* DL scheduling related function declarations */
705 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
706 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
707 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
708 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
709 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
710 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
711 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
712 bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchDlHqProcCb **hqP);
713 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
714 uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP);
715 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgSchInfo *msg4Alloc,\
716 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
717 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
718 uint16_t *startPrb, uint16_t numPrb);
719 void fillDlMsgInfo(DlMsgSchInfo *dlMsgInfo, uint16_t crnti, bool isRetx, SchDlHqProcCb* hqP); /*AS per 38.473 V15.3.0, Section 9.3.1.32 crnti value range is b/w 0..65535*/
720 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
721 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP);
722 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
724 /* UL scheduling related function declarations */
725 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
726 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
727 uint8_t schCalcPrachNumRb(SchCellCb *cell);
728 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
729 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP);
730 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
731 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
732 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
733 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
734 uint16_t *startPrb, uint16_t numPrb);
735 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
737 /*Generic Functions*/
738 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgSchInfo *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
739 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
740 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
741 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
742 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
743 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
746 void schProcPagingCfg(SchCellCb *cell);
747 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
748 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
749 uint8_t schFillPagePdschCfg(SchCellCb *cell, PageDlSch *pageDlSch, SlotTimingInfo slotTime, \
750 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
751 /*DL HARQ Functions*/
752 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
753 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
754 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
755 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
756 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
757 void schDlHqEntDelete(SchUeCb *ueCb);
759 /*UL HARQ Functions*/
760 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
761 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
762 void schUlHqProcessNack(SchUlHqProcCb *hqP);
763 void schUlHqProcessAck(SchUlHqProcCb *hqP);
764 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
765 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
766 void schUlHqEntDelete(SchUeCb *ueCb);
768 /* UE Manager HARQ Fun*/
769 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
771 /* Round Robbin Scheduler funtions*/
772 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
773 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
774 void schMsg4Complete(SchUeCb *ueCb);
775 /**********************************************************************
777 **********************************************************************/