1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define MAX_NUM_RB 106 /* value for numerology 0 15Khz */
29 #define SCH_MIB_TRANS 80
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SYMBOL_PER_SLOT 14
33 #define SCH_SSB_NUM_SYMB 4
34 #define SCH_SSB_NUM_PRB 20
39 #define PUSCH_START_RB 15
40 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
41 #define SI_RNTI 0xFFFF
43 #define DMRS_MAP_TYPE_A 1
44 #define NUM_DMRS_SYMBOLS 12
45 #define DMRS_ADDITIONAL_POS 2
46 #define SCH_DEFAULT_K1 1
51 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
52 #define UL_GRANT_SIZE 224
54 typedef struct schCellCb SchCellCb;
55 typedef struct schUeCb SchUeCb;
68 SCH_UE_STATE_INACTIVE,
74 SCH_LC_STATE_INACTIVE,
80 * Structure holding LTE MAC's General Configuration information.
82 typedef struct schGenCb
84 uint8_t tmrRes; /*!< Timer resolution */
85 uint8_t startCellId; /*!< Starting Cell Id */
87 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
88 of RLC control BO and SRB BO on
89 PCell. val 0 means don't force*/
90 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
96 * scheduler allocationsfor DL per cell.
98 typedef struct schDlSlotInfo
100 uint16_t totalPrb; /*!< Number of RBs in the cell */
101 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
102 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
103 uint8_t ssbIdxSupported; /*!< Max SSB index */
104 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
105 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
106 RarInfo *rarInfo; /*!< RAR info */
107 DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
110 typedef struct schRaCb
117 * scheduler allocationsfor UL per cell.
119 typedef struct schUlSlotInfo
121 uint16_t totalPrb; /*!< Number of RBs in the cell */
122 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
123 uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */
124 bool puschPres; /*!< PUSCH presence field */
125 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
126 bool pucchPres; /*!< PUCCH presence field */
127 SchPucchInfo schPucchInfo; /*!< PUCCH info */
132 * BSR info per slot per UE.
134 typedef struct bsrInfo
136 uint8_t priority; /* CG priority */
137 uint32_t dataVol; /* Data volume requested in bytes */
140 typedef struct schLcCtxt
142 uint8_t lcId; // logical Channel ID
143 uint8_t lcp; // logical Channel Prioritization
148 typedef struct schDlCb
151 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
154 typedef struct schUlLcCtxt
161 uint8_t pbr; // prioritisedBitRate
162 uint8_t bsd; // bucketSizeDuration
165 typedef struct schUlCb
168 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
175 typedef struct schUeCb
183 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
190 * Cell Control block per cell.
192 typedef struct schCellCb
194 uint16_t cellId; /*!< Cell ID */
195 Inst instIdx; /*!< Index of the scheduler instance */
196 Inst macInst; /*!< Index of the MAC instance */
197 uint8_t numSlots; /*!< Number of slots in current frame */
198 SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/
199 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
200 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
201 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
202 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
203 SchRaCb raCb[MAX_NUM_UE]; /*!< Rach Cb */
204 uint16_t numActvUe; /*!<Number of active UEs */
205 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
206 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
207 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
209 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
210 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
211 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
217 * Control block for sch
221 TskInit schInit; /*!< Task Init info */
222 SchGenCb genCfg; /*!< General Config info */
223 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
226 /* Declaration for scheduler control blocks */
227 SchCb schCb[SCH_MAX_INST];
229 /* function declarations */
230 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,uint16_t slot);
231 uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst inst);
232 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
233 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot);
234 uint16_t schCalcTbSize(uint16_t payLoadSize);
235 uint16_t schCalcNumPrb(uint16_t tbSize, uint16_t mcs, uint8_t numSymbols);
236 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
237 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
238 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
239 uint8_t schFillPuschAlloc(SchUeCb *ueCb, uint16_t pdcchSlot, uint32_t dataVol, SchPuschInfo *puschInfo);
240 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
241 uint16_t accumalatedSize, uint16_t slot);
242 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
244 /**********************************************************************
246 **********************************************************************/