1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
29 #define MAX_NUM_RB 275 /* value for numerology 1, 100 MHz */
31 #define MAX_NUM_RB 106 /* value for numerology 0, 20 MHz */
33 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
34 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
35 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
36 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
37 #define SCH_SYMBOL_PER_SLOT 14
38 #define SCH_SSB_NUM_SYMB 4
39 #define SCH_SSB_NUM_PRB 20
44 #define PDSCH_START_RB 10
45 #define PUSCH_START_RB 15
46 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
47 #define SI_RNTI 0xFFFF
49 #define DMRS_MAP_TYPE_A 1
50 #define NUM_DMRS_SYMBOLS 1
51 #define DMRS_ADDITIONAL_POS 0
52 #define SCH_DEFAULT_K1 1
53 #define SCH_TQ_SIZE 10
54 #define SSB_IDX_SUPPORTED 1
59 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
60 #define UL_GRANT_SIZE 224
62 typedef struct schCellCb SchCellCb;
63 typedef struct schUeCb SchUeCb;
76 SCH_UE_STATE_INACTIVE,
82 SCH_LC_STATE_INACTIVE,
95 * Structure holding LTE MAC's General Configuration information.
97 typedef struct schGenCb
99 uint8_t tmrRes; /*!< Timer resolution */
100 uint8_t startCellId; /*!< Starting Cell Id */
102 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
103 of RLC control BO and SRB BO on
104 PCell. val 0 means don't force*/
105 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
111 * scheduler allocationsfor DL per cell.
113 typedef struct schDlSlotInfo
115 uint16_t totalPrb; /*!< Number of RBs in the cell */
116 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
117 uint16_t resAllocBitMap; /*!< Resource allocation bitmap */
118 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
119 uint8_t ssbIdxSupported; /*!< Max SSB index */
120 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
121 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
122 RarAlloc *rarAlloc; /*!< RAR allocation */
123 DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
126 typedef struct schRaCb
133 * scheduler allocationsfor UL per cell.
135 typedef struct schUlSlotInfo
137 uint16_t totalPrb; /*!< Number of RBs in the cell */
138 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
139 uint16_t resAllocBitMap; /*!< Resource allocation bitmap */
140 uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */
141 bool puschPres; /*!< PUSCH presence field */
142 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
143 bool pucchPres; /*!< PUCCH presence field */
144 SchPucchInfo schPucchInfo; /*!< PUCCH info */
149 * BSR info per slot per UE.
151 typedef struct bsrInfo
153 uint8_t priority; /* CG priority */
154 uint32_t dataVol; /* Data volume requested in bytes */
157 typedef struct schLcCtxt
159 uint8_t lcId; // logical Channel ID
160 uint8_t lcp; // logical Channel Prioritization
163 uint16_t pduSessionId; /*Pdu Session Id*/
164 SchSnssai *snssai; /*S-NSSAI assoc with LCID*/
167 typedef struct schDlCb
170 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
173 typedef struct schUlLcCtxt
180 uint8_t pbr; // prioritisedBitRate
181 uint8_t bsd; // bucketSizeDuration
182 uint16_t pduSessionId; /*Pdu Session Id*/
183 SchSnssai *snssai; /*S-NSSAI assoc with LCID*/
186 typedef struct schUlCb
189 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
192 typedef struct schUeCfgCb
196 bool macCellGrpCfgPres;
197 SchMacCellGrpCfg macCellGrpCfg;
198 bool phyCellGrpCfgPres;
199 SchPhyCellGrpCfg phyCellGrpCfg;
201 SchSpCellCfg spCellCfg;
203 SchModulationInfo dlModInfo;
204 SchModulationInfo ulModInfo;
211 typedef struct schUeCb
219 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
228 typedef struct schRaReq
231 RachIndInfo *rachInd;
232 SlotTimingInfo winStartTime;
233 SlotTimingInfo winEndTime;
238 * Cell Control block per cell.
240 typedef struct schCellCb
242 uint16_t cellId; /*!< Cell ID */
243 Inst instIdx; /*!< Index of the scheduler instance */
244 Inst macInst; /*!< Index of the MAC instance */
245 uint8_t numSlots; /*!< Number of slots in current frame */
246 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
247 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
248 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
249 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
250 bool firstSsbTransmitted;
251 bool firstSib1Transmitted;
252 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
253 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
254 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
255 uint16_t numActvUe; /*!<Number of active UEs */
256 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
257 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
258 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
260 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
261 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
262 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
268 * Control block for sch
272 TskInit schInit; /*!< Task Init info */
273 SchGenCb genCfg; /*!< General Config info */
274 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
275 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
276 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
279 /* Declaration for scheduler control blocks */
280 SchCb schCb[SCH_MAX_INST];
282 /* function declarations */
283 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
284 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
285 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
286 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
287 short int schActvTmr(Ent ent,Inst inst);
288 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,uint16_t slot);
289 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
290 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
291 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot, bool ssbPresent, bool sib1Present);
292 uint16_t schCalcTbSize(uint32_t payLoadSize);
293 uint16_t schCalcNumPrb(uint16_t tbSize, uint16_t mcs, uint8_t numSymbols);
294 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
295 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
296 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
297 uint8_t schFillPuschAlloc(SchUeCb *ueCb, uint16_t pdcchSlot, uint32_t dataVol, SchPuschInfo *puschInfo);
298 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
299 uint32_t *accumalatedSize, uint16_t slot);
300 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
301 uint8_t schFillRar(RarAlloc *rarAlloc, uint16_t raRnti, uint16_t pci, uint8_t offsetPointA, \
302 uint8_t k0Index, bool ssbPresent, bool sib1Present);
303 void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
305 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
306 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
307 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
308 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
310 PduTxOccsaion schCheckSsbOcc(SlotTimingInfo slotTime, SchCellCb *cell);
311 PduTxOccsaion schCheckSib1Occ(SlotTimingInfo slotTime, SchCellCb *cell);
313 /**********************************************************************
315 **********************************************************************/