1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 typedef struct schCellCb SchCellCb;
63 typedef struct schUeCb SchUeCb;
76 SCH_UE_STATE_INACTIVE,
82 SCH_LC_STATE_INACTIVE,
102 * Structure holding LTE MAC's General Configuration information.
104 typedef struct schGenCb
106 uint8_t tmrRes; /*!< Timer resolution */
107 uint8_t startCellId; /*!< Starting Cell Id */
109 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
110 of RLC control BO and SRB BO on
111 PCell. val 0 means don't force*/
112 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
116 typedef struct freePrbBlock
125 * PRB allocations for a symbol within a slot
127 typedef struct schPrbAlloc
129 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
130 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
135 * scheduler allocationsfor DL per cell.
137 typedef struct schDlSlotInfo
139 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
140 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
141 uint8_t ssbIdxSupported; /*!< Max SSB index */
142 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
143 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
144 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
145 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
146 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
148 DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
151 typedef struct schRaCb
155 uint16_t dlMsgPduLen;
160 * scheduler allocationsfor UL per cell.
162 typedef struct schUlSlotInfo
164 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
165 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
166 bool puschPres; /*!< PUSCH presence field */
167 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
168 bool pucchPres; /*!< PUCCH presence field */
169 SchPucchInfo schPucchInfo; /*!< PUCCH info */
170 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
171 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
176 * BSR info per slot per UE.
178 typedef struct bsrInfo
180 uint8_t priority; /* CG priority */
181 uint32_t dataVol; /* Data volume requested in bytes */
184 typedef struct schLcCtxt
186 uint8_t lcId; // logical Channel ID
187 uint8_t lcp; // logical Channel Prioritization
190 uint16_t pduSessionId; /*Pdu Session Id*/
191 Snssai *snssai; /*S-NSSAI assoc with LCID*/
192 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
195 typedef struct schDlCb
197 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
200 typedef struct schUlLcCtxt
207 uint8_t pbr; // prioritisedBitRate
208 uint8_t bsd; // bucketSizeDuration
209 uint16_t pduSessionId; /*Pdu Session Id*/
210 Snssai *snssai; /*S-NSSAI assoc with LCID*/
211 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
214 typedef struct schUlCb
216 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
219 typedef struct schUeCfgCb
223 bool macCellGrpCfgPres;
224 SchMacCellGrpCfg macCellGrpCfg;
225 bool phyCellGrpCfgPres;
226 SchPhyCellGrpCfg phyCellGrpCfg;
228 SchSpCellCfg spCellCfg;
230 SchModulationInfo dlModInfo;
231 SchModulationInfo ulModInfo;
234 /*Following structures to keep record and estimations of PRB allocated for each
235 * LC taking into consideration the RRM policies*/
236 typedef struct lcInfo
238 uint8_t lcId; /*LCID for which BO are getting recorded*/
239 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
240 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
241 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
244 typedef struct dedicatedLCInfo
246 CmLListCp dedLcList; /*Linklist of LC assoc with RRMPolicyMemberList*/
247 uint16_t rsvdDedicatedPRB; /*Number of PRB reserved for this Dedicated S-NSSAI*/
250 typedef struct schLcPrbEstimate
252 /* TODO: For Multiple RRMPolicies, Make DedicatedLcInfo as array/Double Pointer
253 * and have separate DedLCInfo for each RRMPolcyMemberList*/
254 /* Dedicated LC List will be allocated, if any available*/
255 DedicatedLCInfo *dedLcInfo; /*Contain LCInfo per RRMPolicy*/
257 CmLListCp defLcList; /*Linklist of LC assoc with Default S-NSSAI(s)*/
259 /* SharedPRB number can be used by any LC.
260 * Need to calculate in every Slot based on PRB availability*/
261 uint16_t sharedNumPrb;
268 typedef struct schUeCb
277 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
280 SchLcPrbEstimate dlLcPrbEst; /*DL PRB Alloc Estimate among different LC*/
281 SchLcPrbEstimate ulLcPrbEst; /*UL PRB Alloc Estimate among different LC*/
288 typedef struct schRaReq
291 RachIndInfo *rachInd;
292 SlotTimingInfo winStartTime;
293 SlotTimingInfo winEndTime;
296 typedef struct schPageInfo
298 uint8_t pf; /*Value of Paging Frame received from DUAPP*/
299 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
300 SlotTimingInfo TxTime; /*Start Paging window*/
301 uint8_t crntSsbIdx; /*Counts the slot till totalSSB is receached*/
308 typedef struct schPagingOcc
311 uint8_t pagingOccSlot;
314 typedef struct schPageCb
316 CmLListCp pageReqInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
317 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
318 SchPageInfo currPageInfo; /*Page Req which is being currently processed */
323 * Cell Control block per cell.
325 typedef struct schCellCb
327 uint16_t cellId; /*!< Cell ID */
328 Inst instIdx; /*!< Index of the scheduler instance */
329 Inst macInst; /*!< Index of the MAC instance */
330 uint8_t numSlots; /*!< Number of slots in current frame */
331 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
332 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
333 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
334 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
335 bool firstSsbTransmitted;
336 bool firstSib1Transmitted;
337 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
338 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
339 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
340 uint16_t numActvUe; /*!<Number of active UEs */
341 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
342 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
343 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
344 CmLListCp ueToBeScheduled; /*!<Linked list to store UEs pending to be scheduled, */
345 SchPageCb pageCb; /*!<Page Record at Schedular*/
347 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
348 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
349 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
354 typedef struct schSliceCfg
356 uint8_t numOfSliceConfigured;
357 SchRrmPolicyOfSlice **listOfConfirguration;
362 * Control block for sch
366 TskInit schInit; /*!< Task Init info */
367 SchGenCb genCfg; /*!< General Config info */
368 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
369 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
370 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
371 SchSliceCfg sliceCfg;
374 /* Declaration for scheduler control blocks */
375 SchCb schCb[SCH_MAX_INST];
377 /* function declarations */
378 short int schActvTmr(Ent ent,Inst inst);
380 /* Configuration related function declarations */
381 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
382 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
383 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
384 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
385 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
386 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
387 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
388 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
389 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
391 /* Incoming message handler function declarations */
392 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
393 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
395 /* DL scheduling related function declarations */
396 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
397 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
398 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
399 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
400 bool schProcessRaReq(SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
401 bool schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId);
402 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
403 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
404 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols);
405 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgAlloc *msg4Alloc,\
406 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols);
407 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
408 uint16_t *startPrb, uint16_t numPrb);
409 void fillDlMsgInfo(DlMsgInfo *dlMsgInfo, uint8_t crnti);
410 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
411 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime);
413 /* UL scheduling related function declarations */
414 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
415 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
416 uint8_t schCalcPrachNumRb(SchCellCb *cell);
417 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
418 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti);
419 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
420 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbsSize, \
421 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb);
422 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
423 uint16_t *startPrb, uint16_t numPrb);
424 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId);
425 bool schCalculateUlTbs(SchUeCb *ueCb, SlotTimingInfo puschTime, uint8_t symbLen,\
426 uint16_t *startPrb, uint32_t *totTBS);
428 /*Generic Functions*/
429 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
430 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
431 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLcLL action);
432 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
433 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
434 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
437 void schProcPagingCfg(SchCellCb *cell);
438 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
439 /**********************************************************************
441 **********************************************************************/